Documentation/devicetree/bindings/mmc/sdhci-msm.txt

Qualcomm Standard Secure Digital Host Controller (SDHC)

Secure Digital Host Controller provides standard host interface to SD/MMC/SDIO cards.

Required properties:
  - compatible : should be "qcom,sdhci-msm"
  - reg : should contain SDHC, SD Core register map.
  - reg-names : indicates various resources passed to driver (via reg proptery) by name.
		Required "reg-names" are "hc_mem" and "core_mem"
  - interrupts : should contain SDHC interrupts.
  - interrupt-names : indicates interrupts passed to driver (via interrupts property) by name.
		      Required "interrupt-names" are "hc_irq" and "pwr_irq".
  - <supply-name>-supply: phandle to the regulator device tree node
			  Required "supply-name" are "vdd" and "vdd-io".
  - qcom,clk-rates: this is an array that specifies supported SDHC clock
		    frequencies for a slot, Units - Hz.

Required alias:
- The slot number is specified via an alias with the following format
	'sdhc{n}' where n is the slot number.

Optional Properties:
	- interrupt-names - "status_irq". This status_irq will be used for card
			     detection.
	- cd-gpios: specify GPIO for card detection. If this property is
		    defined, then it means SDHC device has more than one interrupt
		    parent and hence, it is required to define the following properties
		    to configure interrupts from multiple parents -

		    interrupt-parent - This must provide reference to the current
				       device node.
		    #address-cells - Should provide a value of 0.
		    interrupts - Should be <0 1 2> and it is an index to the
				 interrupt-map.
		    #interrupt-cells - should provide a value of 1.
		    #interrupt-mask - should provide a value of 0xffffffff.
		    interrupt-map - Must create mapping for the number of interrupts
				    that are defined in above interrupts property.
				    For SDHC device node, it must define 3 mappings for
				    hc_irq, pwr_irq and status_irq in the format
				    mentioned in below example node of sdhc_2.

	- qcom,bus-width - defines the bus I/O width that controller supports.
			   Units - number of bits. The valid bus-width values are
			   1, 4 and 8.
	- qcom,nonremovable - specifies whether the card in slot is
			      hot pluggable or hard wired.
	- qcom,bus-speed-mode - specifies supported bus speed modes by host.
				The supported bus speed modes are :
				"HS200_1p8v" - indicates that host can support HS200 at 1.8v.
				"HS200_1p2v" - indicates that host can support HS200 at 1.2v.
				"DDR_1p8v" - indicates that host can support DDR mode at 1.8v.
				"DDR_1p2v" - indicates that host can support DDR mode at 1.2v.
	- qcom,cpu-dma-latency-us: specifies acceptable DMA latency in microseconds. There is
				   no default value that the driver assumes if this property
				   is not specified. So if this property is not specified,
				   then SDHC driver will not vote for PM QOS.
        - qcom,dat1-mpm-int:    specifies MPM interrupt number (e.g. sdhc_2 node below)
				corresponding to DAT1 line of SDHC (used only if slot has dedicated
				DAT1 MSM pin (not GPIO))

In the following, <supply> can be vdd (flash core voltage) or vdd-io (I/O voltage).
	- qcom,<supply>-always-on - specifies whether supply should be kept "on" always.
	- qcom,<supply>-lpm_sup - specifies whether supply can be kept in low power mode (lpm).
	- qcom,<supply>-voltage_level - specifies voltage levels for supply. Should be
					specified in pairs (min, max), units uV.
	- qcom,<supply>-current_level - specifies load levels for supply in lpm or
					high power mode (hpm). Should be specified in
					pairs (lpm, hpm), units uA.

	- gpios - specifies gpios assigned for sdhc slot.
	- qcom,gpio-names -  a list of strings that map in order to the list of gpios

	A slot has either gpios or dedicated tlmm pins as represented below.
	- qcom,pad-pull-on - Active pull configuration for sdc tlmm pins
	- qcom,pad-pull-off - Suspend pull configuration for sdc tlmm pins.
	- qcom,pad-drv-on - Active drive strength configuration for sdc tlmm pins.
	- qcom,pad-drv-off - Suspend drive strength configuration for sdc tlmm pins.
	Tlmm pins are specified as <clk cmd data> and starting with eMMC5.0 as
	<clk cmd data rclk>

	- qcom,bus-bw-vectors-bps: specifies array of throughput values in
	Bytes/sec. The values in the array are determined according to
	supported bus speed modes. For example, if host supports SDR12 mode,
	value is 13631488 Bytes/sec.
	- Refer to "Documentation/devicetree/bindings/arm/msm/msm_bus.txt" for
	below optional properties:
	- qcom,msm-bus,name
	- qcom,msm-bus,num-cases
	- qcom,msm-bus,active-only
	- qcom,msm-bus,num-paths
	- qcom,msm-bus,vectors-KBps

Example:

	aliases {
		sdhc1 = &sdhc_1;
		sdhc2 = &sdhc_2;
	};

	sdhc_1: qcom,sdhc@f9824900 {
		compatible = "qcom,sdhci-msm";
                reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
                reg-names = "hc_mem", "core_mem";
                interrupts = <0 123 0>, <0 138 0>;
                interrupt-names = "hc_irq", "pwr_irq";

		vdd-supply = <&pm8941_l21>;
		vdd-io-supply = <&pm8941_l13>;
		qcom,vdd-voltage-level = <2950000 2950000>;
		qcom,vdd-current-level = <9000 800000>;

		qcom,vdd-io-always-on;
		qcom,vdd-io-lpm-sup;
		qcom,vdd-io-voltage-level = <1800000 2950000>;
		qcom,vdd-io-current-level = <6 22000>;

                qcom,bus-width = <4>;
		qcom,nonremovable;
		qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v";
		qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 200000000>;

		gpios = <&msmgpio 40 0>, /* CLK */
			<&msmgpio 39 0>, /* CMD */
			<&msmgpio 38 0>, /* DATA0 */
			<&msmgpio 37 0>, /* DATA1 */
			<&msmgpio 36 0>, /* DATA2 */
			<&msmgpio 35 0>; /* DATA3 */
		qcom,gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3";
	};

	sdhc_2: qcom,sdhc@f98a4900 {
		compatible = "qcom,sdhci-msm";
                reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
                reg-names = "hc_mem", "core_mem";

		#address-cells = <0>;
		interrupt-parent = <&sdhc_2>;
		interrupts = <0 1 2>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0xffffffff>;
		interrupt-map = <0 &intc 0 125 0
				1 &intc 0 221 0
				2 &msmgpio 62 0x3>;
                interrupt-names = "hc_irq", "pwr_irq", "status_irq";
		cd-gpios = <&msmgpio 62 0x1>;

		vdd-supply = <&pm8941_l21>;
		vdd-io-supply = <&pm8941_l13>;

                qcom,bus-width = <4>;
		qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 200000000>;

		qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
		qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
		qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */
		qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */

		qcom,cpu-dma-latency-us = <200>;
		qcom,msm-bus,name = "sdhc2";
		qcom,msm-bus,num-cases = <7>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps = <81 512 0 0>, /* No vote */
				<81 512 6656 13312>, /* 13 MB/s*/
				<81 512 13312 26624>, /* 26 MB/s */
				<81 512 26624 53248>, /* 52 MB/s */
				<81 512 53248 106496>, /* 104 MB/s */
				<81 512 106496 212992>, /* 208 MB/s */
				<81 512 2147483647 4294967295>; /* Max. bandwidth */
		qcom,bus-bw-vectors-bps = <0 13631488 27262976 54525952 109051904 218103808 4294967295>;
		qcom,dat1-mpm-int = <44>;
	};