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Linus Torvalds1da177e2005-04-16 15:20:36 -07001#ifndef __ASM_PARISC_PCI_H
2#define __ASM_PARISC_PCI_H
3
4#include <linux/config.h>
5#include <asm/scatterlist.h>
6
7
8
9/*
10** HP PCI platforms generally support multiple bus adapters.
11** (workstations 1-~4, servers 2-~32)
12**
13** Newer platforms number the busses across PCI bus adapters *sparsely*.
14** E.g. 0, 8, 16, ...
15**
16** Under a PCI bus, most HP platforms support PPBs up to two or three
17** levels deep. See "Bit3" product line.
18*/
19#define PCI_MAX_BUSSES 256
20
Helge Dellercb6fc182006-01-17 12:40:40 -070021
22/* To be used as: mdelay(pci_post_reset_delay);
23 *
24 * post_reset is the time the kernel should stall to prevent anyone from
25 * accessing the PCI bus once #RESET is de-asserted.
26 * PCI spec somewhere says 1 second but with multi-PCI bus systems,
27 * this makes the boot time much longer than necessary.
28 * 20ms seems to work for all the HP PCI implementations to date.
29 */
30#define pci_post_reset_delay 50
31
32
Linus Torvalds1da177e2005-04-16 15:20:36 -070033/*
34** pci_hba_data (aka H2P_OBJECT in HP/UX)
35**
36** This is the "common" or "base" data structure which HBA drivers
37** (eg Dino or LBA) are required to place at the top of their own
38** platform_data structure. I've heard this called "C inheritance" too.
39**
40** Data needed by pcibios layer belongs here.
41*/
42struct pci_hba_data {
43 void __iomem *base_addr; /* aka Host Physical Address */
44 const struct parisc_device *dev; /* device from PA bus walk */
45 struct pci_bus *hba_bus; /* primary PCI bus below HBA */
46 int hba_num; /* I/O port space access "key" */
47 struct resource bus_num; /* PCI bus numbers */
48 struct resource io_space; /* PIOP */
49 struct resource lmmio_space; /* bus addresses < 4Gb */
50 struct resource elmmio_space; /* additional bus addresses < 4Gb */
51 struct resource gmmio_space; /* bus addresses > 4Gb */
52
53 /* NOTE: Dino code assumes it can use *all* of the lmmio_space,
54 * elmmio_space and gmmio_space as a contiguous array of
55 * resources. This #define represents the array size */
56 #define DINO_MAX_LMMIO_RESOURCES 3
57
58 unsigned long lmmio_space_offset; /* CPU view - PCI view */
59 void * iommu; /* IOMMU this device is under */
60 /* REVISIT - spinlock to protect resources? */
61
62 #define HBA_NAME_SIZE 16
63 char io_name[HBA_NAME_SIZE];
64 char lmmio_name[HBA_NAME_SIZE];
65 char elmmio_name[HBA_NAME_SIZE];
66 char gmmio_name[HBA_NAME_SIZE];
67};
68
69#define HBA_DATA(d) ((struct pci_hba_data *) (d))
70
71/*
72** We support 2^16 I/O ports per HBA. These are set up in the form
73** 0xbbxxxx, where bb is the bus number and xxxx is the I/O port
74** space address.
75*/
76#define HBA_PORT_SPACE_BITS 16
77
78#define HBA_PORT_BASE(h) ((h) << HBA_PORT_SPACE_BITS)
79#define HBA_PORT_SPACE_SIZE (1UL << HBA_PORT_SPACE_BITS)
80
81#define PCI_PORT_HBA(a) ((a) >> HBA_PORT_SPACE_BITS)
82#define PCI_PORT_ADDR(a) ((a) & (HBA_PORT_SPACE_SIZE - 1))
83
Matthew Wilcox74d13f82005-10-21 22:49:05 -040084#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -070085#define PCI_F_EXTEND 0xffffffff00000000UL
86#define PCI_IS_LMMIO(hba,a) pci_is_lmmio(hba,a)
87
88/* We need to know if an address is LMMMIO or GMMIO.
89 * LMMIO requires mangling and GMMIO we must use as-is.
90 */
91static __inline__ int pci_is_lmmio(struct pci_hba_data *hba, unsigned long a)
92{
93 return(((a) & PCI_F_EXTEND) == PCI_F_EXTEND);
94}
95
96/*
97** Convert between PCI (IO_VIEW) addresses and processor (PA_VIEW) addresses.
Helge Dellercb6fc182006-01-17 12:40:40 -070098** See pci.c for more conversions used by Generic PCI code.
Grant Grundler9b9ff2e2006-01-10 20:48:00 -050099**
100** Platform characteristics/firmware guarantee that
101** (1) PA_VIEW - IO_VIEW = lmmio_offset for both LMMIO and ELMMIO
102** (2) PA_VIEW == IO_VIEW for GMMIO
Linus Torvalds1da177e2005-04-16 15:20:36 -0700103*/
104#define PCI_BUS_ADDR(hba,a) (PCI_IS_LMMIO(hba,a) \
105 ? ((a) - hba->lmmio_space_offset) /* mangle LMMIO */ \
106 : (a)) /* GMMIO */
Grant Grundler9b9ff2e2006-01-10 20:48:00 -0500107#define PCI_HOST_ADDR(hba,a) (((a) & PCI_F_EXTEND) == 0 \
108 ? (a) + hba->lmmio_space_offset \
109 : (a))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700110
111#else /* !CONFIG_64BIT */
112
113#define PCI_BUS_ADDR(hba,a) (a)
114#define PCI_HOST_ADDR(hba,a) (a)
115#define PCI_F_EXTEND 0UL
116#define PCI_IS_LMMIO(hba,a) (1) /* 32-bit doesn't support GMMIO */
117
118#endif /* !CONFIG_64BIT */
119
120/*
121** KLUGE: linux/pci.h include asm/pci.h BEFORE declaring struct pci_bus
122** (This eliminates some of the warnings).
123*/
124struct pci_bus;
125struct pci_dev;
126
127/*
128 * If the PCI device's view of memory is the same as the CPU's view of memory,
129 * PCI_DMA_BUS_IS_PHYS is true. The networking and block device layers use
130 * this boolean for bounce buffer decisions.
131 */
132#ifdef CONFIG_PA20
133/* All PA-2.0 machines have an IOMMU. */
134#define PCI_DMA_BUS_IS_PHYS 0
135#define parisc_has_iommu() do { } while (0)
136#else
137
138#if defined(CONFIG_IOMMU_CCIO) || defined(CONFIG_IOMMU_SBA)
139extern int parisc_bus_is_phys; /* in arch/parisc/kernel/setup.c */
140#define PCI_DMA_BUS_IS_PHYS parisc_bus_is_phys
141#define parisc_has_iommu() do { parisc_bus_is_phys = 0; } while (0)
142#else
143#define PCI_DMA_BUS_IS_PHYS 1
144#define parisc_has_iommu() do { } while (0)
145#endif
146
147#endif /* !CONFIG_PA20 */
148
149
150/*
151** Most PCI devices (eg Tulip, NCR720) also export the same registers
152** to both MMIO and I/O port space. Due to poor performance of I/O Port
153** access under HP PCI bus adapters, strongly reccomend use of MMIO
154** address space.
155**
156** While I'm at it more PA programming notes:
157**
158** 1) MMIO stores (writes) are posted operations. This means the processor
159** gets an "ACK" before the write actually gets to the device. A read
160** to the same device (or typically the bus adapter above it) will
161** force in-flight write transaction(s) out to the targeted device
162** before the read can complete.
163**
164** 2) The Programmed I/O (PIO) data may not always be strongly ordered with
165** respect to DMA on all platforms. Ie PIO data can reach the processor
166** before in-flight DMA reaches memory. Since most SMP PA platforms
167** are I/O coherent, it generally doesn't matter...but sometimes
168** it does.
169**
170** I've helped device driver writers debug both types of problems.
171*/
172struct pci_port_ops {
173 u8 (*inb) (struct pci_hba_data *hba, u16 port);
174 u16 (*inw) (struct pci_hba_data *hba, u16 port);
175 u32 (*inl) (struct pci_hba_data *hba, u16 port);
176 void (*outb) (struct pci_hba_data *hba, u16 port, u8 data);
177 void (*outw) (struct pci_hba_data *hba, u16 port, u16 data);
178 void (*outl) (struct pci_hba_data *hba, u16 port, u32 data);
179};
180
181
182struct pci_bios_ops {
183 void (*init)(void);
184 void (*fixup_bus)(struct pci_bus *bus);
185};
186
187/* pci_unmap_{single,page} is not a nop, thus... */
188#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \
189 dma_addr_t ADDR_NAME;
190#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \
191 __u32 LEN_NAME;
192#define pci_unmap_addr(PTR, ADDR_NAME) \
193 ((PTR)->ADDR_NAME)
194#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \
195 (((PTR)->ADDR_NAME) = (VAL))
196#define pci_unmap_len(PTR, LEN_NAME) \
197 ((PTR)->LEN_NAME)
198#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
199 (((PTR)->LEN_NAME) = (VAL))
200
201/*
202** Stuff declared in arch/parisc/kernel/pci.c
203*/
204extern struct pci_port_ops *pci_port;
205extern struct pci_bios_ops *pci_bios;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700206
207#ifdef CONFIG_PCI
208extern void pcibios_register_hba(struct pci_hba_data *);
209extern void pcibios_set_master(struct pci_dev *);
210#else
211extern inline void pcibios_register_hba(struct pci_hba_data *x)
212{
213}
214#endif
215
216/*
217 * pcibios_assign_all_busses() is used in drivers/pci/pci.c:pci_do_scan_bus()
218 * 0 == check if bridge is numbered before re-numbering.
219 * 1 == pci_do_scan_bus() should automatically number all PCI-PCI bridges.
220 *
221 * We *should* set this to zero for "legacy" platforms and one
222 * for PAT platforms.
223 *
224 * But legacy platforms also need to renumber the busses below a Host
225 * Bus controller. Adding a 4-port Tulip card on the first PCI root
226 * bus of a C200 resulted in the secondary bus being numbered as 1.
227 * The second PCI host bus controller's root bus had already been
228 * assigned bus number 1 by firmware and sysfs complained.
229 *
230 * Firmware isn't doing anything wrong here since each controller
231 * is its own PCI domain. It's simpler and easier for us to renumber
232 * the busses rather than treat each Dino as a separate PCI domain.
233 * Eventually, we may want to introduce PCI domains for Superdome or
234 * rp7420/8420 boxes and then revisit this issue.
235 */
236#define pcibios_assign_all_busses() (1)
237#define pcibios_scan_all_fns(a, b) (0)
238
239#define PCIBIOS_MIN_IO 0x10
240#define PCIBIOS_MIN_MEM 0x1000 /* NBPG - but pci/setup-res.c dies */
241
242/* Don't support DAC yet. */
243#define pci_dac_dma_supported(pci_dev, mask) (0)
244
245/* export the pci_ DMA API in terms of the dma_ one */
246#include <asm-generic/pci-dma-compat.h>
247
Andrew Mortonbb4a61b2005-06-06 23:07:46 -0700248#ifdef CONFIG_PCI
David S. Millere24c2d92005-06-02 12:55:50 -0700249static inline void pci_dma_burst_advice(struct pci_dev *pdev,
250 enum pci_dma_burst_strategy *strat,
251 unsigned long *strategy_parameter)
252{
253 unsigned long cacheline_size;
254 u8 byte;
255
256 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
257 if (byte == 0)
258 cacheline_size = 1024;
259 else
260 cacheline_size = (int) byte * 4;
261
262 *strat = PCI_DMA_BURST_MULTIPLE;
263 *strategy_parameter = cacheline_size;
264}
Andrew Mortonbb4a61b2005-06-06 23:07:46 -0700265#endif
David S. Millere24c2d92005-06-02 12:55:50 -0700266
Linus Torvalds1da177e2005-04-16 15:20:36 -0700267extern void
268pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
269 struct resource *res);
270
Dominik Brodowski43c34732005-08-04 18:06:21 -0700271extern void
272pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
273 struct pci_bus_region *region);
274
David S. Miller085ae412005-08-08 13:19:08 -0700275static inline struct resource *
276pcibios_select_root(struct pci_dev *pdev, struct resource *res)
277{
278 struct resource *root = NULL;
279
280 if (res->flags & IORESOURCE_IO)
281 root = &ioport_resource;
282 if (res->flags & IORESOURCE_MEM)
283 root = &iomem_resource;
284
285 return root;
286}
287
Linus Torvalds1da177e2005-04-16 15:20:36 -0700288static inline void pcibios_add_platform_entries(struct pci_dev *dev)
289{
290}
291
292#endif /* __ASM_PARISC_PCI_H */