Juergen Beisert | 80eedae | 2008-07-05 10:03:00 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. |
| 3 | */ |
| 4 | |
| 5 | /* |
| 6 | * The code contained herein is licensed under the GNU General Public |
| 7 | * License. You may obtain a copy of the GNU General Public License |
| 8 | * Version 2 or later at the following locations: |
| 9 | * |
| 10 | * http://www.opensource.org/licenses/gpl-license.html |
| 11 | * http://www.gnu.org/copyleft/gpl.html |
| 12 | */ |
| 13 | |
| 14 | #ifndef __ASM_ARCH_MXC_BOARD_MX27ADS_H__ |
| 15 | #define __ASM_ARCH_MXC_BOARD_MX27ADS_H__ |
| 16 | |
| 17 | /* external interrupt multiplexer */ |
Sascha Hauer | 9d631b8 | 2008-12-18 11:08:55 +0100 | [diff] [blame] | 18 | #define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START) |
Juergen Beisert | 80eedae | 2008-07-05 10:03:00 +0200 | [diff] [blame] | 19 | |
| 20 | #define MXC_VIRTUAL_INTS_BASE (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES) |
| 21 | #define MXC_SDIO1_CARD_IRQ MXC_VIRTUAL_INTS_BASE |
| 22 | #define MXC_SDIO2_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 1) |
| 23 | #define MXC_SDIO3_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 2) |
| 24 | |
| 25 | #define MXC_MAX_BOARD_INTS (MXC_MAX_EXP_IO_LINES + \ |
| 26 | MXC_MAX_VIRTUAL_INTS) |
| 27 | |
| 28 | /* |
| 29 | * MXC UART EVB board level configurations |
| 30 | */ |
Juergen Beisert | 80eedae | 2008-07-05 10:03:00 +0200 | [diff] [blame] | 31 | #define MXC_LL_UART_PADDR UART1_BASE_ADDR |
| 32 | #define MXC_LL_UART_VADDR AIPI_IO_ADDRESS(UART1_BASE_ADDR) |
| 33 | |
| 34 | /* |
| 35 | * @name Memory Size parameters |
| 36 | */ |
| 37 | |
| 38 | /* |
| 39 | * Size of SDRAM memory |
| 40 | */ |
| 41 | #define SDRAM_MEM_SIZE SZ_128M |
| 42 | |
| 43 | /* |
| 44 | * PBC Controller parameters |
| 45 | */ |
| 46 | |
| 47 | /* |
| 48 | * Base address of PBC controller, CS4 |
| 49 | */ |
Uwe Kleine-König | 7b9020b | 2009-04-21 22:56:14 +0200 | [diff] [blame] | 50 | #define PBC_BASE_ADDRESS 0xf4300000 |
Holger Schurig | 058b7a6 | 2009-01-26 16:34:51 +0100 | [diff] [blame] | 51 | #define PBC_REG_ADDR(offset) (void __force __iomem *) \ |
| 52 | (PBC_BASE_ADDRESS + (offset)) |
Juergen Beisert | 80eedae | 2008-07-05 10:03:00 +0200 | [diff] [blame] | 53 | |
| 54 | /* |
| 55 | * PBC Interupt name definitions |
| 56 | */ |
| 57 | #define PBC_GPIO1_0 0 |
| 58 | #define PBC_GPIO1_1 1 |
| 59 | #define PBC_GPIO1_2 2 |
| 60 | #define PBC_GPIO1_3 3 |
| 61 | #define PBC_GPIO1_4 4 |
| 62 | #define PBC_GPIO1_5 5 |
| 63 | |
| 64 | #define PBC_INTR_MAX_NUM 6 |
| 65 | #define PBC_INTR_SHARED_MAX_NUM 8 |
| 66 | |
| 67 | /* When the PBC address connection is fixed in h/w, defined as 1 */ |
| 68 | #define PBC_ADDR_SH 0 |
| 69 | |
| 70 | /* Offsets for the PBC Controller register */ |
| 71 | /* |
| 72 | * PBC Board version register offset |
| 73 | */ |
| 74 | #define PBC_VERSION_REG PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH) |
| 75 | /* |
| 76 | * PBC Board control register 1 set address. |
| 77 | */ |
| 78 | #define PBC_BCTRL1_SET_REG PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH) |
| 79 | /* |
| 80 | * PBC Board control register 1 clear address. |
| 81 | */ |
| 82 | #define PBC_BCTRL1_CLEAR_REG PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH) |
| 83 | /* |
| 84 | * PBC Board control register 2 set address. |
| 85 | */ |
| 86 | #define PBC_BCTRL2_SET_REG PBC_REG_ADDR(0x00010 >> PBC_ADDR_SH) |
| 87 | /* |
| 88 | * PBC Board control register 2 clear address. |
| 89 | */ |
| 90 | #define PBC_BCTRL2_CLEAR_REG PBC_REG_ADDR(0x00014 >> PBC_ADDR_SH) |
| 91 | /* |
| 92 | * PBC Board control register 3 set address. |
| 93 | */ |
| 94 | #define PBC_BCTRL3_SET_REG PBC_REG_ADDR(0x00018 >> PBC_ADDR_SH) |
| 95 | /* |
| 96 | * PBC Board control register 3 clear address. |
| 97 | */ |
| 98 | #define PBC_BCTRL3_CLEAR_REG PBC_REG_ADDR(0x0001C >> PBC_ADDR_SH) |
| 99 | /* |
| 100 | * PBC Board control register 3 set address. |
| 101 | */ |
| 102 | #define PBC_BCTRL4_SET_REG PBC_REG_ADDR(0x00020 >> PBC_ADDR_SH) |
| 103 | /* |
| 104 | * PBC Board control register 4 clear address. |
| 105 | */ |
| 106 | #define PBC_BCTRL4_CLEAR_REG PBC_REG_ADDR(0x00024 >> PBC_ADDR_SH) |
| 107 | /*PBC_ADDR_SH |
| 108 | * PBC Board status register 1. |
| 109 | */ |
| 110 | #define PBC_BSTAT1_REG PBC_REG_ADDR(0x00028 >> PBC_ADDR_SH) |
| 111 | /* |
| 112 | * PBC Board interrupt status register. |
| 113 | */ |
| 114 | #define PBC_INTSTATUS_REG PBC_REG_ADDR(0x0002C >> PBC_ADDR_SH) |
| 115 | /* |
| 116 | * PBC Board interrupt current status register. |
| 117 | */ |
| 118 | #define PBC_INTCURR_STATUS_REG PBC_REG_ADDR(0x00034 >> PBC_ADDR_SH) |
| 119 | /* |
| 120 | * PBC Interrupt mask register set address. |
| 121 | */ |
| 122 | #define PBC_INTMASK_SET_REG PBC_REG_ADDR(0x00038 >> PBC_ADDR_SH) |
| 123 | /* |
| 124 | * PBC Interrupt mask register clear address. |
| 125 | */ |
| 126 | #define PBC_INTMASK_CLEAR_REG PBC_REG_ADDR(0x0003C >> PBC_ADDR_SH) |
| 127 | /* |
| 128 | * External UART A. |
| 129 | */ |
| 130 | #define PBC_SC16C652_UARTA_REG PBC_REG_ADDR(0x20000 >> PBC_ADDR_SH) |
| 131 | /* |
| 132 | * UART 4 Expanding Signal Status. |
| 133 | */ |
| 134 | #define PBC_UART_STATUS_REG PBC_REG_ADDR(0x22000 >> PBC_ADDR_SH) |
| 135 | /* |
| 136 | * UART 4 Expanding Signal Control Set. |
| 137 | */ |
| 138 | #define PBC_UCTRL_SET_REG PBC_REG_ADDR(0x24000 >> PBC_ADDR_SH) |
| 139 | /* |
| 140 | * UART 4 Expanding Signal Control Clear. |
| 141 | */ |
| 142 | #define PBC_UCTRL_CLR_REG PBC_REG_ADDR(0x26000 >> PBC_ADDR_SH) |
| 143 | /* |
| 144 | * Ethernet Controller IO base address. |
| 145 | */ |
| 146 | #define PBC_CS8900A_IOBASE_REG PBC_REG_ADDR(0x40000 >> PBC_ADDR_SH) |
| 147 | /* |
| 148 | * Ethernet Controller Memory base address. |
| 149 | */ |
| 150 | #define PBC_CS8900A_MEMBASE_REG PBC_REG_ADDR(0x42000 >> PBC_ADDR_SH) |
| 151 | /* |
| 152 | * Ethernet Controller DMA base address. |
| 153 | */ |
| 154 | #define PBC_CS8900A_DMABASE_REG PBC_REG_ADDR(0x44000 >> PBC_ADDR_SH) |
| 155 | |
| 156 | /* PBC Board Version Register bit definition */ |
| 157 | #define PBC_VERSION_ADS 0x8000 /* Bit15=1 means version for ads */ |
| 158 | #define PBC_VERSION_EVB_REVB 0x4000 /* BIT14=1 means version for evb revb */ |
| 159 | |
| 160 | /* PBC Board Control Register 1 bit definitions */ |
| 161 | #define PBC_BCTRL1_ERST 0x0001 /* Ethernet Reset */ |
| 162 | #define PBC_BCTRL1_URST 0x0002 /* Reset External UART controller */ |
| 163 | #define PBC_BCTRL1_FRST 0x0004 /* FEC Reset */ |
| 164 | #define PBC_BCTRL1_ESLEEP 0x0010 /* Enable ethernet Sleep */ |
| 165 | #define PBC_BCTRL1_LCDON 0x0800 /* Enable the LCD */ |
| 166 | |
| 167 | /* PBC Board Control Register 2 bit definitions */ |
| 168 | #define PBC_BCTRL2_VCC_EN 0x0004 /* Enable VCC */ |
| 169 | #define PBC_BCTRL2_VPP_EN 0x0008 /* Enable Vpp */ |
| 170 | #define PBC_BCTRL2_ATAFEC_EN 0X0010 |
| 171 | #define PBC_BCTRL2_ATAFEC_SEL 0X0020 |
| 172 | #define PBC_BCTRL2_ATA_EN 0X0040 |
| 173 | #define PBC_BCTRL2_IRDA_SD 0X0080 |
| 174 | #define PBC_BCTRL2_IRDA_EN 0X0100 |
| 175 | #define PBC_BCTRL2_CCTL10 0X0200 |
| 176 | #define PBC_BCTRL2_CCTL11 0X0400 |
| 177 | |
| 178 | /* PBC Board Control Register 3 bit definitions */ |
| 179 | #define PBC_BCTRL3_HSH_EN 0X0020 |
| 180 | #define PBC_BCTRL3_FSH_MOD 0X0040 |
| 181 | #define PBC_BCTRL3_OTG_HS_EN 0X0080 |
| 182 | #define PBC_BCTRL3_OTG_VBUS_EN 0X0100 |
| 183 | #define PBC_BCTRL3_FSH_VBUS_EN 0X0200 |
| 184 | #define PBC_BCTRL3_USB_OTG_ON 0X0800 |
| 185 | #define PBC_BCTRL3_USB_FSH_ON 0X1000 |
| 186 | |
| 187 | /* PBC Board Control Register 4 bit definitions */ |
| 188 | #define PBC_BCTRL4_REGEN_SEL 0X0001 |
| 189 | #define PBC_BCTRL4_USER_OFF 0X0002 |
| 190 | #define PBC_BCTRL4_VIB_EN 0X0004 |
| 191 | #define PBC_BCTRL4_PWRGT1_EN 0X0008 |
| 192 | #define PBC_BCTRL4_PWRGT2_EN 0X0010 |
| 193 | #define PBC_BCTRL4_STDBY_PRI 0X0020 |
| 194 | |
| 195 | #ifndef __ASSEMBLY__ |
| 196 | /* |
| 197 | * Enumerations for SD cards and memory stick card. This corresponds to |
| 198 | * the card EN bits in the IMR: SD1_EN | MS_EN | SD3_EN | SD2_EN. |
| 199 | */ |
| 200 | enum mxc_card_no { |
| 201 | MXC_CARD_SD2 = 0, |
| 202 | MXC_CARD_SD3, |
| 203 | MXC_CARD_MS, |
| 204 | MXC_CARD_SD1, |
| 205 | MXC_CARD_MIN = MXC_CARD_SD2, |
| 206 | MXC_CARD_MAX = MXC_CARD_SD1, |
| 207 | }; |
| 208 | #endif |
| 209 | |
| 210 | #define MXC_CPLD_VER_1_50 0x01 |
| 211 | |
| 212 | /* |
| 213 | * PBC BSTAT Register bit definitions |
| 214 | */ |
| 215 | #define PBC_BSTAT_PRI_INT 0X0001 |
| 216 | #define PBC_BSTAT_USB_BYP 0X0002 |
| 217 | #define PBC_BSTAT_ATA_IOCS16 0X0004 |
| 218 | #define PBC_BSTAT_ATA_CBLID 0X0008 |
| 219 | #define PBC_BSTAT_ATA_DASP 0X0010 |
| 220 | #define PBC_BSTAT_PWR_RDY 0X0020 |
| 221 | #define PBC_BSTAT_SD3_WP 0X0100 |
| 222 | #define PBC_BSTAT_SD2_WP 0X0200 |
| 223 | #define PBC_BSTAT_SD1_WP 0X0400 |
| 224 | #define PBC_BSTAT_SD3_DET 0X0800 |
| 225 | #define PBC_BSTAT_SD2_DET 0X1000 |
| 226 | #define PBC_BSTAT_SD1_DET 0X2000 |
| 227 | #define PBC_BSTAT_MS_DET 0X4000 |
| 228 | #define PBC_BSTAT_SD3_DET_BIT 11 |
| 229 | #define PBC_BSTAT_SD2_DET_BIT 12 |
| 230 | #define PBC_BSTAT_SD1_DET_BIT 13 |
| 231 | #define PBC_BSTAT_MS_DET_BIT 14 |
| 232 | #define MXC_BSTAT_BIT(n) ((n == MXC_CARD_SD2) ? PBC_BSTAT_SD2_DET : \ |
| 233 | ((n == MXC_CARD_SD3) ? PBC_BSTAT_SD3_DET : \ |
| 234 | ((n == MXC_CARD_SD1) ? PBC_BSTAT_SD1_DET : \ |
| 235 | ((n == MXC_CARD_MS) ? PBC_BSTAT_MS_DET : \ |
| 236 | 0x0)))) |
| 237 | |
| 238 | /* |
| 239 | * PBC UART Control Register bit definitions |
| 240 | */ |
| 241 | #define PBC_UCTRL_DCE_DCD 0X0001 |
| 242 | #define PBC_UCTRL_DCE_DSR 0X0002 |
| 243 | #define PBC_UCTRL_DCE_RI 0X0004 |
| 244 | #define PBC_UCTRL_DTE_DTR 0X0100 |
| 245 | |
| 246 | /* |
| 247 | * PBC UART Status Register bit definitions |
| 248 | */ |
| 249 | #define PBC_USTAT_DTE_DCD 0X0001 |
| 250 | #define PBC_USTAT_DTE_DSR 0X0002 |
| 251 | #define PBC_USTAT_DTE_RI 0X0004 |
| 252 | #define PBC_USTAT_DCE_DTR 0X0100 |
| 253 | |
| 254 | /* |
| 255 | * PBC Interupt mask register bit definitions |
| 256 | */ |
| 257 | #define PBC_INTR_SD3_R_EN_BIT 4 |
| 258 | #define PBC_INTR_SD2_R_EN_BIT 0 |
| 259 | #define PBC_INTR_SD1_R_EN_BIT 6 |
| 260 | #define PBC_INTR_MS_R_EN_BIT 5 |
| 261 | #define PBC_INTR_SD3_EN_BIT 13 |
| 262 | #define PBC_INTR_SD2_EN_BIT 12 |
| 263 | #define PBC_INTR_MS_EN_BIT 14 |
| 264 | #define PBC_INTR_SD1_EN_BIT 15 |
| 265 | |
| 266 | #define PBC_INTR_SD2_R_EN 0x0001 |
| 267 | #define PBC_INTR_LOW_BAT 0X0002 |
| 268 | #define PBC_INTR_OTG_FSOVER 0X0004 |
| 269 | #define PBC_INTR_FSH_OVER 0X0008 |
| 270 | #define PBC_INTR_SD3_R_EN 0x0010 |
| 271 | #define PBC_INTR_MS_R_EN 0x0020 |
| 272 | #define PBC_INTR_SD1_R_EN 0x0040 |
| 273 | #define PBC_INTR_FEC_INT 0X0080 |
| 274 | #define PBC_INTR_ENET_INT 0X0100 |
| 275 | #define PBC_INTR_OTGFS_INT 0X0200 |
| 276 | #define PBC_INTR_XUART_INT 0X0400 |
| 277 | #define PBC_INTR_CCTL12 0X0800 |
| 278 | #define PBC_INTR_SD2_EN 0x1000 |
| 279 | #define PBC_INTR_SD3_EN 0x2000 |
| 280 | #define PBC_INTR_MS_EN 0x4000 |
| 281 | #define PBC_INTR_SD1_EN 0x8000 |
| 282 | |
| 283 | |
| 284 | |
| 285 | /* For interrupts like xuart, enet etc */ |
| 286 | #define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX27_PIN_TIN) |
| 287 | #define MXC_MAX_EXP_IO_LINES 16 |
| 288 | |
| 289 | /* |
| 290 | * This corresponds to PBC_INTMASK_SET_REG at offset 0x38. |
| 291 | * |
| 292 | */ |
| 293 | #define EXPIO_INT_LOW_BAT (MXC_EXP_IO_BASE + 1) |
| 294 | #define EXPIO_INT_OTG_FS_OVR (MXC_EXP_IO_BASE + 2) |
| 295 | #define EXPIO_INT_FSH_OVR (MXC_EXP_IO_BASE + 3) |
| 296 | #define EXPIO_INT_RES4 (MXC_EXP_IO_BASE + 4) |
| 297 | #define EXPIO_INT_RES5 (MXC_EXP_IO_BASE + 5) |
| 298 | #define EXPIO_INT_RES6 (MXC_EXP_IO_BASE + 6) |
| 299 | #define EXPIO_INT_FEC (MXC_EXP_IO_BASE + 7) |
| 300 | #define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8) |
| 301 | #define EXPIO_INT_OTG_FS_INT (MXC_EXP_IO_BASE + 9) |
| 302 | #define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10) |
| 303 | #define EXPIO_INT_CCTL12_INT (MXC_EXP_IO_BASE + 11) |
| 304 | #define EXPIO_INT_SD2_EN (MXC_EXP_IO_BASE + 12) |
| 305 | #define EXPIO_INT_SD3_EN (MXC_EXP_IO_BASE + 13) |
| 306 | #define EXPIO_INT_MS_EN (MXC_EXP_IO_BASE + 14) |
| 307 | #define EXPIO_INT_SD1_EN (MXC_EXP_IO_BASE + 15) |
| 308 | |
| 309 | /* |
| 310 | * This is System IRQ used by CS8900A for interrupt generation |
| 311 | * taken from platform.h |
| 312 | */ |
| 313 | #define CS8900AIRQ EXPIO_INT_ENET_INT |
| 314 | /* This is I/O Base address used to access registers of CS8900A on MXC ADS */ |
| 315 | #define CS8900A_BASE_ADDRESS (PBC_CS8900A_IOBASE_REG + 0x300) |
| 316 | |
| 317 | #define MXC_PMIC_INT_LINE IOMUX_TO_IRQ(MX27_PIN_TOUT) |
| 318 | |
| 319 | /* |
| 320 | * This is used to detect if the CPLD version is for mx27 evb board rev-a |
| 321 | */ |
| 322 | #define PBC_CPLD_VERSION_IS_REVA() \ |
| 323 | ((__raw_readw(PBC_VERSION_REG) & \ |
| 324 | (PBC_VERSION_ADS | PBC_VERSION_EVB_REVB))\ |
| 325 | == 0) |
| 326 | |
| 327 | /* This is used to active or inactive ata signal in CPLD . |
| 328 | * It is dependent with hardware |
| 329 | */ |
| 330 | #define PBC_ATA_SIGNAL_ACTIVE() \ |
| 331 | __raw_writew( \ |
| 332 | PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \ |
| 333 | PBC_BCTRL2_CLEAR_REG) |
| 334 | |
| 335 | #define PBC_ATA_SIGNAL_INACTIVE() \ |
| 336 | __raw_writew( \ |
| 337 | PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \ |
| 338 | PBC_BCTRL2_SET_REG) |
| 339 | |
| 340 | #define MXC_BD_LED1 (1 << 5) |
| 341 | #define MXC_BD_LED2 (1 << 6) |
| 342 | #define MXC_BD_LED_ON(led) \ |
| 343 | __raw_writew(led, PBC_BCTRL1_SET_REG) |
| 344 | #define MXC_BD_LED_OFF(led) \ |
| 345 | __raw_writew(led, PBC_BCTRL1_CLEAR_REG) |
| 346 | |
| 347 | /* to determine the correct external crystal reference */ |
| 348 | #define CKIH_27MHZ_BIT_SET (1 << 3) |
| 349 | |
| 350 | #endif /* __ASM_ARCH_MXC_BOARD_MX27ADS_H__ */ |