Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
Russell King | 4baa992 | 2008-08-02 10:55:55 +0100 | [diff] [blame] | 2 | * arch/arm/include/asm/cacheflush.h |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 1999-2002 Russell King |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | */ |
| 10 | #ifndef _ASMARM_CACHEFLUSH_H |
| 11 | #define _ASMARM_CACHEFLUSH_H |
| 12 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13 | #include <linux/mm.h> |
| 14 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15 | #include <asm/glue.h> |
Russell King | b8a9b66 | 2005-06-20 11:31:09 +0100 | [diff] [blame] | 16 | #include <asm/shmparam.h> |
Catalin Marinas | 376e142 | 2008-11-06 13:23:08 +0000 | [diff] [blame] | 17 | #include <asm/cachetype.h> |
Russell King | b8a9b66 | 2005-06-20 11:31:09 +0100 | [diff] [blame] | 18 | |
| 19 | #define CACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 20 | |
| 21 | /* |
| 22 | * Cache Model |
| 23 | * =========== |
| 24 | */ |
| 25 | #undef _CACHE |
| 26 | #undef MULTI_CACHE |
| 27 | |
Russell King | 6cc7cbe | 2006-09-27 18:00:35 +0100 | [diff] [blame] | 28 | #if defined(CONFIG_CPU_CACHE_V3) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 29 | # ifdef _CACHE |
| 30 | # define MULTI_CACHE 1 |
| 31 | # else |
| 32 | # define _CACHE v3 |
| 33 | # endif |
| 34 | #endif |
| 35 | |
Russell King | 6cc7cbe | 2006-09-27 18:00:35 +0100 | [diff] [blame] | 36 | #if defined(CONFIG_CPU_CACHE_V4) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 37 | # ifdef _CACHE |
| 38 | # define MULTI_CACHE 1 |
| 39 | # else |
| 40 | # define _CACHE v4 |
| 41 | # endif |
| 42 | #endif |
| 43 | |
| 44 | #if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \ |
Abdoulaye Walsimou Gaye | 1c8e170 | 2010-02-19 12:47:14 +0100 | [diff] [blame] | 45 | defined(CONFIG_CPU_ARM925T) || defined(CONFIG_CPU_ARM1020) || \ |
| 46 | defined(CONFIG_CPU_ARM1026) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 47 | # define MULTI_CACHE 1 |
| 48 | #endif |
| 49 | |
Paulius Zaleckas | 28853ac | 2009-03-25 13:10:01 +0200 | [diff] [blame] | 50 | #if defined(CONFIG_CPU_FA526) |
| 51 | # ifdef _CACHE |
| 52 | # define MULTI_CACHE 1 |
| 53 | # else |
| 54 | # define _CACHE fa |
| 55 | # endif |
| 56 | #endif |
| 57 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 58 | #if defined(CONFIG_CPU_ARM926T) |
| 59 | # ifdef _CACHE |
| 60 | # define MULTI_CACHE 1 |
| 61 | # else |
| 62 | # define _CACHE arm926 |
| 63 | # endif |
| 64 | #endif |
| 65 | |
Hyok S. Choi | d60674e | 2006-09-26 17:38:18 +0900 | [diff] [blame] | 66 | #if defined(CONFIG_CPU_ARM940T) |
| 67 | # ifdef _CACHE |
| 68 | # define MULTI_CACHE 1 |
| 69 | # else |
| 70 | # define _CACHE arm940 |
| 71 | # endif |
| 72 | #endif |
| 73 | |
Hyok S. Choi | f37f46e | 2006-09-26 17:38:32 +0900 | [diff] [blame] | 74 | #if defined(CONFIG_CPU_ARM946E) |
| 75 | # ifdef _CACHE |
| 76 | # define MULTI_CACHE 1 |
| 77 | # else |
| 78 | # define _CACHE arm946 |
| 79 | # endif |
| 80 | #endif |
| 81 | |
Russell King | 6cc7cbe | 2006-09-27 18:00:35 +0100 | [diff] [blame] | 82 | #if defined(CONFIG_CPU_CACHE_V4WB) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 83 | # ifdef _CACHE |
| 84 | # define MULTI_CACHE 1 |
| 85 | # else |
| 86 | # define _CACHE v4wb |
| 87 | # endif |
| 88 | #endif |
| 89 | |
| 90 | #if defined(CONFIG_CPU_XSCALE) |
| 91 | # ifdef _CACHE |
| 92 | # define MULTI_CACHE 1 |
| 93 | # else |
| 94 | # define _CACHE xscale |
| 95 | # endif |
| 96 | #endif |
| 97 | |
Lennert Buytenhek | 23bdf86 | 2006-03-28 21:00:40 +0100 | [diff] [blame] | 98 | #if defined(CONFIG_CPU_XSC3) |
| 99 | # ifdef _CACHE |
| 100 | # define MULTI_CACHE 1 |
| 101 | # else |
| 102 | # define _CACHE xsc3 |
| 103 | # endif |
| 104 | #endif |
| 105 | |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 106 | #if defined(CONFIG_CPU_MOHAWK) |
| 107 | # ifdef _CACHE |
| 108 | # define MULTI_CACHE 1 |
| 109 | # else |
| 110 | # define _CACHE mohawk |
| 111 | # endif |
| 112 | #endif |
| 113 | |
Assaf Hoffman | e50d640 | 2007-10-23 15:14:41 -0400 | [diff] [blame] | 114 | #if defined(CONFIG_CPU_FEROCEON) |
Stanislav Samsonov | 836a805 | 2008-06-03 11:24:40 +0300 | [diff] [blame] | 115 | # define MULTI_CACHE 1 |
Assaf Hoffman | e50d640 | 2007-10-23 15:14:41 -0400 | [diff] [blame] | 116 | #endif |
| 117 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 118 | #if defined(CONFIG_CPU_V6) |
| 119 | //# ifdef _CACHE |
| 120 | # define MULTI_CACHE 1 |
| 121 | //# else |
| 122 | //# define _CACHE v6 |
| 123 | //# endif |
| 124 | #endif |
| 125 | |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 126 | #if defined(CONFIG_CPU_V7) |
| 127 | //# ifdef _CACHE |
| 128 | # define MULTI_CACHE 1 |
| 129 | //# else |
| 130 | //# define _CACHE v7 |
| 131 | //# endif |
| 132 | #endif |
| 133 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 134 | #if !defined(_CACHE) && !defined(MULTI_CACHE) |
| 135 | #error Unknown cache maintainence model |
| 136 | #endif |
| 137 | |
| 138 | /* |
| 139 | * This flag is used to indicate that the page pointed to by a pte |
| 140 | * is dirty and requires cleaning before returning it to the user. |
| 141 | */ |
| 142 | #define PG_dcache_dirty PG_arch_1 |
| 143 | |
| 144 | /* |
| 145 | * MM Cache Management |
| 146 | * =================== |
| 147 | * |
| 148 | * The arch/arm/mm/cache-*.S and arch/arm/mm/proc-*.S files |
| 149 | * implement these methods. |
| 150 | * |
| 151 | * Start addresses are inclusive and end addresses are exclusive; |
| 152 | * start addresses should be rounded down, end addresses up. |
| 153 | * |
| 154 | * See Documentation/cachetlb.txt for more information. |
| 155 | * Please note that the implementation of these, and the required |
| 156 | * effects are cache-type (VIVT/VIPT/PIPT) specific. |
| 157 | * |
Tony Lindgren | 2045124 | 2010-01-19 23:42:08 +0100 | [diff] [blame] | 158 | * flush_kern_all() |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 159 | * |
| 160 | * Unconditionally clean and invalidate the entire cache. |
| 161 | * |
Tony Lindgren | 2045124 | 2010-01-19 23:42:08 +0100 | [diff] [blame] | 162 | * flush_user_all() |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 163 | * |
| 164 | * Clean and invalidate all user space cache entries |
| 165 | * before a change of page tables. |
| 166 | * |
Tony Lindgren | 2045124 | 2010-01-19 23:42:08 +0100 | [diff] [blame] | 167 | * flush_user_range(start, end, flags) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 168 | * |
| 169 | * Clean and invalidate a range of cache entries in the |
| 170 | * specified address space before a change of page tables. |
| 171 | * - start - user start address (inclusive, page aligned) |
| 172 | * - end - user end address (exclusive, page aligned) |
| 173 | * - flags - vma->vm_flags field |
| 174 | * |
| 175 | * coherent_kern_range(start, end) |
| 176 | * |
| 177 | * Ensure coherency between the Icache and the Dcache in the |
| 178 | * region described by start, end. If you have non-snooping |
| 179 | * Harvard caches, you need to implement this function. |
| 180 | * - start - virtual start address |
| 181 | * - end - virtual end address |
| 182 | * |
Tony Lindgren | 2045124 | 2010-01-19 23:42:08 +0100 | [diff] [blame] | 183 | * coherent_user_range(start, end) |
| 184 | * |
| 185 | * Ensure coherency between the Icache and the Dcache in the |
| 186 | * region described by start, end. If you have non-snooping |
| 187 | * Harvard caches, you need to implement this function. |
| 188 | * - start - virtual start address |
| 189 | * - end - virtual end address |
| 190 | * |
| 191 | * flush_kern_dcache_area(kaddr, size) |
| 192 | * |
| 193 | * Ensure that the data held in page is written back. |
| 194 | * - kaddr - page address |
| 195 | * - size - region size |
| 196 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 197 | * DMA Cache Coherency |
| 198 | * =================== |
| 199 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 200 | * dma_flush_range(start, end) |
| 201 | * |
| 202 | * Clean and invalidate the specified virtual address range. |
| 203 | * - start - virtual start address |
| 204 | * - end - virtual end address |
| 205 | */ |
| 206 | |
| 207 | struct cpu_cache_fns { |
| 208 | void (*flush_kern_all)(void); |
| 209 | void (*flush_user_all)(void); |
| 210 | void (*flush_user_range)(unsigned long, unsigned long, unsigned int); |
| 211 | |
| 212 | void (*coherent_kern_range)(unsigned long, unsigned long); |
| 213 | void (*coherent_user_range)(unsigned long, unsigned long); |
Russell King | 2c9b9c8 | 2009-11-26 12:56:21 +0000 | [diff] [blame] | 214 | void (*flush_kern_dcache_area)(void *, size_t); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 215 | |
Russell King | a9c9147 | 2009-11-26 16:19:58 +0000 | [diff] [blame] | 216 | void (*dma_map_area)(const void *, size_t, int); |
| 217 | void (*dma_unmap_area)(const void *, size_t, int); |
| 218 | |
Russell King | 7ae5a76 | 2007-02-06 17:39:31 +0000 | [diff] [blame] | 219 | void (*dma_flush_range)(const void *, const void *); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 220 | }; |
| 221 | |
Catalin Marinas | 953233d | 2007-02-05 14:48:08 +0100 | [diff] [blame] | 222 | struct outer_cache_fns { |
| 223 | void (*inv_range)(unsigned long, unsigned long); |
| 224 | void (*clean_range)(unsigned long, unsigned long); |
| 225 | void (*flush_range)(unsigned long, unsigned long); |
| 226 | }; |
| 227 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 228 | /* |
| 229 | * Select the calling method |
| 230 | */ |
| 231 | #ifdef MULTI_CACHE |
| 232 | |
| 233 | extern struct cpu_cache_fns cpu_cache; |
| 234 | |
| 235 | #define __cpuc_flush_kern_all cpu_cache.flush_kern_all |
| 236 | #define __cpuc_flush_user_all cpu_cache.flush_user_all |
| 237 | #define __cpuc_flush_user_range cpu_cache.flush_user_range |
| 238 | #define __cpuc_coherent_kern_range cpu_cache.coherent_kern_range |
| 239 | #define __cpuc_coherent_user_range cpu_cache.coherent_user_range |
Russell King | 2c9b9c8 | 2009-11-26 12:56:21 +0000 | [diff] [blame] | 240 | #define __cpuc_flush_dcache_area cpu_cache.flush_kern_dcache_area |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 241 | |
| 242 | /* |
| 243 | * These are private to the dma-mapping API. Do not use directly. |
| 244 | * Their sole purpose is to ensure that data held in the cache |
| 245 | * is visible to DMA, or data written by DMA to system memory is |
| 246 | * visible to the CPU. |
| 247 | */ |
Russell King | a9c9147 | 2009-11-26 16:19:58 +0000 | [diff] [blame] | 248 | #define dmac_map_area cpu_cache.dma_map_area |
| 249 | #define dmac_unmap_area cpu_cache.dma_unmap_area |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 250 | #define dmac_flush_range cpu_cache.dma_flush_range |
| 251 | |
| 252 | #else |
| 253 | |
| 254 | #define __cpuc_flush_kern_all __glue(_CACHE,_flush_kern_cache_all) |
| 255 | #define __cpuc_flush_user_all __glue(_CACHE,_flush_user_cache_all) |
| 256 | #define __cpuc_flush_user_range __glue(_CACHE,_flush_user_cache_range) |
| 257 | #define __cpuc_coherent_kern_range __glue(_CACHE,_coherent_kern_range) |
| 258 | #define __cpuc_coherent_user_range __glue(_CACHE,_coherent_user_range) |
Russell King | 2c9b9c8 | 2009-11-26 12:56:21 +0000 | [diff] [blame] | 259 | #define __cpuc_flush_dcache_area __glue(_CACHE,_flush_kern_dcache_area) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 260 | |
| 261 | extern void __cpuc_flush_kern_all(void); |
| 262 | extern void __cpuc_flush_user_all(void); |
| 263 | extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int); |
| 264 | extern void __cpuc_coherent_kern_range(unsigned long, unsigned long); |
| 265 | extern void __cpuc_coherent_user_range(unsigned long, unsigned long); |
Russell King | 2c9b9c8 | 2009-11-26 12:56:21 +0000 | [diff] [blame] | 266 | extern void __cpuc_flush_dcache_area(void *, size_t); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 267 | |
| 268 | /* |
| 269 | * These are private to the dma-mapping API. Do not use directly. |
| 270 | * Their sole purpose is to ensure that data held in the cache |
| 271 | * is visible to DMA, or data written by DMA to system memory is |
| 272 | * visible to the CPU. |
| 273 | */ |
Russell King | a9c9147 | 2009-11-26 16:19:58 +0000 | [diff] [blame] | 274 | #define dmac_map_area __glue(_CACHE,_dma_map_area) |
| 275 | #define dmac_unmap_area __glue(_CACHE,_dma_unmap_area) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 276 | #define dmac_flush_range __glue(_CACHE,_dma_flush_range) |
| 277 | |
Russell King | a9c9147 | 2009-11-26 16:19:58 +0000 | [diff] [blame] | 278 | extern void dmac_map_area(const void *, size_t, int); |
| 279 | extern void dmac_unmap_area(const void *, size_t, int); |
Russell King | 7ae5a76 | 2007-02-06 17:39:31 +0000 | [diff] [blame] | 280 | extern void dmac_flush_range(const void *, const void *); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 281 | |
| 282 | #endif |
| 283 | |
Catalin Marinas | 953233d | 2007-02-05 14:48:08 +0100 | [diff] [blame] | 284 | #ifdef CONFIG_OUTER_CACHE |
| 285 | |
| 286 | extern struct outer_cache_fns outer_cache; |
| 287 | |
| 288 | static inline void outer_inv_range(unsigned long start, unsigned long end) |
| 289 | { |
| 290 | if (outer_cache.inv_range) |
| 291 | outer_cache.inv_range(start, end); |
| 292 | } |
| 293 | static inline void outer_clean_range(unsigned long start, unsigned long end) |
| 294 | { |
| 295 | if (outer_cache.clean_range) |
| 296 | outer_cache.clean_range(start, end); |
| 297 | } |
| 298 | static inline void outer_flush_range(unsigned long start, unsigned long end) |
| 299 | { |
| 300 | if (outer_cache.flush_range) |
| 301 | outer_cache.flush_range(start, end); |
| 302 | } |
| 303 | |
| 304 | #else |
| 305 | |
| 306 | static inline void outer_inv_range(unsigned long start, unsigned long end) |
| 307 | { } |
| 308 | static inline void outer_clean_range(unsigned long start, unsigned long end) |
| 309 | { } |
| 310 | static inline void outer_flush_range(unsigned long start, unsigned long end) |
| 311 | { } |
| 312 | |
| 313 | #endif |
| 314 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 315 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 316 | * Copy user data from/to a page which is mapped into a different |
| 317 | * processes address space. Really, we want to allow our "user |
| 318 | * space" model to handle this. |
| 319 | */ |
Russell King | 2ef7f3d | 2009-11-05 13:29:36 +0000 | [diff] [blame] | 320 | extern void copy_to_user_page(struct vm_area_struct *, struct page *, |
| 321 | unsigned long, void *, const void *, unsigned long); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 322 | #define copy_from_user_page(vma, page, vaddr, dst, src, len) \ |
| 323 | do { \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 324 | memcpy(dst, src, len); \ |
| 325 | } while (0) |
| 326 | |
| 327 | /* |
| 328 | * Convert calls to our calling convention. |
| 329 | */ |
| 330 | #define flush_cache_all() __cpuc_flush_kern_all() |
Russell King | 2f0b192 | 2009-10-25 10:40:02 +0000 | [diff] [blame] | 331 | |
| 332 | static inline void vivt_flush_cache_mm(struct mm_struct *mm) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 333 | { |
Rusty Russell | 56f8ba8 | 2009-09-24 09:34:49 -0600 | [diff] [blame] | 334 | if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm))) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 335 | __cpuc_flush_user_all(); |
| 336 | } |
| 337 | |
| 338 | static inline void |
Russell King | 2f0b192 | 2009-10-25 10:40:02 +0000 | [diff] [blame] | 339 | vivt_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 340 | { |
Rusty Russell | 56f8ba8 | 2009-09-24 09:34:49 -0600 | [diff] [blame] | 341 | if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 342 | __cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end), |
| 343 | vma->vm_flags); |
| 344 | } |
| 345 | |
| 346 | static inline void |
Russell King | 2f0b192 | 2009-10-25 10:40:02 +0000 | [diff] [blame] | 347 | vivt_flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 348 | { |
Rusty Russell | 56f8ba8 | 2009-09-24 09:34:49 -0600 | [diff] [blame] | 349 | if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 350 | unsigned long addr = user_addr & PAGE_MASK; |
| 351 | __cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags); |
| 352 | } |
| 353 | } |
George G. Davis | a188ad2 | 2006-09-02 18:43:20 +0100 | [diff] [blame] | 354 | |
Russell King | 2f0b192 | 2009-10-25 10:40:02 +0000 | [diff] [blame] | 355 | #ifndef CONFIG_CPU_CACHE_VIPT |
| 356 | #define flush_cache_mm(mm) \ |
| 357 | vivt_flush_cache_mm(mm) |
| 358 | #define flush_cache_range(vma,start,end) \ |
| 359 | vivt_flush_cache_range(vma,start,end) |
| 360 | #define flush_cache_page(vma,addr,pfn) \ |
| 361 | vivt_flush_cache_page(vma,addr,pfn) |
Russell King | d7b6b35 | 2005-09-08 15:32:23 +0100 | [diff] [blame] | 362 | #else |
| 363 | extern void flush_cache_mm(struct mm_struct *mm); |
| 364 | extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); |
| 365 | extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn); |
| 366 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 367 | |
Ralf Baechle | ec8c044 | 2006-12-12 17:14:57 +0000 | [diff] [blame] | 368 | #define flush_cache_dup_mm(mm) flush_cache_mm(mm) |
| 369 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 370 | /* |
| 371 | * flush_cache_user_range is used when we want to ensure that the |
| 372 | * Harvard caches are synchronised for the user space address range. |
| 373 | * This is used for the ARM private sys_cacheflush system call. |
| 374 | */ |
| 375 | #define flush_cache_user_range(vma,start,end) \ |
| 376 | __cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end)) |
| 377 | |
| 378 | /* |
| 379 | * Perform necessary cache operations to ensure that data previously |
| 380 | * stored within this range of addresses can be executed by the CPU. |
| 381 | */ |
| 382 | #define flush_icache_range(s,e) __cpuc_coherent_kern_range(s,e) |
| 383 | |
| 384 | /* |
| 385 | * Perform necessary cache operations to ensure that the TLB will |
| 386 | * see data written in the specified area. |
| 387 | */ |
| 388 | #define clean_dcache_area(start,size) cpu_dcache_clean_area(start, size) |
| 389 | |
| 390 | /* |
| 391 | * flush_dcache_page is used when the kernel has written to the page |
| 392 | * cache page at virtual address page->virtual. |
| 393 | * |
| 394 | * If this page isn't mapped (ie, page_mapping == NULL), or it might |
| 395 | * have userspace mappings, then we _must_ always clean + invalidate |
| 396 | * the dcache entries associated with the kernel mapping. |
| 397 | * |
| 398 | * Otherwise we can defer the operation, and clean the cache when we are |
| 399 | * about to change to user space. This is the same method as used on SPARC64. |
| 400 | * See update_mmu_cache for the user space part. |
| 401 | */ |
Ilya Loginov | 2d4dc89 | 2009-11-26 09:16:19 +0100 | [diff] [blame] | 402 | #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 403 | extern void flush_dcache_page(struct page *); |
| 404 | |
Catalin Marinas | 826cbda | 2008-06-13 10:28:36 +0100 | [diff] [blame] | 405 | static inline void __flush_icache_all(void) |
| 406 | { |
Russell King | df71dfd | 2009-10-24 22:36:36 +0100 | [diff] [blame] | 407 | #ifdef CONFIG_ARM_ERRATA_411920 |
| 408 | extern void v6_icache_inval_all(void); |
| 409 | v6_icache_inval_all(); |
| 410 | #else |
Catalin Marinas | 826cbda | 2008-06-13 10:28:36 +0100 | [diff] [blame] | 411 | asm("mcr p15, 0, %0, c7, c5, 0 @ invalidate I-cache\n" |
| 412 | : |
| 413 | : "r" (0)); |
Russell King | df71dfd | 2009-10-24 22:36:36 +0100 | [diff] [blame] | 414 | #endif |
Catalin Marinas | 826cbda | 2008-06-13 10:28:36 +0100 | [diff] [blame] | 415 | } |
James Bottomley | 252a9af | 2010-01-25 11:42:22 -0600 | [diff] [blame] | 416 | static inline void flush_kernel_vmap_range(void *addr, int size) |
| 417 | { |
| 418 | if ((cache_is_vivt() || cache_is_vipt_aliasing())) |
| 419 | __cpuc_flush_dcache_area(addr, (size_t)size); |
| 420 | } |
| 421 | static inline void invalidate_kernel_vmap_range(void *addr, int size) |
| 422 | { |
| 423 | if ((cache_is_vivt() || cache_is_vipt_aliasing())) |
| 424 | __cpuc_flush_dcache_area(addr, (size_t)size); |
| 425 | } |
Catalin Marinas | 826cbda | 2008-06-13 10:28:36 +0100 | [diff] [blame] | 426 | |
Russell King | 6020dff | 2006-12-30 23:17:40 +0000 | [diff] [blame] | 427 | #define ARCH_HAS_FLUSH_ANON_PAGE |
| 428 | static inline void flush_anon_page(struct vm_area_struct *vma, |
| 429 | struct page *page, unsigned long vmaddr) |
| 430 | { |
| 431 | extern void __flush_anon_page(struct vm_area_struct *vma, |
| 432 | struct page *, unsigned long); |
| 433 | if (PageAnon(page)) |
| 434 | __flush_anon_page(vma, page, vmaddr); |
| 435 | } |
| 436 | |
Nicolas Pitre | 73be159 | 2009-06-12 03:09:29 +0100 | [diff] [blame] | 437 | #define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE |
| 438 | static inline void flush_kernel_dcache_page(struct page *page) |
| 439 | { |
| 440 | /* highmem pages are always flushed upon kunmap already */ |
| 441 | if ((cache_is_vivt() || cache_is_vipt_aliasing()) && !PageHighMem(page)) |
Russell King | 2c9b9c8 | 2009-11-26 12:56:21 +0000 | [diff] [blame] | 442 | __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE); |
Nicolas Pitre | 73be159 | 2009-06-12 03:09:29 +0100 | [diff] [blame] | 443 | } |
| 444 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 445 | #define flush_dcache_mmap_lock(mapping) \ |
Nick Piggin | 19fd623 | 2008-07-25 19:45:32 -0700 | [diff] [blame] | 446 | spin_lock_irq(&(mapping)->tree_lock) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 447 | #define flush_dcache_mmap_unlock(mapping) \ |
Nick Piggin | 19fd623 | 2008-07-25 19:45:32 -0700 | [diff] [blame] | 448 | spin_unlock_irq(&(mapping)->tree_lock) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 449 | |
| 450 | #define flush_icache_user_range(vma,page,addr,len) \ |
| 451 | flush_dcache_page(page) |
| 452 | |
| 453 | /* |
| 454 | * We don't appear to need to do anything here. In fact, if we did, we'd |
| 455 | * duplicate cache flushing elsewhere performed by flush_dcache_page(). |
| 456 | */ |
| 457 | #define flush_icache_page(vma,page) do { } while (0) |
| 458 | |
Catalin Marinas | 376e142 | 2008-11-06 13:23:08 +0000 | [diff] [blame] | 459 | /* |
| 460 | * flush_cache_vmap() is used when creating mappings (eg, via vmap, |
| 461 | * vmalloc, ioremap etc) in kernel space for pages. On non-VIPT |
| 462 | * caches, since the direct-mappings of these pages may contain cached |
| 463 | * data, we need to do a full cache flush to ensure that writebacks |
| 464 | * don't corrupt data placed into these pages via the new mappings. |
| 465 | */ |
| 466 | static inline void flush_cache_vmap(unsigned long start, unsigned long end) |
| 467 | { |
| 468 | if (!cache_is_vipt_nonaliasing()) |
| 469 | flush_cache_all(); |
| 470 | else |
| 471 | /* |
| 472 | * set_pte_at() called from vmap_pte_range() does not |
| 473 | * have a DSB after cleaning the cache line. |
| 474 | */ |
| 475 | dsb(); |
| 476 | } |
| 477 | |
| 478 | static inline void flush_cache_vunmap(unsigned long start, unsigned long end) |
| 479 | { |
| 480 | if (!cache_is_vipt_nonaliasing()) |
| 481 | flush_cache_all(); |
| 482 | } |
| 483 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 484 | #endif |