Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mm/mmu.c |
| 3 | * |
| 4 | * Copyright (C) 1995-2005 Russell King |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | */ |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 10 | #include <linux/module.h> |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 11 | #include <linux/kernel.h> |
| 12 | #include <linux/errno.h> |
| 13 | #include <linux/init.h> |
| 14 | #include <linux/bootmem.h> |
| 15 | #include <linux/mman.h> |
| 16 | #include <linux/nodemask.h> |
| 17 | |
Russell King | 0ba8b9b | 2008-08-10 18:08:10 +0100 | [diff] [blame] | 18 | #include <asm/cputype.h> |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 19 | #include <asm/mach-types.h> |
Russell King | 37efe64 | 2008-12-01 11:53:07 +0000 | [diff] [blame] | 20 | #include <asm/sections.h> |
Nicolas Pitre | 3f973e2 | 2008-11-04 00:48:42 -0500 | [diff] [blame] | 21 | #include <asm/cachetype.h> |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 22 | #include <asm/setup.h> |
| 23 | #include <asm/sizes.h> |
Russell King | e616c59 | 2009-09-27 20:55:43 +0100 | [diff] [blame] | 24 | #include <asm/smp_plat.h> |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 25 | #include <asm/tlb.h> |
Nicolas Pitre | d73cd42 | 2008-09-15 16:44:55 -0400 | [diff] [blame] | 26 | #include <asm/highmem.h> |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 27 | |
| 28 | #include <asm/mach/arch.h> |
| 29 | #include <asm/mach/map.h> |
| 30 | |
| 31 | #include "mm.h" |
| 32 | |
| 33 | DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); |
| 34 | |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 35 | /* |
| 36 | * empty_zero_page is a special page that is used for |
| 37 | * zero-initialized data and COW. |
| 38 | */ |
| 39 | struct page *empty_zero_page; |
Aneesh Kumar K.V | 3653f3a | 2008-04-29 08:11:12 -0400 | [diff] [blame] | 40 | EXPORT_SYMBOL(empty_zero_page); |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 41 | |
| 42 | /* |
| 43 | * The pmd table for the upper-most set of pages. |
| 44 | */ |
| 45 | pmd_t *top_pmd; |
| 46 | |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 47 | #define CPOLICY_UNCACHED 0 |
| 48 | #define CPOLICY_BUFFERED 1 |
| 49 | #define CPOLICY_WRITETHROUGH 2 |
| 50 | #define CPOLICY_WRITEBACK 3 |
| 51 | #define CPOLICY_WRITEALLOC 4 |
| 52 | |
| 53 | static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK; |
| 54 | static unsigned int ecc_mask __initdata = 0; |
Imre_Deak | 44b1869 | 2007-02-11 13:45:13 +0100 | [diff] [blame] | 55 | pgprot_t pgprot_user; |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 56 | pgprot_t pgprot_kernel; |
| 57 | |
Imre_Deak | 44b1869 | 2007-02-11 13:45:13 +0100 | [diff] [blame] | 58 | EXPORT_SYMBOL(pgprot_user); |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 59 | EXPORT_SYMBOL(pgprot_kernel); |
| 60 | |
| 61 | struct cachepolicy { |
| 62 | const char policy[16]; |
| 63 | unsigned int cr_mask; |
| 64 | unsigned int pmd; |
| 65 | unsigned int pte; |
| 66 | }; |
| 67 | |
| 68 | static struct cachepolicy cache_policies[] __initdata = { |
| 69 | { |
| 70 | .policy = "uncached", |
| 71 | .cr_mask = CR_W|CR_C, |
| 72 | .pmd = PMD_SECT_UNCACHED, |
Russell King | bb30f36 | 2008-09-06 20:04:59 +0100 | [diff] [blame] | 73 | .pte = L_PTE_MT_UNCACHED, |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 74 | }, { |
| 75 | .policy = "buffered", |
| 76 | .cr_mask = CR_C, |
| 77 | .pmd = PMD_SECT_BUFFERED, |
Russell King | bb30f36 | 2008-09-06 20:04:59 +0100 | [diff] [blame] | 78 | .pte = L_PTE_MT_BUFFERABLE, |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 79 | }, { |
| 80 | .policy = "writethrough", |
| 81 | .cr_mask = 0, |
| 82 | .pmd = PMD_SECT_WT, |
Russell King | bb30f36 | 2008-09-06 20:04:59 +0100 | [diff] [blame] | 83 | .pte = L_PTE_MT_WRITETHROUGH, |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 84 | }, { |
| 85 | .policy = "writeback", |
| 86 | .cr_mask = 0, |
| 87 | .pmd = PMD_SECT_WB, |
Russell King | bb30f36 | 2008-09-06 20:04:59 +0100 | [diff] [blame] | 88 | .pte = L_PTE_MT_WRITEBACK, |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 89 | }, { |
| 90 | .policy = "writealloc", |
| 91 | .cr_mask = 0, |
| 92 | .pmd = PMD_SECT_WBWA, |
Russell King | bb30f36 | 2008-09-06 20:04:59 +0100 | [diff] [blame] | 93 | .pte = L_PTE_MT_WRITEALLOC, |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 94 | } |
| 95 | }; |
| 96 | |
| 97 | /* |
Simon Arlott | 6cbdc8c | 2007-05-11 20:40:30 +0100 | [diff] [blame] | 98 | * These are useful for identifying cache coherency |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 99 | * problems by allowing the cache or the cache and |
| 100 | * writebuffer to be turned off. (Note: the write |
| 101 | * buffer should not be on and the cache off). |
| 102 | */ |
Jeremy Kerr | 2b0d8c2 | 2010-01-11 23:17:34 +0100 | [diff] [blame] | 103 | static int __init early_cachepolicy(char *p) |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 104 | { |
| 105 | int i; |
| 106 | |
| 107 | for (i = 0; i < ARRAY_SIZE(cache_policies); i++) { |
| 108 | int len = strlen(cache_policies[i].policy); |
| 109 | |
Jeremy Kerr | 2b0d8c2 | 2010-01-11 23:17:34 +0100 | [diff] [blame] | 110 | if (memcmp(p, cache_policies[i].policy, len) == 0) { |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 111 | cachepolicy = i; |
| 112 | cr_alignment &= ~cache_policies[i].cr_mask; |
| 113 | cr_no_alignment &= ~cache_policies[i].cr_mask; |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 114 | break; |
| 115 | } |
| 116 | } |
| 117 | if (i == ARRAY_SIZE(cache_policies)) |
| 118 | printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n"); |
Russell King | 4b46d64 | 2009-11-01 17:44:24 +0000 | [diff] [blame] | 119 | /* |
| 120 | * This restriction is partly to do with the way we boot; it is |
| 121 | * unpredictable to have memory mapped using two different sets of |
| 122 | * memory attributes (shared, type, and cache attribs). We can not |
| 123 | * change these attributes once the initial assembly has setup the |
| 124 | * page tables. |
| 125 | */ |
Catalin Marinas | 11179d8 | 2007-07-20 11:42:24 +0100 | [diff] [blame] | 126 | if (cpu_architecture() >= CPU_ARCH_ARMv6) { |
| 127 | printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n"); |
| 128 | cachepolicy = CPOLICY_WRITEBACK; |
| 129 | } |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 130 | flush_cache_all(); |
| 131 | set_cr(cr_alignment); |
Jeremy Kerr | 2b0d8c2 | 2010-01-11 23:17:34 +0100 | [diff] [blame] | 132 | return 0; |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 133 | } |
Jeremy Kerr | 2b0d8c2 | 2010-01-11 23:17:34 +0100 | [diff] [blame] | 134 | early_param("cachepolicy", early_cachepolicy); |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 135 | |
Jeremy Kerr | 2b0d8c2 | 2010-01-11 23:17:34 +0100 | [diff] [blame] | 136 | static int __init early_nocache(char *__unused) |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 137 | { |
| 138 | char *p = "buffered"; |
| 139 | printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p); |
Jeremy Kerr | 2b0d8c2 | 2010-01-11 23:17:34 +0100 | [diff] [blame] | 140 | early_cachepolicy(p); |
| 141 | return 0; |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 142 | } |
Jeremy Kerr | 2b0d8c2 | 2010-01-11 23:17:34 +0100 | [diff] [blame] | 143 | early_param("nocache", early_nocache); |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 144 | |
Jeremy Kerr | 2b0d8c2 | 2010-01-11 23:17:34 +0100 | [diff] [blame] | 145 | static int __init early_nowrite(char *__unused) |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 146 | { |
| 147 | char *p = "uncached"; |
| 148 | printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p); |
Jeremy Kerr | 2b0d8c2 | 2010-01-11 23:17:34 +0100 | [diff] [blame] | 149 | early_cachepolicy(p); |
| 150 | return 0; |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 151 | } |
Jeremy Kerr | 2b0d8c2 | 2010-01-11 23:17:34 +0100 | [diff] [blame] | 152 | early_param("nowb", early_nowrite); |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 153 | |
Jeremy Kerr | 2b0d8c2 | 2010-01-11 23:17:34 +0100 | [diff] [blame] | 154 | static int __init early_ecc(char *p) |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 155 | { |
Jeremy Kerr | 2b0d8c2 | 2010-01-11 23:17:34 +0100 | [diff] [blame] | 156 | if (memcmp(p, "on", 2) == 0) |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 157 | ecc_mask = PMD_PROTECTION; |
Jeremy Kerr | 2b0d8c2 | 2010-01-11 23:17:34 +0100 | [diff] [blame] | 158 | else if (memcmp(p, "off", 3) == 0) |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 159 | ecc_mask = 0; |
Jeremy Kerr | 2b0d8c2 | 2010-01-11 23:17:34 +0100 | [diff] [blame] | 160 | return 0; |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 161 | } |
Jeremy Kerr | 2b0d8c2 | 2010-01-11 23:17:34 +0100 | [diff] [blame] | 162 | early_param("ecc", early_ecc); |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 163 | |
| 164 | static int __init noalign_setup(char *__unused) |
| 165 | { |
| 166 | cr_alignment &= ~CR_A; |
| 167 | cr_no_alignment &= ~CR_A; |
| 168 | set_cr(cr_alignment); |
| 169 | return 1; |
| 170 | } |
| 171 | __setup("noalign", noalign_setup); |
| 172 | |
Russell King | 255d1f8 | 2006-12-18 00:12:47 +0000 | [diff] [blame] | 173 | #ifndef CONFIG_SMP |
| 174 | void adjust_cr(unsigned long mask, unsigned long set) |
| 175 | { |
| 176 | unsigned long flags; |
| 177 | |
| 178 | mask &= ~CR_A; |
| 179 | |
| 180 | set &= mask; |
| 181 | |
| 182 | local_irq_save(flags); |
| 183 | |
| 184 | cr_no_alignment = (cr_no_alignment & ~mask) | set; |
| 185 | cr_alignment = (cr_alignment & ~mask) | set; |
| 186 | |
| 187 | set_cr((get_cr() & ~mask) | set); |
| 188 | |
| 189 | local_irq_restore(flags); |
| 190 | } |
| 191 | #endif |
| 192 | |
Russell King | 0af92be | 2007-05-05 20:28:16 +0100 | [diff] [blame] | 193 | #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_WRITE |
Russell King | b1cce6b | 2008-11-04 10:52:28 +0000 | [diff] [blame] | 194 | #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE |
Russell King | 0af92be | 2007-05-05 20:28:16 +0100 | [diff] [blame] | 195 | |
Russell King | b29e9f5 | 2007-04-21 10:47:29 +0100 | [diff] [blame] | 196 | static struct mem_type mem_types[] = { |
Russell King | 0af92be | 2007-05-05 20:28:16 +0100 | [diff] [blame] | 197 | [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */ |
Russell King | bb30f36 | 2008-09-06 20:04:59 +0100 | [diff] [blame] | 198 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED | |
| 199 | L_PTE_SHARED, |
Russell King | 0af92be | 2007-05-05 20:28:16 +0100 | [diff] [blame] | 200 | .prot_l1 = PMD_TYPE_TABLE, |
Russell King | b1cce6b | 2008-11-04 10:52:28 +0000 | [diff] [blame] | 201 | .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S, |
Russell King | 0af92be | 2007-05-05 20:28:16 +0100 | [diff] [blame] | 202 | .domain = DOMAIN_IO, |
| 203 | }, |
| 204 | [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */ |
Russell King | bb30f36 | 2008-09-06 20:04:59 +0100 | [diff] [blame] | 205 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED, |
Russell King | 0af92be | 2007-05-05 20:28:16 +0100 | [diff] [blame] | 206 | .prot_l1 = PMD_TYPE_TABLE, |
Russell King | b1cce6b | 2008-11-04 10:52:28 +0000 | [diff] [blame] | 207 | .prot_sect = PROT_SECT_DEVICE, |
Russell King | 0af92be | 2007-05-05 20:28:16 +0100 | [diff] [blame] | 208 | .domain = DOMAIN_IO, |
| 209 | }, |
| 210 | [MT_DEVICE_CACHED] = { /* ioremap_cached */ |
Russell King | bb30f36 | 2008-09-06 20:04:59 +0100 | [diff] [blame] | 211 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED, |
Russell King | 0af92be | 2007-05-05 20:28:16 +0100 | [diff] [blame] | 212 | .prot_l1 = PMD_TYPE_TABLE, |
| 213 | .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB, |
| 214 | .domain = DOMAIN_IO, |
| 215 | }, |
Lennert Buytenhek | 1ad77a8 | 2008-09-05 13:17:11 +0100 | [diff] [blame] | 216 | [MT_DEVICE_WC] = { /* ioremap_wc */ |
Russell King | bb30f36 | 2008-09-06 20:04:59 +0100 | [diff] [blame] | 217 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC, |
Russell King | 0af92be | 2007-05-05 20:28:16 +0100 | [diff] [blame] | 218 | .prot_l1 = PMD_TYPE_TABLE, |
Russell King | b1cce6b | 2008-11-04 10:52:28 +0000 | [diff] [blame] | 219 | .prot_sect = PROT_SECT_DEVICE, |
Russell King | 0af92be | 2007-05-05 20:28:16 +0100 | [diff] [blame] | 220 | .domain = DOMAIN_IO, |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 221 | }, |
Russell King | ebb4c65 | 2008-11-09 11:18:36 +0000 | [diff] [blame] | 222 | [MT_UNCACHED] = { |
| 223 | .prot_pte = PROT_PTE_DEVICE, |
| 224 | .prot_l1 = PMD_TYPE_TABLE, |
| 225 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, |
| 226 | .domain = DOMAIN_IO, |
| 227 | }, |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 228 | [MT_CACHECLEAN] = { |
Russell King | 9ef7963 | 2007-05-05 20:03:35 +0100 | [diff] [blame] | 229 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 230 | .domain = DOMAIN_KERNEL, |
| 231 | }, |
| 232 | [MT_MINICLEAN] = { |
Russell King | 9ef7963 | 2007-05-05 20:03:35 +0100 | [diff] [blame] | 233 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE, |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 234 | .domain = DOMAIN_KERNEL, |
| 235 | }, |
| 236 | [MT_LOW_VECTORS] = { |
| 237 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
| 238 | L_PTE_EXEC, |
| 239 | .prot_l1 = PMD_TYPE_TABLE, |
| 240 | .domain = DOMAIN_USER, |
| 241 | }, |
| 242 | [MT_HIGH_VECTORS] = { |
| 243 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
| 244 | L_PTE_USER | L_PTE_EXEC, |
| 245 | .prot_l1 = PMD_TYPE_TABLE, |
| 246 | .domain = DOMAIN_USER, |
| 247 | }, |
| 248 | [MT_MEMORY] = { |
Russell King | 9ef7963 | 2007-05-05 20:03:35 +0100 | [diff] [blame] | 249 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 250 | .domain = DOMAIN_KERNEL, |
| 251 | }, |
| 252 | [MT_ROM] = { |
Russell King | 9ef7963 | 2007-05-05 20:03:35 +0100 | [diff] [blame] | 253 | .prot_sect = PMD_TYPE_SECT, |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 254 | .domain = DOMAIN_KERNEL, |
| 255 | }, |
Paul Walmsley | e4707dd | 2009-03-12 20:11:43 +0100 | [diff] [blame] | 256 | [MT_MEMORY_NONCACHED] = { |
| 257 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, |
| 258 | .domain = DOMAIN_KERNEL, |
| 259 | }, |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 260 | }; |
| 261 | |
Russell King | b29e9f5 | 2007-04-21 10:47:29 +0100 | [diff] [blame] | 262 | const struct mem_type *get_mem_type(unsigned int type) |
| 263 | { |
| 264 | return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL; |
| 265 | } |
Hiroshi DOYU | 69d3a84 | 2009-01-28 21:32:08 +0200 | [diff] [blame] | 266 | EXPORT_SYMBOL(get_mem_type); |
Russell King | b29e9f5 | 2007-04-21 10:47:29 +0100 | [diff] [blame] | 267 | |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 268 | /* |
| 269 | * Adjust the PMD section entries according to the CPU in use. |
| 270 | */ |
| 271 | static void __init build_mem_type_table(void) |
| 272 | { |
| 273 | struct cachepolicy *cp; |
| 274 | unsigned int cr = get_cr(); |
Russell King | bb30f36 | 2008-09-06 20:04:59 +0100 | [diff] [blame] | 275 | unsigned int user_pgprot, kern_pgprot, vecs_pgprot; |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 276 | int cpu_arch = cpu_architecture(); |
| 277 | int i; |
| 278 | |
Catalin Marinas | 11179d8 | 2007-07-20 11:42:24 +0100 | [diff] [blame] | 279 | if (cpu_arch < CPU_ARCH_ARMv6) { |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 280 | #if defined(CONFIG_CPU_DCACHE_DISABLE) |
Catalin Marinas | 11179d8 | 2007-07-20 11:42:24 +0100 | [diff] [blame] | 281 | if (cachepolicy > CPOLICY_BUFFERED) |
| 282 | cachepolicy = CPOLICY_BUFFERED; |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 283 | #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH) |
Catalin Marinas | 11179d8 | 2007-07-20 11:42:24 +0100 | [diff] [blame] | 284 | if (cachepolicy > CPOLICY_WRITETHROUGH) |
| 285 | cachepolicy = CPOLICY_WRITETHROUGH; |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 286 | #endif |
Catalin Marinas | 11179d8 | 2007-07-20 11:42:24 +0100 | [diff] [blame] | 287 | } |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 288 | if (cpu_arch < CPU_ARCH_ARMv5) { |
| 289 | if (cachepolicy >= CPOLICY_WRITEALLOC) |
| 290 | cachepolicy = CPOLICY_WRITEBACK; |
| 291 | ecc_mask = 0; |
| 292 | } |
Russell King | bb30f36 | 2008-09-06 20:04:59 +0100 | [diff] [blame] | 293 | #ifdef CONFIG_SMP |
| 294 | cachepolicy = CPOLICY_WRITEALLOC; |
| 295 | #endif |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 296 | |
| 297 | /* |
Russell King | b1cce6b | 2008-11-04 10:52:28 +0000 | [diff] [blame] | 298 | * Strip out features not present on earlier architectures. |
| 299 | * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those |
| 300 | * without extended page tables don't have the 'Shared' bit. |
Lennert Buytenhek | 1ad77a8 | 2008-09-05 13:17:11 +0100 | [diff] [blame] | 301 | */ |
Russell King | b1cce6b | 2008-11-04 10:52:28 +0000 | [diff] [blame] | 302 | if (cpu_arch < CPU_ARCH_ARMv5) |
| 303 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) |
| 304 | mem_types[i].prot_sect &= ~PMD_SECT_TEX(7); |
| 305 | if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3()) |
| 306 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) |
| 307 | mem_types[i].prot_sect &= ~PMD_SECT_S; |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 308 | |
| 309 | /* |
Russell King | b1cce6b | 2008-11-04 10:52:28 +0000 | [diff] [blame] | 310 | * ARMv5 and lower, bit 4 must be set for page tables (was: cache |
| 311 | * "update-able on write" bit on ARM610). However, Xscale and |
| 312 | * Xscale3 require this bit to be cleared. |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 313 | */ |
Russell King | b1cce6b | 2008-11-04 10:52:28 +0000 | [diff] [blame] | 314 | if (cpu_is_xscale() || cpu_is_xsc3()) { |
Russell King | 9ef7963 | 2007-05-05 20:03:35 +0100 | [diff] [blame] | 315 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 316 | mem_types[i].prot_sect &= ~PMD_BIT4; |
Russell King | 9ef7963 | 2007-05-05 20:03:35 +0100 | [diff] [blame] | 317 | mem_types[i].prot_l1 &= ~PMD_BIT4; |
| 318 | } |
| 319 | } else if (cpu_arch < CPU_ARCH_ARMv6) { |
| 320 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 321 | if (mem_types[i].prot_l1) |
| 322 | mem_types[i].prot_l1 |= PMD_BIT4; |
Russell King | 9ef7963 | 2007-05-05 20:03:35 +0100 | [diff] [blame] | 323 | if (mem_types[i].prot_sect) |
| 324 | mem_types[i].prot_sect |= PMD_BIT4; |
| 325 | } |
| 326 | } |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 327 | |
Russell King | b1cce6b | 2008-11-04 10:52:28 +0000 | [diff] [blame] | 328 | /* |
| 329 | * Mark the device areas according to the CPU/architecture. |
| 330 | */ |
| 331 | if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) { |
| 332 | if (!cpu_is_xsc3()) { |
| 333 | /* |
| 334 | * Mark device regions on ARMv6+ as execute-never |
| 335 | * to prevent speculative instruction fetches. |
| 336 | */ |
| 337 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN; |
| 338 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN; |
| 339 | mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN; |
| 340 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN; |
| 341 | } |
| 342 | if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { |
| 343 | /* |
| 344 | * For ARMv7 with TEX remapping, |
| 345 | * - shared device is SXCB=1100 |
| 346 | * - nonshared device is SXCB=0100 |
| 347 | * - write combine device mem is SXCB=0001 |
| 348 | * (Uncached Normal memory) |
| 349 | */ |
| 350 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1); |
| 351 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1); |
| 352 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE; |
| 353 | } else if (cpu_is_xsc3()) { |
| 354 | /* |
| 355 | * For Xscale3, |
| 356 | * - shared device is TEXCB=00101 |
| 357 | * - nonshared device is TEXCB=01000 |
| 358 | * - write combine device mem is TEXCB=00100 |
| 359 | * (Inner/Outer Uncacheable in xsc3 parlance) |
| 360 | */ |
| 361 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED; |
| 362 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2); |
| 363 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); |
| 364 | } else { |
| 365 | /* |
| 366 | * For ARMv6 and ARMv7 without TEX remapping, |
| 367 | * - shared device is TEXCB=00001 |
| 368 | * - nonshared device is TEXCB=01000 |
| 369 | * - write combine device mem is TEXCB=00100 |
| 370 | * (Uncached Normal in ARMv6 parlance). |
| 371 | */ |
| 372 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED; |
| 373 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2); |
| 374 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); |
| 375 | } |
| 376 | } else { |
| 377 | /* |
| 378 | * On others, write combining is "Uncached/Buffered" |
| 379 | */ |
| 380 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE; |
| 381 | } |
| 382 | |
| 383 | /* |
| 384 | * Now deal with the memory-type mappings |
| 385 | */ |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 386 | cp = &cache_policies[cachepolicy]; |
Russell King | bb30f36 | 2008-09-06 20:04:59 +0100 | [diff] [blame] | 387 | vecs_pgprot = kern_pgprot = user_pgprot = cp->pte; |
| 388 | |
| 389 | #ifndef CONFIG_SMP |
| 390 | /* |
| 391 | * Only use write-through for non-SMP systems |
| 392 | */ |
| 393 | if (cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH) |
| 394 | vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte; |
| 395 | #endif |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 396 | |
| 397 | /* |
| 398 | * Enable CPU-specific coherency if supported. |
| 399 | * (Only available on XSC3 at the moment.) |
| 400 | */ |
Russell King | b1cce6b | 2008-11-04 10:52:28 +0000 | [diff] [blame] | 401 | if (arch_is_coherent() && cpu_is_xsc3()) |
| 402 | mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 403 | |
| 404 | /* |
| 405 | * ARMv6 and above have extended page tables. |
| 406 | */ |
| 407 | if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) { |
| 408 | /* |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 409 | * Mark cache clean areas and XIP ROM read only |
| 410 | * from SVC mode and no access from userspace. |
| 411 | */ |
| 412 | mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; |
| 413 | mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; |
| 414 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; |
| 415 | |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 416 | #ifdef CONFIG_SMP |
| 417 | /* |
| 418 | * Mark memory with the "shared" attribute for SMP systems |
| 419 | */ |
| 420 | user_pgprot |= L_PTE_SHARED; |
| 421 | kern_pgprot |= L_PTE_SHARED; |
Russell King | bb30f36 | 2008-09-06 20:04:59 +0100 | [diff] [blame] | 422 | vecs_pgprot |= L_PTE_SHARED; |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 423 | mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; |
Paul Walmsley | e4707dd | 2009-03-12 20:11:43 +0100 | [diff] [blame] | 424 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S; |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 425 | #endif |
| 426 | } |
| 427 | |
Paul Walmsley | e4707dd | 2009-03-12 20:11:43 +0100 | [diff] [blame] | 428 | /* |
| 429 | * Non-cacheable Normal - intended for memory areas that must |
| 430 | * not cause dirty cache line writebacks when used |
| 431 | */ |
| 432 | if (cpu_arch >= CPU_ARCH_ARMv6) { |
| 433 | if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { |
| 434 | /* Non-cacheable Normal is XCB = 001 */ |
| 435 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= |
| 436 | PMD_SECT_BUFFERED; |
| 437 | } else { |
| 438 | /* For both ARMv6 and non-TEX-remapping ARMv7 */ |
| 439 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= |
| 440 | PMD_SECT_TEX(1); |
| 441 | } |
| 442 | } else { |
| 443 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE; |
| 444 | } |
| 445 | |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 446 | for (i = 0; i < 16; i++) { |
| 447 | unsigned long v = pgprot_val(protection_map[i]); |
Russell King | bb30f36 | 2008-09-06 20:04:59 +0100 | [diff] [blame] | 448 | protection_map[i] = __pgprot(v | user_pgprot); |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 449 | } |
| 450 | |
Russell King | bb30f36 | 2008-09-06 20:04:59 +0100 | [diff] [blame] | 451 | mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot; |
| 452 | mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot; |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 453 | |
Imre_Deak | 44b1869 | 2007-02-11 13:45:13 +0100 | [diff] [blame] | 454 | pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot); |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 455 | pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | |
Russell King | 6dc995a | 2009-12-24 10:16:21 +0000 | [diff] [blame] | 456 | L_PTE_DIRTY | L_PTE_WRITE | kern_pgprot); |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 457 | |
| 458 | mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask; |
| 459 | mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask; |
| 460 | mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd; |
| 461 | mem_types[MT_ROM].prot_sect |= cp->pmd; |
| 462 | |
| 463 | switch (cp->pmd) { |
| 464 | case PMD_SECT_WT: |
| 465 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT; |
| 466 | break; |
| 467 | case PMD_SECT_WB: |
| 468 | case PMD_SECT_WBWA: |
| 469 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB; |
| 470 | break; |
| 471 | } |
| 472 | printk("Memory policy: ECC %sabled, Data cache %s\n", |
| 473 | ecc_mask ? "en" : "dis", cp->policy); |
Russell King | 2497f0a | 2007-04-21 09:59:44 +0100 | [diff] [blame] | 474 | |
| 475 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { |
| 476 | struct mem_type *t = &mem_types[i]; |
| 477 | if (t->prot_l1) |
| 478 | t->prot_l1 |= PMD_DOMAIN(t->domain); |
| 479 | if (t->prot_sect) |
| 480 | t->prot_sect |= PMD_DOMAIN(t->domain); |
| 481 | } |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 482 | } |
| 483 | |
| 484 | #define vectors_base() (vectors_high() ? 0xffff0000 : 0) |
| 485 | |
Russell King | 24e6c69 | 2007-04-21 10:21:28 +0100 | [diff] [blame] | 486 | static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr, |
| 487 | unsigned long end, unsigned long pfn, |
| 488 | const struct mem_type *type) |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 489 | { |
Russell King | 24e6c69 | 2007-04-21 10:21:28 +0100 | [diff] [blame] | 490 | pte_t *pte; |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 491 | |
Russell King | 24e6c69 | 2007-04-21 10:21:28 +0100 | [diff] [blame] | 492 | if (pmd_none(*pmd)) { |
| 493 | pte = alloc_bootmem_low_pages(2 * PTRS_PER_PTE * sizeof(pte_t)); |
| 494 | __pmd_populate(pmd, __pa(pte) | type->prot_l1); |
| 495 | } |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 496 | |
Russell King | 24e6c69 | 2007-04-21 10:21:28 +0100 | [diff] [blame] | 497 | pte = pte_offset_kernel(pmd, addr); |
| 498 | do { |
Russell King | 40d192b | 2008-09-06 21:15:56 +0100 | [diff] [blame] | 499 | set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0); |
Russell King | 24e6c69 | 2007-04-21 10:21:28 +0100 | [diff] [blame] | 500 | pfn++; |
| 501 | } while (pte++, addr += PAGE_SIZE, addr != end); |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 502 | } |
| 503 | |
Russell King | 24e6c69 | 2007-04-21 10:21:28 +0100 | [diff] [blame] | 504 | static void __init alloc_init_section(pgd_t *pgd, unsigned long addr, |
| 505 | unsigned long end, unsigned long phys, |
| 506 | const struct mem_type *type) |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 507 | { |
Russell King | 24e6c69 | 2007-04-21 10:21:28 +0100 | [diff] [blame] | 508 | pmd_t *pmd = pmd_offset(pgd, addr); |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 509 | |
Russell King | 24e6c69 | 2007-04-21 10:21:28 +0100 | [diff] [blame] | 510 | /* |
| 511 | * Try a section mapping - end, addr and phys must all be aligned |
| 512 | * to a section boundary. Note that PMDs refer to the individual |
| 513 | * L1 entries, whereas PGDs refer to a group of L1 entries making |
| 514 | * up one logical pointer to an L2 table. |
| 515 | */ |
| 516 | if (((addr | end | phys) & ~SECTION_MASK) == 0) { |
| 517 | pmd_t *p = pmd; |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 518 | |
Russell King | 24e6c69 | 2007-04-21 10:21:28 +0100 | [diff] [blame] | 519 | if (addr & SECTION_SIZE) |
| 520 | pmd++; |
| 521 | |
| 522 | do { |
| 523 | *pmd = __pmd(phys | type->prot_sect); |
| 524 | phys += SECTION_SIZE; |
| 525 | } while (pmd++, addr += SECTION_SIZE, addr != end); |
| 526 | |
| 527 | flush_pmd_entry(p); |
| 528 | } else { |
| 529 | /* |
| 530 | * No need to loop; pte's aren't interested in the |
| 531 | * individual L1 entries. |
| 532 | */ |
| 533 | alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type); |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 534 | } |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 535 | } |
| 536 | |
Russell King | 4a56c1e | 2007-04-21 10:16:48 +0100 | [diff] [blame] | 537 | static void __init create_36bit_mapping(struct map_desc *md, |
| 538 | const struct mem_type *type) |
| 539 | { |
| 540 | unsigned long phys, addr, length, end; |
| 541 | pgd_t *pgd; |
| 542 | |
| 543 | addr = md->virtual; |
| 544 | phys = (unsigned long)__pfn_to_phys(md->pfn); |
| 545 | length = PAGE_ALIGN(md->length); |
| 546 | |
| 547 | if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) { |
| 548 | printk(KERN_ERR "MM: CPU does not support supersection " |
| 549 | "mapping for 0x%08llx at 0x%08lx\n", |
| 550 | __pfn_to_phys((u64)md->pfn), addr); |
| 551 | return; |
| 552 | } |
| 553 | |
| 554 | /* N.B. ARMv6 supersections are only defined to work with domain 0. |
| 555 | * Since domain assignments can in fact be arbitrary, the |
| 556 | * 'domain == 0' check below is required to insure that ARMv6 |
| 557 | * supersections are only allocated for domain 0 regardless |
| 558 | * of the actual domain assignments in use. |
| 559 | */ |
| 560 | if (type->domain) { |
| 561 | printk(KERN_ERR "MM: invalid domain in supersection " |
| 562 | "mapping for 0x%08llx at 0x%08lx\n", |
| 563 | __pfn_to_phys((u64)md->pfn), addr); |
| 564 | return; |
| 565 | } |
| 566 | |
| 567 | if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) { |
| 568 | printk(KERN_ERR "MM: cannot create mapping for " |
| 569 | "0x%08llx at 0x%08lx invalid alignment\n", |
| 570 | __pfn_to_phys((u64)md->pfn), addr); |
| 571 | return; |
| 572 | } |
| 573 | |
| 574 | /* |
| 575 | * Shift bits [35:32] of address into bits [23:20] of PMD |
| 576 | * (See ARMv6 spec). |
| 577 | */ |
| 578 | phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20); |
| 579 | |
| 580 | pgd = pgd_offset_k(addr); |
| 581 | end = addr + length; |
| 582 | do { |
| 583 | pmd_t *pmd = pmd_offset(pgd, addr); |
| 584 | int i; |
| 585 | |
| 586 | for (i = 0; i < 16; i++) |
| 587 | *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER); |
| 588 | |
| 589 | addr += SUPERSECTION_SIZE; |
| 590 | phys += SUPERSECTION_SIZE; |
| 591 | pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT; |
| 592 | } while (addr != end); |
| 593 | } |
| 594 | |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 595 | /* |
| 596 | * Create the page directory entries and any necessary |
| 597 | * page tables for the mapping specified by `md'. We |
| 598 | * are able to cope here with varying sizes and address |
| 599 | * offsets, and we take full advantage of sections and |
| 600 | * supersections. |
| 601 | */ |
| 602 | void __init create_mapping(struct map_desc *md) |
| 603 | { |
Russell King | 24e6c69 | 2007-04-21 10:21:28 +0100 | [diff] [blame] | 604 | unsigned long phys, addr, length, end; |
Russell King | d5c9817 | 2007-04-21 10:05:32 +0100 | [diff] [blame] | 605 | const struct mem_type *type; |
Russell King | 24e6c69 | 2007-04-21 10:21:28 +0100 | [diff] [blame] | 606 | pgd_t *pgd; |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 607 | |
| 608 | if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) { |
| 609 | printk(KERN_WARNING "BUG: not creating mapping for " |
| 610 | "0x%08llx at 0x%08lx in user region\n", |
| 611 | __pfn_to_phys((u64)md->pfn), md->virtual); |
| 612 | return; |
| 613 | } |
| 614 | |
| 615 | if ((md->type == MT_DEVICE || md->type == MT_ROM) && |
| 616 | md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) { |
| 617 | printk(KERN_WARNING "BUG: mapping for 0x%08llx at 0x%08lx " |
| 618 | "overlaps vmalloc space\n", |
| 619 | __pfn_to_phys((u64)md->pfn), md->virtual); |
| 620 | } |
| 621 | |
Russell King | d5c9817 | 2007-04-21 10:05:32 +0100 | [diff] [blame] | 622 | type = &mem_types[md->type]; |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 623 | |
| 624 | /* |
| 625 | * Catch 36-bit addresses |
| 626 | */ |
Russell King | 4a56c1e | 2007-04-21 10:16:48 +0100 | [diff] [blame] | 627 | if (md->pfn >= 0x100000) { |
| 628 | create_36bit_mapping(md, type); |
| 629 | return; |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 630 | } |
| 631 | |
Russell King | 7b9c7b4 | 2007-07-04 21:16:33 +0100 | [diff] [blame] | 632 | addr = md->virtual & PAGE_MASK; |
Russell King | 24e6c69 | 2007-04-21 10:21:28 +0100 | [diff] [blame] | 633 | phys = (unsigned long)__pfn_to_phys(md->pfn); |
Russell King | 7b9c7b4 | 2007-07-04 21:16:33 +0100 | [diff] [blame] | 634 | length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 635 | |
Russell King | 24e6c69 | 2007-04-21 10:21:28 +0100 | [diff] [blame] | 636 | if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) { |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 637 | printk(KERN_WARNING "BUG: map for 0x%08lx at 0x%08lx can not " |
| 638 | "be mapped using pages, ignoring.\n", |
Russell King | 24e6c69 | 2007-04-21 10:21:28 +0100 | [diff] [blame] | 639 | __pfn_to_phys(md->pfn), addr); |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 640 | return; |
| 641 | } |
| 642 | |
Russell King | 24e6c69 | 2007-04-21 10:21:28 +0100 | [diff] [blame] | 643 | pgd = pgd_offset_k(addr); |
| 644 | end = addr + length; |
| 645 | do { |
| 646 | unsigned long next = pgd_addr_end(addr, end); |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 647 | |
Russell King | 24e6c69 | 2007-04-21 10:21:28 +0100 | [diff] [blame] | 648 | alloc_init_section(pgd, addr, next, phys, type); |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 649 | |
Russell King | 24e6c69 | 2007-04-21 10:21:28 +0100 | [diff] [blame] | 650 | phys += next - addr; |
| 651 | addr = next; |
| 652 | } while (pgd++, addr != end); |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 653 | } |
| 654 | |
| 655 | /* |
| 656 | * Create the architecture specific mappings |
| 657 | */ |
| 658 | void __init iotable_init(struct map_desc *io_desc, int nr) |
| 659 | { |
| 660 | int i; |
| 661 | |
| 662 | for (i = 0; i < nr; i++) |
| 663 | create_mapping(io_desc + i); |
| 664 | } |
| 665 | |
Russell King | 6c5da7a | 2008-09-30 19:31:44 +0100 | [diff] [blame] | 666 | static unsigned long __initdata vmalloc_reserve = SZ_128M; |
| 667 | |
| 668 | /* |
| 669 | * vmalloc=size forces the vmalloc area to be exactly 'size' |
| 670 | * bytes. This can be used to increase (or decrease) the vmalloc |
| 671 | * area - the default is 128m. |
| 672 | */ |
Jeremy Kerr | 2b0d8c2 | 2010-01-11 23:17:34 +0100 | [diff] [blame] | 673 | static int __init early_vmalloc(char *arg) |
Russell King | 6c5da7a | 2008-09-30 19:31:44 +0100 | [diff] [blame] | 674 | { |
Jeremy Kerr | 2b0d8c2 | 2010-01-11 23:17:34 +0100 | [diff] [blame] | 675 | vmalloc_reserve = memparse(arg, NULL); |
Russell King | 6c5da7a | 2008-09-30 19:31:44 +0100 | [diff] [blame] | 676 | |
| 677 | if (vmalloc_reserve < SZ_16M) { |
| 678 | vmalloc_reserve = SZ_16M; |
| 679 | printk(KERN_WARNING |
| 680 | "vmalloc area too small, limiting to %luMB\n", |
| 681 | vmalloc_reserve >> 20); |
| 682 | } |
Nicolas Pitre | 9210807 | 2008-09-19 10:43:06 -0400 | [diff] [blame] | 683 | |
| 684 | if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) { |
| 685 | vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M); |
| 686 | printk(KERN_WARNING |
| 687 | "vmalloc area is too big, limiting to %luMB\n", |
| 688 | vmalloc_reserve >> 20); |
| 689 | } |
Jeremy Kerr | 2b0d8c2 | 2010-01-11 23:17:34 +0100 | [diff] [blame] | 690 | return 0; |
Russell King | 6c5da7a | 2008-09-30 19:31:44 +0100 | [diff] [blame] | 691 | } |
Jeremy Kerr | 2b0d8c2 | 2010-01-11 23:17:34 +0100 | [diff] [blame] | 692 | early_param("vmalloc", early_vmalloc); |
Russell King | 6c5da7a | 2008-09-30 19:31:44 +0100 | [diff] [blame] | 693 | |
| 694 | #define VMALLOC_MIN (void *)(VMALLOC_END - vmalloc_reserve) |
| 695 | |
Nicolas Pitre | 4b5f32c | 2008-10-06 13:24:40 -0400 | [diff] [blame] | 696 | static void __init sanity_check_meminfo(void) |
Lennert Buytenhek | 60296c7 | 2008-08-05 01:56:13 +0200 | [diff] [blame] | 697 | { |
Russell King | dde5828 | 2009-08-15 12:36:00 +0100 | [diff] [blame] | 698 | int i, j, highmem = 0; |
Lennert Buytenhek | 60296c7 | 2008-08-05 01:56:13 +0200 | [diff] [blame] | 699 | |
Nicolas Pitre | 4b5f32c | 2008-10-06 13:24:40 -0400 | [diff] [blame] | 700 | for (i = 0, j = 0; i < meminfo.nr_banks; i++) { |
Nicolas Pitre | a1bbaec | 2008-09-02 11:44:21 -0400 | [diff] [blame] | 701 | struct membank *bank = &meminfo.bank[j]; |
| 702 | *bank = meminfo.bank[i]; |
| 703 | |
| 704 | #ifdef CONFIG_HIGHMEM |
Russell King | dde5828 | 2009-08-15 12:36:00 +0100 | [diff] [blame] | 705 | if (__va(bank->start) > VMALLOC_MIN || |
| 706 | __va(bank->start) < (void *)PAGE_OFFSET) |
| 707 | highmem = 1; |
| 708 | |
| 709 | bank->highmem = highmem; |
| 710 | |
Nicolas Pitre | a1bbaec | 2008-09-02 11:44:21 -0400 | [diff] [blame] | 711 | /* |
| 712 | * Split those memory banks which are partially overlapping |
| 713 | * the vmalloc area greatly simplifying things later. |
| 714 | */ |
| 715 | if (__va(bank->start) < VMALLOC_MIN && |
| 716 | bank->size > VMALLOC_MIN - __va(bank->start)) { |
| 717 | if (meminfo.nr_banks >= NR_BANKS) { |
| 718 | printk(KERN_CRIT "NR_BANKS too low, " |
| 719 | "ignoring high memory\n"); |
| 720 | } else { |
| 721 | memmove(bank + 1, bank, |
| 722 | (meminfo.nr_banks - i) * sizeof(*bank)); |
| 723 | meminfo.nr_banks++; |
| 724 | i++; |
| 725 | bank[1].size -= VMALLOC_MIN - __va(bank->start); |
| 726 | bank[1].start = __pa(VMALLOC_MIN - 1) + 1; |
Russell King | dde5828 | 2009-08-15 12:36:00 +0100 | [diff] [blame] | 727 | bank[1].highmem = highmem = 1; |
Nicolas Pitre | a1bbaec | 2008-09-02 11:44:21 -0400 | [diff] [blame] | 728 | j++; |
| 729 | } |
| 730 | bank->size = VMALLOC_MIN - __va(bank->start); |
| 731 | } |
| 732 | #else |
Russell King | 041d785 | 2009-09-27 17:40:42 +0100 | [diff] [blame] | 733 | bank->highmem = highmem; |
| 734 | |
Nicolas Pitre | a1bbaec | 2008-09-02 11:44:21 -0400 | [diff] [blame] | 735 | /* |
| 736 | * Check whether this memory bank would entirely overlap |
| 737 | * the vmalloc area. |
| 738 | */ |
Nicolas Pitre | 3fd9825 | 2009-02-18 22:29:22 +0100 | [diff] [blame] | 739 | if (__va(bank->start) >= VMALLOC_MIN || |
Mikael Pettersson | f0bba9f | 2009-03-28 19:18:05 +0100 | [diff] [blame] | 740 | __va(bank->start) < (void *)PAGE_OFFSET) { |
Nicolas Pitre | a1bbaec | 2008-09-02 11:44:21 -0400 | [diff] [blame] | 741 | printk(KERN_NOTICE "Ignoring RAM at %.8lx-%.8lx " |
| 742 | "(vmalloc region overlap).\n", |
| 743 | bank->start, bank->start + bank->size - 1); |
| 744 | continue; |
| 745 | } |
| 746 | |
| 747 | /* |
| 748 | * Check whether this memory bank would partially overlap |
| 749 | * the vmalloc area. |
| 750 | */ |
| 751 | if (__va(bank->start + bank->size) > VMALLOC_MIN || |
| 752 | __va(bank->start + bank->size) < __va(bank->start)) { |
| 753 | unsigned long newsize = VMALLOC_MIN - __va(bank->start); |
| 754 | printk(KERN_NOTICE "Truncating RAM at %.8lx-%.8lx " |
| 755 | "to -%.8lx (vmalloc region overlap).\n", |
| 756 | bank->start, bank->start + bank->size - 1, |
| 757 | bank->start + newsize - 1); |
| 758 | bank->size = newsize; |
| 759 | } |
| 760 | #endif |
| 761 | j++; |
Lennert Buytenhek | 60296c7 | 2008-08-05 01:56:13 +0200 | [diff] [blame] | 762 | } |
Russell King | e616c59 | 2009-09-27 20:55:43 +0100 | [diff] [blame] | 763 | #ifdef CONFIG_HIGHMEM |
| 764 | if (highmem) { |
| 765 | const char *reason = NULL; |
| 766 | |
| 767 | if (cache_is_vipt_aliasing()) { |
| 768 | /* |
| 769 | * Interactions between kmap and other mappings |
| 770 | * make highmem support with aliasing VIPT caches |
| 771 | * rather difficult. |
| 772 | */ |
| 773 | reason = "with VIPT aliasing cache"; |
| 774 | #ifdef CONFIG_SMP |
| 775 | } else if (tlb_ops_need_broadcast()) { |
| 776 | /* |
| 777 | * kmap_high needs to occasionally flush TLB entries, |
| 778 | * however, if the TLB entries need to be broadcast |
| 779 | * we may deadlock: |
| 780 | * kmap_high(irqs off)->flush_all_zero_pkmaps-> |
| 781 | * flush_tlb_kernel_range->smp_call_function_many |
| 782 | * (must not be called with irqs off) |
| 783 | */ |
| 784 | reason = "without hardware TLB ops broadcasting"; |
| 785 | #endif |
| 786 | } |
| 787 | if (reason) { |
| 788 | printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n", |
| 789 | reason); |
| 790 | while (j > 0 && meminfo.bank[j - 1].highmem) |
| 791 | j--; |
| 792 | } |
| 793 | } |
| 794 | #endif |
Nicolas Pitre | 4b5f32c | 2008-10-06 13:24:40 -0400 | [diff] [blame] | 795 | meminfo.nr_banks = j; |
Lennert Buytenhek | 60296c7 | 2008-08-05 01:56:13 +0200 | [diff] [blame] | 796 | } |
| 797 | |
Nicolas Pitre | 4b5f32c | 2008-10-06 13:24:40 -0400 | [diff] [blame] | 798 | static inline void prepare_page_table(void) |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 799 | { |
| 800 | unsigned long addr; |
| 801 | |
| 802 | /* |
| 803 | * Clear out all the mappings below the kernel image. |
| 804 | */ |
Russell King | ab4f2ee | 2008-11-06 17:11:07 +0000 | [diff] [blame] | 805 | for (addr = 0; addr < MODULES_VADDR; addr += PGDIR_SIZE) |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 806 | pmd_clear(pmd_off_k(addr)); |
| 807 | |
| 808 | #ifdef CONFIG_XIP_KERNEL |
| 809 | /* The XIP kernel is mapped in the module area -- skip over it */ |
Russell King | 37efe64 | 2008-12-01 11:53:07 +0000 | [diff] [blame] | 810 | addr = ((unsigned long)_etext + PGDIR_SIZE - 1) & PGDIR_MASK; |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 811 | #endif |
| 812 | for ( ; addr < PAGE_OFFSET; addr += PGDIR_SIZE) |
| 813 | pmd_clear(pmd_off_k(addr)); |
| 814 | |
| 815 | /* |
| 816 | * Clear out all the kernel space mappings, except for the first |
| 817 | * memory bank, up to the end of the vmalloc region. |
| 818 | */ |
Nicolas Pitre | 4b5f32c | 2008-10-06 13:24:40 -0400 | [diff] [blame] | 819 | for (addr = __phys_to_virt(bank_phys_end(&meminfo.bank[0])); |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 820 | addr < VMALLOC_END; addr += PGDIR_SIZE) |
| 821 | pmd_clear(pmd_off_k(addr)); |
| 822 | } |
| 823 | |
| 824 | /* |
| 825 | * Reserve the various regions of node 0 |
| 826 | */ |
| 827 | void __init reserve_node_zero(pg_data_t *pgdat) |
| 828 | { |
| 829 | unsigned long res_size = 0; |
| 830 | |
| 831 | /* |
| 832 | * Register the kernel text and data with bootmem. |
| 833 | * Note that this can only be in node 0. |
| 834 | */ |
| 835 | #ifdef CONFIG_XIP_KERNEL |
Russell King | 37efe64 | 2008-12-01 11:53:07 +0000 | [diff] [blame] | 836 | reserve_bootmem_node(pgdat, __pa(_data), _end - _data, |
Bernhard Walle | 72a7fe3 | 2008-02-07 00:15:17 -0800 | [diff] [blame] | 837 | BOOTMEM_DEFAULT); |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 838 | #else |
Russell King | 37efe64 | 2008-12-01 11:53:07 +0000 | [diff] [blame] | 839 | reserve_bootmem_node(pgdat, __pa(_stext), _end - _stext, |
Bernhard Walle | 72a7fe3 | 2008-02-07 00:15:17 -0800 | [diff] [blame] | 840 | BOOTMEM_DEFAULT); |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 841 | #endif |
| 842 | |
| 843 | /* |
| 844 | * Reserve the page tables. These are already in use, |
| 845 | * and can only be in node 0. |
| 846 | */ |
| 847 | reserve_bootmem_node(pgdat, __pa(swapper_pg_dir), |
Bernhard Walle | 72a7fe3 | 2008-02-07 00:15:17 -0800 | [diff] [blame] | 848 | PTRS_PER_PGD * sizeof(pgd_t), BOOTMEM_DEFAULT); |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 849 | |
| 850 | /* |
| 851 | * Hmm... This should go elsewhere, but we really really need to |
| 852 | * stop things allocating the low memory; ideally we need a better |
| 853 | * implementation of GFP_DMA which does not assume that DMA-able |
| 854 | * memory starts at zero. |
| 855 | */ |
| 856 | if (machine_is_integrator() || machine_is_cintegrator()) |
| 857 | res_size = __pa(swapper_pg_dir) - PHYS_OFFSET; |
| 858 | |
| 859 | /* |
| 860 | * These should likewise go elsewhere. They pre-reserve the |
| 861 | * screen memory region at the start of main system memory. |
| 862 | */ |
| 863 | if (machine_is_edb7211()) |
| 864 | res_size = 0x00020000; |
| 865 | if (machine_is_p720t()) |
| 866 | res_size = 0x00014000; |
| 867 | |
Ben Dooks | bbf6f28 | 2006-12-07 20:47:58 +0100 | [diff] [blame] | 868 | /* H1940 and RX3715 need to reserve this for suspend */ |
| 869 | |
| 870 | if (machine_is_h1940() || machine_is_rx3715()) { |
Bernhard Walle | 72a7fe3 | 2008-02-07 00:15:17 -0800 | [diff] [blame] | 871 | reserve_bootmem_node(pgdat, 0x30003000, 0x1000, |
| 872 | BOOTMEM_DEFAULT); |
| 873 | reserve_bootmem_node(pgdat, 0x30081000, 0x1000, |
| 874 | BOOTMEM_DEFAULT); |
Ben Dooks | 9073341 | 2006-12-06 01:50:24 +0100 | [diff] [blame] | 875 | } |
| 876 | |
Marek Vasut | 81854f8 | 2009-03-28 12:37:42 +0100 | [diff] [blame] | 877 | if (machine_is_palmld() || machine_is_palmtx()) { |
| 878 | reserve_bootmem_node(pgdat, 0xa0000000, 0x1000, |
| 879 | BOOTMEM_EXCLUSIVE); |
| 880 | reserve_bootmem_node(pgdat, 0xa0200000, 0x1000, |
| 881 | BOOTMEM_EXCLUSIVE); |
| 882 | } |
| 883 | |
Tomáš Čech | d0a92fd | 2009-09-11 13:57:02 +0200 | [diff] [blame] | 884 | if (machine_is_treo680() || machine_is_centro()) { |
Tomas 'Sleep_Walker' Cech | e6c3f4b | 2009-05-18 15:24:14 +0200 | [diff] [blame] | 885 | reserve_bootmem_node(pgdat, 0xa0000000, 0x1000, |
| 886 | BOOTMEM_EXCLUSIVE); |
| 887 | reserve_bootmem_node(pgdat, 0xa2000000, 0x1000, |
| 888 | BOOTMEM_EXCLUSIVE); |
| 889 | } |
| 890 | |
Marek Vasut | 81854f8 | 2009-03-28 12:37:42 +0100 | [diff] [blame] | 891 | if (machine_is_palmt5()) |
| 892 | reserve_bootmem_node(pgdat, 0xa0200000, 0x1000, |
| 893 | BOOTMEM_EXCLUSIVE); |
| 894 | |
Linus Walleij | d98aac7 | 2009-04-27 10:21:46 +0100 | [diff] [blame] | 895 | /* |
| 896 | * U300 - This platform family can share physical memory |
| 897 | * between two ARM cpus, one running Linux and the other |
| 898 | * running another OS. |
| 899 | */ |
| 900 | if (machine_is_u300()) { |
| 901 | #ifdef CONFIG_MACH_U300_SINGLE_RAM |
| 902 | #if ((CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1) == 1) && \ |
| 903 | CONFIG_MACH_U300_2MB_ALIGNMENT_FIX |
| 904 | res_size = 0x00100000; |
| 905 | #endif |
| 906 | #endif |
| 907 | } |
| 908 | |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 909 | #ifdef CONFIG_SA1111 |
| 910 | /* |
| 911 | * Because of the SA1111 DMA bug, we want to preserve our |
| 912 | * precious DMA-able memory... |
| 913 | */ |
| 914 | res_size = __pa(swapper_pg_dir) - PHYS_OFFSET; |
| 915 | #endif |
| 916 | if (res_size) |
Bernhard Walle | 72a7fe3 | 2008-02-07 00:15:17 -0800 | [diff] [blame] | 917 | reserve_bootmem_node(pgdat, PHYS_OFFSET, res_size, |
| 918 | BOOTMEM_DEFAULT); |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 919 | } |
| 920 | |
| 921 | /* |
| 922 | * Set up device the mappings. Since we clear out the page tables for all |
| 923 | * mappings above VMALLOC_END, we will remove any debug device mappings. |
| 924 | * This means you have to be careful how you debug this function, or any |
| 925 | * called function. This means you can't use any function or debugging |
| 926 | * method which may touch any device, otherwise the kernel _will_ crash. |
| 927 | */ |
| 928 | static void __init devicemaps_init(struct machine_desc *mdesc) |
| 929 | { |
| 930 | struct map_desc map; |
| 931 | unsigned long addr; |
| 932 | void *vectors; |
| 933 | |
| 934 | /* |
| 935 | * Allocate the vector page early. |
| 936 | */ |
| 937 | vectors = alloc_bootmem_low_pages(PAGE_SIZE); |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 938 | |
| 939 | for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE) |
| 940 | pmd_clear(pmd_off_k(addr)); |
| 941 | |
| 942 | /* |
| 943 | * Map the kernel if it is XIP. |
| 944 | * It is always first in the modulearea. |
| 945 | */ |
| 946 | #ifdef CONFIG_XIP_KERNEL |
| 947 | map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK); |
Russell King | ab4f2ee | 2008-11-06 17:11:07 +0000 | [diff] [blame] | 948 | map.virtual = MODULES_VADDR; |
Russell King | 37efe64 | 2008-12-01 11:53:07 +0000 | [diff] [blame] | 949 | map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK; |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 950 | map.type = MT_ROM; |
| 951 | create_mapping(&map); |
| 952 | #endif |
| 953 | |
| 954 | /* |
| 955 | * Map the cache flushing regions. |
| 956 | */ |
| 957 | #ifdef FLUSH_BASE |
| 958 | map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS); |
| 959 | map.virtual = FLUSH_BASE; |
| 960 | map.length = SZ_1M; |
| 961 | map.type = MT_CACHECLEAN; |
| 962 | create_mapping(&map); |
| 963 | #endif |
| 964 | #ifdef FLUSH_BASE_MINICACHE |
| 965 | map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M); |
| 966 | map.virtual = FLUSH_BASE_MINICACHE; |
| 967 | map.length = SZ_1M; |
| 968 | map.type = MT_MINICLEAN; |
| 969 | create_mapping(&map); |
| 970 | #endif |
| 971 | |
| 972 | /* |
| 973 | * Create a mapping for the machine vectors at the high-vectors |
| 974 | * location (0xffff0000). If we aren't using high-vectors, also |
| 975 | * create a mapping at the low-vectors virtual address. |
| 976 | */ |
| 977 | map.pfn = __phys_to_pfn(virt_to_phys(vectors)); |
| 978 | map.virtual = 0xffff0000; |
| 979 | map.length = PAGE_SIZE; |
| 980 | map.type = MT_HIGH_VECTORS; |
| 981 | create_mapping(&map); |
| 982 | |
| 983 | if (!vectors_high()) { |
| 984 | map.virtual = 0; |
| 985 | map.type = MT_LOW_VECTORS; |
| 986 | create_mapping(&map); |
| 987 | } |
| 988 | |
| 989 | /* |
| 990 | * Ask the machine support to map in the statically mapped devices. |
| 991 | */ |
| 992 | if (mdesc->map_io) |
| 993 | mdesc->map_io(); |
| 994 | |
| 995 | /* |
| 996 | * Finally flush the caches and tlb to ensure that we're in a |
| 997 | * consistent state wrt the writebuffer. This also ensures that |
| 998 | * any write-allocated cache lines in the vector page are written |
| 999 | * back. After this point, we can start to touch devices again. |
| 1000 | */ |
| 1001 | local_flush_tlb_all(); |
| 1002 | flush_cache_all(); |
| 1003 | } |
| 1004 | |
Nicolas Pitre | d73cd42 | 2008-09-15 16:44:55 -0400 | [diff] [blame] | 1005 | static void __init kmap_init(void) |
| 1006 | { |
| 1007 | #ifdef CONFIG_HIGHMEM |
| 1008 | pmd_t *pmd = pmd_off_k(PKMAP_BASE); |
| 1009 | pte_t *pte = alloc_bootmem_low_pages(2 * PTRS_PER_PTE * sizeof(pte_t)); |
| 1010 | BUG_ON(!pmd_none(*pmd) || !pte); |
| 1011 | __pmd_populate(pmd, __pa(pte) | _PAGE_KERNEL_TABLE); |
| 1012 | pkmap_page_table = pte + PTRS_PER_PTE; |
| 1013 | #endif |
| 1014 | } |
| 1015 | |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 1016 | /* |
| 1017 | * paging_init() sets up the page tables, initialises the zone memory |
| 1018 | * maps, and sets up the zero page, bad page and bad page tables. |
| 1019 | */ |
Nicolas Pitre | 4b5f32c | 2008-10-06 13:24:40 -0400 | [diff] [blame] | 1020 | void __init paging_init(struct machine_desc *mdesc) |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 1021 | { |
| 1022 | void *zero_page; |
| 1023 | |
| 1024 | build_mem_type_table(); |
Nicolas Pitre | 4b5f32c | 2008-10-06 13:24:40 -0400 | [diff] [blame] | 1025 | sanity_check_meminfo(); |
| 1026 | prepare_page_table(); |
| 1027 | bootmem_init(); |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 1028 | devicemaps_init(mdesc); |
Nicolas Pitre | d73cd42 | 2008-09-15 16:44:55 -0400 | [diff] [blame] | 1029 | kmap_init(); |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 1030 | |
| 1031 | top_pmd = pmd_off_k(0xffff0000); |
| 1032 | |
| 1033 | /* |
Julia Lawall | 6ce1b87 | 2008-12-01 14:15:41 -0800 | [diff] [blame] | 1034 | * allocate the zero page. Note that this always succeeds and |
| 1035 | * returns a zeroed result. |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 1036 | */ |
| 1037 | zero_page = alloc_bootmem_low_pages(PAGE_SIZE); |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 1038 | empty_zero_page = virt_to_page(zero_page); |
Russell King | 421fe93 | 2009-10-25 10:23:04 +0000 | [diff] [blame] | 1039 | __flush_dcache_page(NULL, empty_zero_page); |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 1040 | } |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 1041 | |
| 1042 | /* |
| 1043 | * In order to soft-boot, we need to insert a 1:1 mapping in place of |
| 1044 | * the user-mode pages. This will then ensure that we have predictable |
| 1045 | * results when turning the mmu off |
| 1046 | */ |
| 1047 | void setup_mm_for_reboot(char mode) |
| 1048 | { |
| 1049 | unsigned long base_pmdval; |
| 1050 | pgd_t *pgd; |
| 1051 | int i; |
| 1052 | |
| 1053 | if (current->mm && current->mm->pgd) |
| 1054 | pgd = current->mm->pgd; |
| 1055 | else |
| 1056 | pgd = init_mm.pgd; |
| 1057 | |
| 1058 | base_pmdval = PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT; |
| 1059 | if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale()) |
| 1060 | base_pmdval |= PMD_BIT4; |
| 1061 | |
| 1062 | for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++, pgd++) { |
| 1063 | unsigned long pmdval = (i << PGDIR_SHIFT) | base_pmdval; |
| 1064 | pmd_t *pmd; |
| 1065 | |
| 1066 | pmd = pmd_off(pgd, i << PGDIR_SHIFT); |
| 1067 | pmd[0] = __pmd(pmdval); |
| 1068 | pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1))); |
| 1069 | flush_pmd_entry(pmd); |
| 1070 | } |
Tony Lindgren | ad3e6c0 | 2010-01-19 16:42:12 +0100 | [diff] [blame] | 1071 | |
| 1072 | local_flush_tlb_all(); |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 1073 | } |