| Liam Girdwood | eb1a6af | 2006-10-06 18:34:51 +0200 | [diff] [blame] | 1 | ASoC currently supports the three main Digital Audio Interfaces (DAI) found on |
| 2 | SoC controllers and portable audio CODECS today, namely AC97, I2S and PCM. |
| 3 | |
| 4 | |
| 5 | AC97 |
| 6 | ==== |
| 7 | |
| 8 | AC97 is a five wire interface commonly found on many PC sound cards. It is |
| 9 | now also popular in many portable devices. This DAI has a reset line and time |
| 10 | multiplexes its data on its SDATA_OUT (playback) and SDATA_IN (capture) lines. |
| 11 | The bit clock (BCLK) is always driven by the CODEC (usually 12.288MHz) and the |
| 12 | frame (FRAME) (usually 48kHz) is always driven by the controller. Each AC97 |
| 13 | frame is 21uS long and is divided into 13 time slots. |
| 14 | |
| Liam Girdwood | a71a468 | 2006-10-19 20:35:56 +0200 | [diff] [blame] | 15 | The AC97 specification can be found at :- |
| 16 | http://www.intel.com/design/chipsets/audio/ac97_r23.pdf |
| Liam Girdwood | eb1a6af | 2006-10-06 18:34:51 +0200 | [diff] [blame] | 17 | |
| 18 | |
| 19 | I2S |
| 20 | === |
| 21 | |
| 22 | I2S is a common 4 wire DAI used in HiFi, STB and portable devices. The Tx and |
| 23 | Rx lines are used for audio transmision, whilst the bit clock (BCLK) and |
| 24 | left/right clock (LRC) synchronise the link. I2S is flexible in that either the |
| 25 | controller or CODEC can drive (master) the BCLK and LRC clock lines. Bit clock |
| 26 | usually varies depending on the sample rate and the master system clock |
| 27 | (SYSCLK). LRCLK is the same as the sample rate. A few devices support separate |
| 28 | ADC and DAC LRCLK's, this allows for similtanious capture and playback at |
| 29 | different sample rates. |
| 30 | |
| 31 | I2S has several different operating modes:- |
| 32 | |
| 33 | o I2S - MSB is transmitted on the falling edge of the first BCLK after LRC |
| 34 | transition. |
| 35 | |
| 36 | o Left Justified - MSB is transmitted on transition of LRC. |
| 37 | |
| 38 | o Right Justified - MSB is transmitted sample size BCLK's before LRC |
| 39 | transition. |
| 40 | |
| 41 | PCM |
| 42 | === |
| 43 | |
| 44 | PCM is another 4 wire interface, very similar to I2S, that can support a more |
| 45 | flexible protocol. It has bit clock (BCLK) and sync (SYNC) lines that are used |
| 46 | to synchronise the link whilst the Tx and Rx lines are used to transmit and |
| 47 | receive the audio data. Bit clock usually varies depending on sample rate |
| 48 | whilst sync runs at the sample rate. PCM also supports Time Division |
| 49 | Multiplexing (TDM) in that several devices can use the bus similtaniuosly (This |
| 50 | is sometimes referred to as network mode). |
| 51 | |
| 52 | Common PCM operating modes:- |
| 53 | |
| 54 | o Mode A - MSB is transmitted on falling edge of first BCLK after FRAME/SYNC. |
| 55 | |
| 56 | o Mode B - MSB is transmitted on rising edge of FRAME/SYNC. |