Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* $Id: ultra.S,v 1.72 2002/02/09 19:49:31 davem Exp $ |
| 2 | * ultra.S: Don't expand these all over the place... |
| 3 | * |
| 4 | * Copyright (C) 1997, 2000 David S. Miller (davem@redhat.com) |
| 5 | */ |
| 6 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7 | #include <asm/asi.h> |
| 8 | #include <asm/pgtable.h> |
| 9 | #include <asm/page.h> |
| 10 | #include <asm/spitfire.h> |
| 11 | #include <asm/mmu_context.h> |
David S. Miller | 2ef2777 | 2005-08-30 20:21:34 -0700 | [diff] [blame] | 12 | #include <asm/mmu.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13 | #include <asm/pil.h> |
| 14 | #include <asm/head.h> |
| 15 | #include <asm/thread_info.h> |
| 16 | #include <asm/cacheflush.h> |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 17 | #include <asm/hypervisor.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 18 | |
| 19 | /* Basically, most of the Spitfire vs. Cheetah madness |
| 20 | * has to do with the fact that Cheetah does not support |
| 21 | * IMMU flushes out of the secondary context. Someone needs |
| 22 | * to throw a south lake birthday party for the folks |
| 23 | * in Microelectronics who refused to fix this shit. |
| 24 | */ |
| 25 | |
| 26 | /* This file is meant to be read efficiently by the CPU, not humans. |
| 27 | * Staraj sie tego nikomu nie pierdolnac... |
| 28 | */ |
| 29 | .text |
| 30 | .align 32 |
| 31 | .globl __flush_tlb_mm |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 32 | __flush_tlb_mm: /* 18 insns */ |
| 33 | /* %o0=(ctx & TAG_CONTEXT_BITS), %o1=SECONDARY_CONTEXT */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 34 | ldxa [%o1] ASI_DMMU, %g2 |
| 35 | cmp %g2, %o0 |
| 36 | bne,pn %icc, __spitfire_flush_tlb_mm_slow |
| 37 | mov 0x50, %g3 |
| 38 | stxa %g0, [%g3] ASI_DMMU_DEMAP |
| 39 | stxa %g0, [%g3] ASI_IMMU_DEMAP |
David S. Miller | 4da808c | 2006-01-31 18:33:00 -0800 | [diff] [blame] | 40 | sethi %hi(KERNBASE), %g3 |
| 41 | flush %g3 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 42 | retl |
David S. Miller | 4da808c | 2006-01-31 18:33:00 -0800 | [diff] [blame] | 43 | nop |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 44 | nop |
| 45 | nop |
| 46 | nop |
| 47 | nop |
| 48 | nop |
| 49 | nop |
| 50 | nop |
David S. Miller | 2ef2777 | 2005-08-30 20:21:34 -0700 | [diff] [blame] | 51 | nop |
| 52 | nop |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 53 | |
| 54 | .align 32 |
| 55 | .globl __flush_tlb_pending |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 56 | __flush_tlb_pending: /* 26 insns */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 57 | /* %o0 = context, %o1 = nr, %o2 = vaddrs[] */ |
| 58 | rdpr %pstate, %g7 |
| 59 | sllx %o1, 3, %o1 |
| 60 | andn %g7, PSTATE_IE, %g2 |
| 61 | wrpr %g2, %pstate |
| 62 | mov SECONDARY_CONTEXT, %o4 |
| 63 | ldxa [%o4] ASI_DMMU, %g2 |
| 64 | stxa %o0, [%o4] ASI_DMMU |
| 65 | 1: sub %o1, (1 << 3), %o1 |
| 66 | ldx [%o2 + %o1], %o3 |
| 67 | andcc %o3, 1, %g0 |
| 68 | andn %o3, 1, %o3 |
| 69 | be,pn %icc, 2f |
| 70 | or %o3, 0x10, %o3 |
| 71 | stxa %g0, [%o3] ASI_IMMU_DEMAP |
| 72 | 2: stxa %g0, [%o3] ASI_DMMU_DEMAP |
| 73 | membar #Sync |
| 74 | brnz,pt %o1, 1b |
| 75 | nop |
| 76 | stxa %g2, [%o4] ASI_DMMU |
David S. Miller | 4da808c | 2006-01-31 18:33:00 -0800 | [diff] [blame] | 77 | sethi %hi(KERNBASE), %o4 |
| 78 | flush %o4 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 79 | retl |
| 80 | wrpr %g7, 0x0, %pstate |
David S. Miller | fef43da | 2005-07-05 19:45:24 -0700 | [diff] [blame] | 81 | nop |
David S. Miller | 2ef2777 | 2005-08-30 20:21:34 -0700 | [diff] [blame] | 82 | nop |
| 83 | nop |
| 84 | nop |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 85 | |
| 86 | .align 32 |
| 87 | .globl __flush_tlb_kernel_range |
David S. Miller | 1daef08 | 2006-02-15 20:35:10 -0800 | [diff] [blame] | 88 | __flush_tlb_kernel_range: /* 16 insns */ |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 89 | /* %o0=start, %o1=end */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 90 | cmp %o0, %o1 |
| 91 | be,pn %xcc, 2f |
| 92 | sethi %hi(PAGE_SIZE), %o4 |
| 93 | sub %o1, %o0, %o3 |
| 94 | sub %o3, %o4, %o3 |
| 95 | or %o0, 0x20, %o0 ! Nucleus |
| 96 | 1: stxa %g0, [%o0 + %o3] ASI_DMMU_DEMAP |
| 97 | stxa %g0, [%o0 + %o3] ASI_IMMU_DEMAP |
| 98 | membar #Sync |
| 99 | brnz,pt %o3, 1b |
| 100 | sub %o3, %o4, %o3 |
David S. Miller | 4da808c | 2006-01-31 18:33:00 -0800 | [diff] [blame] | 101 | 2: sethi %hi(KERNBASE), %o3 |
| 102 | flush %o3 |
| 103 | retl |
| 104 | nop |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 105 | nop |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 106 | |
| 107 | __spitfire_flush_tlb_mm_slow: |
| 108 | rdpr %pstate, %g1 |
| 109 | wrpr %g1, PSTATE_IE, %pstate |
| 110 | stxa %o0, [%o1] ASI_DMMU |
| 111 | stxa %g0, [%g3] ASI_DMMU_DEMAP |
| 112 | stxa %g0, [%g3] ASI_IMMU_DEMAP |
| 113 | flush %g6 |
| 114 | stxa %g2, [%o1] ASI_DMMU |
David S. Miller | 4da808c | 2006-01-31 18:33:00 -0800 | [diff] [blame] | 115 | sethi %hi(KERNBASE), %o1 |
| 116 | flush %o1 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 117 | retl |
| 118 | wrpr %g1, 0, %pstate |
| 119 | |
| 120 | /* |
| 121 | * The following code flushes one page_size worth. |
| 122 | */ |
Prasanna S Panchamukhi | 8300516 | 2005-09-06 15:19:31 -0700 | [diff] [blame] | 123 | .section .kprobes.text, "ax" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 124 | .align 32 |
| 125 | .globl __flush_icache_page |
| 126 | __flush_icache_page: /* %o0 = phys_page */ |
| 127 | membar #StoreStore |
| 128 | srlx %o0, PAGE_SHIFT, %o0 |
| 129 | sethi %uhi(PAGE_OFFSET), %g1 |
| 130 | sllx %o0, PAGE_SHIFT, %o0 |
| 131 | sethi %hi(PAGE_SIZE), %g2 |
| 132 | sllx %g1, 32, %g1 |
| 133 | add %o0, %g1, %o0 |
| 134 | 1: subcc %g2, 32, %g2 |
| 135 | bne,pt %icc, 1b |
| 136 | flush %o0 + %g2 |
| 137 | retl |
| 138 | nop |
| 139 | |
| 140 | #ifdef DCACHE_ALIASING_POSSIBLE |
| 141 | |
| 142 | #if (PAGE_SHIFT != 13) |
| 143 | #error only page shift of 13 is supported by dcache flush |
| 144 | #endif |
| 145 | |
| 146 | #define DTAG_MASK 0x3 |
| 147 | |
David S. Miller | c5bd50a | 2005-09-26 16:06:03 -0700 | [diff] [blame] | 148 | /* This routine is Spitfire specific so the hardcoded |
| 149 | * D-cache size and line-size are OK. |
| 150 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 151 | .align 64 |
| 152 | .globl __flush_dcache_page |
| 153 | __flush_dcache_page: /* %o0=kaddr, %o1=flush_icache */ |
| 154 | sethi %uhi(PAGE_OFFSET), %g1 |
| 155 | sllx %g1, 32, %g1 |
David S. Miller | c5bd50a | 2005-09-26 16:06:03 -0700 | [diff] [blame] | 156 | sub %o0, %g1, %o0 ! physical address |
| 157 | srlx %o0, 11, %o0 ! make D-cache TAG |
| 158 | sethi %hi(1 << 14), %o2 ! D-cache size |
| 159 | sub %o2, (1 << 5), %o2 ! D-cache line size |
| 160 | 1: ldxa [%o2] ASI_DCACHE_TAG, %o3 ! load D-cache TAG |
| 161 | andcc %o3, DTAG_MASK, %g0 ! Valid? |
| 162 | be,pn %xcc, 2f ! Nope, branch |
| 163 | andn %o3, DTAG_MASK, %o3 ! Clear valid bits |
| 164 | cmp %o3, %o0 ! TAG match? |
| 165 | bne,pt %xcc, 2f ! Nope, branch |
| 166 | nop |
| 167 | stxa %g0, [%o2] ASI_DCACHE_TAG ! Invalidate TAG |
| 168 | membar #Sync |
| 169 | 2: brnz,pt %o2, 1b |
| 170 | sub %o2, (1 << 5), %o2 ! D-cache line size |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 171 | |
| 172 | /* The I-cache does not snoop local stores so we |
| 173 | * better flush that too when necessary. |
| 174 | */ |
| 175 | brnz,pt %o1, __flush_icache_page |
| 176 | sllx %o0, 11, %o0 |
| 177 | retl |
| 178 | nop |
| 179 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 180 | #endif /* DCACHE_ALIASING_POSSIBLE */ |
| 181 | |
David S. Miller | c5bd50a | 2005-09-26 16:06:03 -0700 | [diff] [blame] | 182 | .previous |
| 183 | |
David S. Miller | 2ef2777 | 2005-08-30 20:21:34 -0700 | [diff] [blame] | 184 | /* Cheetah specific versions, patched at boot time. */ |
David S. Miller | 4da808c | 2006-01-31 18:33:00 -0800 | [diff] [blame] | 185 | __cheetah_flush_tlb_mm: /* 19 insns */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 186 | rdpr %pstate, %g7 |
| 187 | andn %g7, PSTATE_IE, %g2 |
| 188 | wrpr %g2, 0x0, %pstate |
| 189 | wrpr %g0, 1, %tl |
| 190 | mov PRIMARY_CONTEXT, %o2 |
| 191 | mov 0x40, %g3 |
| 192 | ldxa [%o2] ASI_DMMU, %g2 |
David S. Miller | 2ef2777 | 2005-08-30 20:21:34 -0700 | [diff] [blame] | 193 | srlx %g2, CTX_PGSZ1_NUC_SHIFT, %o1 |
| 194 | sllx %o1, CTX_PGSZ1_NUC_SHIFT, %o1 |
| 195 | or %o0, %o1, %o0 /* Preserve nucleus page size fields */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 196 | stxa %o0, [%o2] ASI_DMMU |
| 197 | stxa %g0, [%g3] ASI_DMMU_DEMAP |
| 198 | stxa %g0, [%g3] ASI_IMMU_DEMAP |
| 199 | stxa %g2, [%o2] ASI_DMMU |
David S. Miller | 4da808c | 2006-01-31 18:33:00 -0800 | [diff] [blame] | 200 | sethi %hi(KERNBASE), %o2 |
| 201 | flush %o2 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 202 | wrpr %g0, 0, %tl |
| 203 | retl |
| 204 | wrpr %g7, 0x0, %pstate |
| 205 | |
David S. Miller | 4da808c | 2006-01-31 18:33:00 -0800 | [diff] [blame] | 206 | __cheetah_flush_tlb_pending: /* 27 insns */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 207 | /* %o0 = context, %o1 = nr, %o2 = vaddrs[] */ |
| 208 | rdpr %pstate, %g7 |
| 209 | sllx %o1, 3, %o1 |
| 210 | andn %g7, PSTATE_IE, %g2 |
| 211 | wrpr %g2, 0x0, %pstate |
| 212 | wrpr %g0, 1, %tl |
| 213 | mov PRIMARY_CONTEXT, %o4 |
| 214 | ldxa [%o4] ASI_DMMU, %g2 |
David S. Miller | 2ef2777 | 2005-08-30 20:21:34 -0700 | [diff] [blame] | 215 | srlx %g2, CTX_PGSZ1_NUC_SHIFT, %o3 |
| 216 | sllx %o3, CTX_PGSZ1_NUC_SHIFT, %o3 |
| 217 | or %o0, %o3, %o0 /* Preserve nucleus page size fields */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 218 | stxa %o0, [%o4] ASI_DMMU |
| 219 | 1: sub %o1, (1 << 3), %o1 |
| 220 | ldx [%o2 + %o1], %o3 |
| 221 | andcc %o3, 1, %g0 |
| 222 | be,pn %icc, 2f |
| 223 | andn %o3, 1, %o3 |
| 224 | stxa %g0, [%o3] ASI_IMMU_DEMAP |
| 225 | 2: stxa %g0, [%o3] ASI_DMMU_DEMAP |
David S. Miller | b445e26 | 2005-06-27 15:42:04 -0700 | [diff] [blame] | 226 | membar #Sync |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 227 | brnz,pt %o1, 1b |
David S. Miller | b445e26 | 2005-06-27 15:42:04 -0700 | [diff] [blame] | 228 | nop |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 229 | stxa %g2, [%o4] ASI_DMMU |
David S. Miller | 4da808c | 2006-01-31 18:33:00 -0800 | [diff] [blame] | 230 | sethi %hi(KERNBASE), %o4 |
| 231 | flush %o4 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 232 | wrpr %g0, 0, %tl |
| 233 | retl |
| 234 | wrpr %g7, 0x0, %pstate |
| 235 | |
| 236 | #ifdef DCACHE_ALIASING_POSSIBLE |
David S. Miller | c5bd50a | 2005-09-26 16:06:03 -0700 | [diff] [blame] | 237 | __cheetah_flush_dcache_page: /* 11 insns */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 238 | sethi %uhi(PAGE_OFFSET), %g1 |
| 239 | sllx %g1, 32, %g1 |
| 240 | sub %o0, %g1, %o0 |
| 241 | sethi %hi(PAGE_SIZE), %o4 |
| 242 | 1: subcc %o4, (1 << 5), %o4 |
| 243 | stxa %g0, [%o0 + %o4] ASI_DCACHE_INVALIDATE |
| 244 | membar #Sync |
| 245 | bne,pt %icc, 1b |
| 246 | nop |
| 247 | retl /* I-cache flush never needed on Cheetah, see callers. */ |
| 248 | nop |
| 249 | #endif /* DCACHE_ALIASING_POSSIBLE */ |
| 250 | |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 251 | /* Hypervisor specific versions, patched at boot time. */ |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 252 | __hypervisor_tlb_tl0_error: |
| 253 | save %sp, -192, %sp |
| 254 | mov %i0, %o0 |
| 255 | call hypervisor_tlbop_error |
| 256 | mov %i1, %o1 |
| 257 | ret |
| 258 | restore |
| 259 | |
| 260 | __hypervisor_flush_tlb_mm: /* 10 insns */ |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 261 | mov %o0, %o2 /* ARG2: mmu context */ |
| 262 | mov 0, %o0 /* ARG0: CPU lists unimplemented */ |
| 263 | mov 0, %o1 /* ARG1: CPU lists unimplemented */ |
| 264 | mov HV_MMU_ALL, %o3 /* ARG3: flags */ |
| 265 | mov HV_FAST_MMU_DEMAP_CTX, %o5 |
| 266 | ta HV_FAST_TRAP |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 267 | brnz,pn %o0, __hypervisor_tlb_tl0_error |
| 268 | mov HV_FAST_MMU_DEMAP_CTX, %o1 |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 269 | retl |
| 270 | nop |
| 271 | |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 272 | __hypervisor_flush_tlb_pending: /* 16 insns */ |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 273 | /* %o0 = context, %o1 = nr, %o2 = vaddrs[] */ |
| 274 | sllx %o1, 3, %g1 |
| 275 | mov %o2, %g2 |
| 276 | mov %o0, %g3 |
| 277 | 1: sub %g1, (1 << 3), %g1 |
| 278 | ldx [%g2 + %g1], %o0 /* ARG0: vaddr + IMMU-bit */ |
| 279 | mov %g3, %o1 /* ARG1: mmu context */ |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 280 | mov HV_MMU_ALL, %o2 /* ARG2: flags */ |
| 281 | srlx %o0, PAGE_SHIFT, %o0 |
| 282 | sllx %o0, PAGE_SHIFT, %o0 |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 283 | ta HV_MMU_UNMAP_ADDR_TRAP |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 284 | brnz,pn %o0, __hypervisor_tlb_tl0_error |
| 285 | mov HV_MMU_UNMAP_ADDR_TRAP, %o1 |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 286 | brnz,pt %g1, 1b |
| 287 | nop |
| 288 | retl |
| 289 | nop |
| 290 | |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 291 | __hypervisor_flush_tlb_kernel_range: /* 16 insns */ |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 292 | /* %o0=start, %o1=end */ |
| 293 | cmp %o0, %o1 |
| 294 | be,pn %xcc, 2f |
| 295 | sethi %hi(PAGE_SIZE), %g3 |
| 296 | mov %o0, %g1 |
| 297 | sub %o1, %g1, %g2 |
| 298 | sub %g2, %g3, %g2 |
| 299 | 1: add %g1, %g2, %o0 /* ARG0: virtual address */ |
| 300 | mov 0, %o1 /* ARG1: mmu context */ |
| 301 | mov HV_MMU_ALL, %o2 /* ARG2: flags */ |
| 302 | ta HV_MMU_UNMAP_ADDR_TRAP |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 303 | brnz,pn %o0, __hypervisor_tlb_tl0_error |
| 304 | mov HV_MMU_UNMAP_ADDR_TRAP, %o1 |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 305 | brnz,pt %g2, 1b |
| 306 | sub %g2, %g3, %g2 |
| 307 | 2: retl |
| 308 | nop |
| 309 | |
| 310 | #ifdef DCACHE_ALIASING_POSSIBLE |
| 311 | /* XXX Niagara and friends have an 8K cache, so no aliasing is |
| 312 | * XXX possible, but nothing explicit in the Hypervisor API |
| 313 | * XXX guarantees this. |
| 314 | */ |
| 315 | __hypervisor_flush_dcache_page: /* 2 insns */ |
| 316 | retl |
| 317 | nop |
| 318 | #endif |
| 319 | |
| 320 | tlb_patch_one: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 321 | 1: lduw [%o1], %g1 |
| 322 | stw %g1, [%o0] |
| 323 | flush %o0 |
| 324 | subcc %o2, 1, %o2 |
| 325 | add %o1, 4, %o1 |
| 326 | bne,pt %icc, 1b |
| 327 | add %o0, 4, %o0 |
| 328 | retl |
| 329 | nop |
| 330 | |
| 331 | .globl cheetah_patch_cachetlbops |
| 332 | cheetah_patch_cachetlbops: |
| 333 | save %sp, -128, %sp |
| 334 | |
| 335 | sethi %hi(__flush_tlb_mm), %o0 |
| 336 | or %o0, %lo(__flush_tlb_mm), %o0 |
| 337 | sethi %hi(__cheetah_flush_tlb_mm), %o1 |
| 338 | or %o1, %lo(__cheetah_flush_tlb_mm), %o1 |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 339 | call tlb_patch_one |
David S. Miller | 4da808c | 2006-01-31 18:33:00 -0800 | [diff] [blame] | 340 | mov 19, %o2 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 341 | |
| 342 | sethi %hi(__flush_tlb_pending), %o0 |
| 343 | or %o0, %lo(__flush_tlb_pending), %o0 |
| 344 | sethi %hi(__cheetah_flush_tlb_pending), %o1 |
| 345 | or %o1, %lo(__cheetah_flush_tlb_pending), %o1 |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 346 | call tlb_patch_one |
David S. Miller | 4da808c | 2006-01-31 18:33:00 -0800 | [diff] [blame] | 347 | mov 27, %o2 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 348 | |
| 349 | #ifdef DCACHE_ALIASING_POSSIBLE |
| 350 | sethi %hi(__flush_dcache_page), %o0 |
| 351 | or %o0, %lo(__flush_dcache_page), %o0 |
David S. Miller | c5bd50a | 2005-09-26 16:06:03 -0700 | [diff] [blame] | 352 | sethi %hi(__cheetah_flush_dcache_page), %o1 |
| 353 | or %o1, %lo(__cheetah_flush_dcache_page), %o1 |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 354 | call tlb_patch_one |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 355 | mov 11, %o2 |
| 356 | #endif /* DCACHE_ALIASING_POSSIBLE */ |
| 357 | |
| 358 | ret |
| 359 | restore |
| 360 | |
| 361 | #ifdef CONFIG_SMP |
| 362 | /* These are all called by the slaves of a cross call, at |
| 363 | * trap level 1, with interrupts fully disabled. |
| 364 | * |
| 365 | * Register usage: |
| 366 | * %g5 mm->context (all tlb flushes) |
| 367 | * %g1 address arg 1 (tlb page and range flushes) |
| 368 | * %g7 address arg 2 (tlb range flush only) |
| 369 | * |
David S. Miller | 56fb4df | 2006-02-26 23:24:22 -0800 | [diff] [blame] | 370 | * %g6 scratch 1 |
| 371 | * %g2 scratch 2 |
| 372 | * %g3 scratch 3 |
| 373 | * %g4 scratch 4 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 374 | */ |
| 375 | .align 32 |
| 376 | .globl xcall_flush_tlb_mm |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 377 | xcall_flush_tlb_mm: /* 21 insns */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 378 | mov PRIMARY_CONTEXT, %g2 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 379 | ldxa [%g2] ASI_DMMU, %g3 |
David S. Miller | 2ef2777 | 2005-08-30 20:21:34 -0700 | [diff] [blame] | 380 | srlx %g3, CTX_PGSZ1_NUC_SHIFT, %g4 |
| 381 | sllx %g4, CTX_PGSZ1_NUC_SHIFT, %g4 |
| 382 | or %g5, %g4, %g5 /* Preserve nucleus page size fields */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 383 | stxa %g5, [%g2] ASI_DMMU |
David S. Miller | 2ef2777 | 2005-08-30 20:21:34 -0700 | [diff] [blame] | 384 | mov 0x40, %g4 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 385 | stxa %g0, [%g4] ASI_DMMU_DEMAP |
| 386 | stxa %g0, [%g4] ASI_IMMU_DEMAP |
| 387 | stxa %g3, [%g2] ASI_DMMU |
| 388 | retry |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 389 | nop |
| 390 | nop |
| 391 | nop |
| 392 | nop |
| 393 | nop |
| 394 | nop |
| 395 | nop |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 396 | nop |
| 397 | nop |
| 398 | nop |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 399 | |
| 400 | .globl xcall_flush_tlb_pending |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 401 | xcall_flush_tlb_pending: /* 21 insns */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 402 | /* %g5=context, %g1=nr, %g7=vaddrs[] */ |
| 403 | sllx %g1, 3, %g1 |
| 404 | mov PRIMARY_CONTEXT, %g4 |
| 405 | ldxa [%g4] ASI_DMMU, %g2 |
David S. Miller | 2ef2777 | 2005-08-30 20:21:34 -0700 | [diff] [blame] | 406 | srlx %g2, CTX_PGSZ1_NUC_SHIFT, %g4 |
| 407 | sllx %g4, CTX_PGSZ1_NUC_SHIFT, %g4 |
| 408 | or %g5, %g4, %g5 |
| 409 | mov PRIMARY_CONTEXT, %g4 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 410 | stxa %g5, [%g4] ASI_DMMU |
| 411 | 1: sub %g1, (1 << 3), %g1 |
| 412 | ldx [%g7 + %g1], %g5 |
| 413 | andcc %g5, 0x1, %g0 |
| 414 | be,pn %icc, 2f |
| 415 | |
| 416 | andn %g5, 0x1, %g5 |
| 417 | stxa %g0, [%g5] ASI_IMMU_DEMAP |
| 418 | 2: stxa %g0, [%g5] ASI_DMMU_DEMAP |
| 419 | membar #Sync |
| 420 | brnz,pt %g1, 1b |
| 421 | nop |
| 422 | stxa %g2, [%g4] ASI_DMMU |
| 423 | retry |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 424 | nop |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 425 | |
| 426 | .globl xcall_flush_tlb_kernel_range |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 427 | xcall_flush_tlb_kernel_range: /* 25 insns */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 428 | sethi %hi(PAGE_SIZE - 1), %g2 |
| 429 | or %g2, %lo(PAGE_SIZE - 1), %g2 |
| 430 | andn %g1, %g2, %g1 |
| 431 | andn %g7, %g2, %g7 |
| 432 | sub %g7, %g1, %g3 |
| 433 | add %g2, 1, %g2 |
| 434 | sub %g3, %g2, %g3 |
| 435 | or %g1, 0x20, %g1 ! Nucleus |
| 436 | 1: stxa %g0, [%g1 + %g3] ASI_DMMU_DEMAP |
| 437 | stxa %g0, [%g1 + %g3] ASI_IMMU_DEMAP |
| 438 | membar #Sync |
| 439 | brnz,pt %g3, 1b |
| 440 | sub %g3, %g2, %g3 |
| 441 | retry |
| 442 | nop |
| 443 | nop |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 444 | nop |
| 445 | nop |
| 446 | nop |
| 447 | nop |
| 448 | nop |
| 449 | nop |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 450 | nop |
| 451 | nop |
| 452 | nop |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 453 | |
| 454 | /* This runs in a very controlled environment, so we do |
| 455 | * not need to worry about BH races etc. |
| 456 | */ |
| 457 | .globl xcall_sync_tick |
| 458 | xcall_sync_tick: |
David S. Miller | 45fec05 | 2006-02-05 22:27:28 -0800 | [diff] [blame] | 459 | |
| 460 | 661: rdpr %pstate, %g2 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 461 | wrpr %g2, PSTATE_IG | PSTATE_AG, %pstate |
David S. Miller | df7d6ae | 2006-02-07 00:00:16 -0800 | [diff] [blame] | 462 | .section .sun4v_2insn_patch, "ax" |
David S. Miller | 45fec05 | 2006-02-05 22:27:28 -0800 | [diff] [blame] | 463 | .word 661b |
| 464 | nop |
| 465 | nop |
| 466 | .previous |
| 467 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 468 | rdpr %pil, %g2 |
| 469 | wrpr %g0, 15, %pil |
| 470 | sethi %hi(109f), %g7 |
| 471 | b,pt %xcc, etrap_irq |
| 472 | 109: or %g7, %lo(109b), %g7 |
David S. Miller | 10e2672 | 2006-11-16 13:38:57 -0800 | [diff] [blame] | 473 | #ifdef CONFIG_TRACE_IRQFLAGS |
| 474 | call trace_hardirqs_off |
| 475 | nop |
| 476 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 477 | call smp_synchronize_tick_client |
| 478 | nop |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 479 | b rtrap_xcall |
| 480 | ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1 |
| 481 | |
| 482 | /* NOTE: This is SPECIAL!! We do etrap/rtrap however |
| 483 | * we choose to deal with the "BH's run with |
| 484 | * %pil==15" problem (described in asm/pil.h) |
| 485 | * by just invoking rtrap directly past where |
| 486 | * BH's are checked for. |
| 487 | * |
| 488 | * We do it like this because we do not want %pil==15 |
| 489 | * lockups to prevent regs being reported. |
| 490 | */ |
| 491 | .globl xcall_report_regs |
| 492 | xcall_report_regs: |
David S. Miller | 45fec05 | 2006-02-05 22:27:28 -0800 | [diff] [blame] | 493 | |
| 494 | 661: rdpr %pstate, %g2 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 495 | wrpr %g2, PSTATE_IG | PSTATE_AG, %pstate |
David S. Miller | df7d6ae | 2006-02-07 00:00:16 -0800 | [diff] [blame] | 496 | .section .sun4v_2insn_patch, "ax" |
David S. Miller | 45fec05 | 2006-02-05 22:27:28 -0800 | [diff] [blame] | 497 | .word 661b |
| 498 | nop |
| 499 | nop |
| 500 | .previous |
| 501 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 502 | rdpr %pil, %g2 |
| 503 | wrpr %g0, 15, %pil |
| 504 | sethi %hi(109f), %g7 |
| 505 | b,pt %xcc, etrap_irq |
| 506 | 109: or %g7, %lo(109b), %g7 |
David S. Miller | 10e2672 | 2006-11-16 13:38:57 -0800 | [diff] [blame] | 507 | #ifdef CONFIG_TRACE_IRQFLAGS |
| 508 | call trace_hardirqs_off |
| 509 | nop |
| 510 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 511 | call __show_regs |
| 512 | add %sp, PTREGS_OFF, %o0 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 513 | /* Has to be a non-v9 branch due to the large distance. */ |
| 514 | b rtrap_xcall |
| 515 | ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1 |
| 516 | |
| 517 | #ifdef DCACHE_ALIASING_POSSIBLE |
| 518 | .align 32 |
| 519 | .globl xcall_flush_dcache_page_cheetah |
| 520 | xcall_flush_dcache_page_cheetah: /* %g1 == physical page address */ |
| 521 | sethi %hi(PAGE_SIZE), %g3 |
| 522 | 1: subcc %g3, (1 << 5), %g3 |
| 523 | stxa %g0, [%g1 + %g3] ASI_DCACHE_INVALIDATE |
| 524 | membar #Sync |
| 525 | bne,pt %icc, 1b |
| 526 | nop |
| 527 | retry |
| 528 | nop |
| 529 | #endif /* DCACHE_ALIASING_POSSIBLE */ |
| 530 | |
| 531 | .globl xcall_flush_dcache_page_spitfire |
| 532 | xcall_flush_dcache_page_spitfire: /* %g1 == physical page address |
| 533 | %g7 == kernel page virtual address |
| 534 | %g5 == (page->mapping != NULL) */ |
| 535 | #ifdef DCACHE_ALIASING_POSSIBLE |
| 536 | srlx %g1, (13 - 2), %g1 ! Form tag comparitor |
| 537 | sethi %hi(L1DCACHE_SIZE), %g3 ! D$ size == 16K |
| 538 | sub %g3, (1 << 5), %g3 ! D$ linesize == 32 |
| 539 | 1: ldxa [%g3] ASI_DCACHE_TAG, %g2 |
| 540 | andcc %g2, 0x3, %g0 |
| 541 | be,pn %xcc, 2f |
| 542 | andn %g2, 0x3, %g2 |
| 543 | cmp %g2, %g1 |
| 544 | |
| 545 | bne,pt %xcc, 2f |
| 546 | nop |
| 547 | stxa %g0, [%g3] ASI_DCACHE_TAG |
| 548 | membar #Sync |
| 549 | 2: cmp %g3, 0 |
| 550 | bne,pt %xcc, 1b |
| 551 | sub %g3, (1 << 5), %g3 |
| 552 | |
| 553 | brz,pn %g5, 2f |
| 554 | #endif /* DCACHE_ALIASING_POSSIBLE */ |
| 555 | sethi %hi(PAGE_SIZE), %g3 |
| 556 | |
| 557 | 1: flush %g7 |
| 558 | subcc %g3, (1 << 5), %g3 |
| 559 | bne,pt %icc, 1b |
| 560 | add %g7, (1 << 5), %g7 |
| 561 | |
| 562 | 2: retry |
| 563 | nop |
| 564 | nop |
| 565 | |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 566 | /* %g5: error |
| 567 | * %g6: tlb op |
| 568 | */ |
| 569 | __hypervisor_tlb_xcall_error: |
| 570 | mov %g5, %g4 |
| 571 | mov %g6, %g5 |
| 572 | ba,pt %xcc, etrap |
| 573 | rd %pc, %g7 |
| 574 | mov %l4, %o0 |
| 575 | call hypervisor_tlbop_error_xcall |
| 576 | mov %l5, %o1 |
David S. Miller | 7697daa | 2008-04-24 03:15:22 -0700 | [diff] [blame^] | 577 | ba,a,pt %xcc, rtrap |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 578 | |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 579 | .globl __hypervisor_xcall_flush_tlb_mm |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 580 | __hypervisor_xcall_flush_tlb_mm: /* 21 insns */ |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 581 | /* %g5=ctx, g1,g2,g3,g4,g7=scratch, %g6=unusable */ |
| 582 | mov %o0, %g2 |
| 583 | mov %o1, %g3 |
| 584 | mov %o2, %g4 |
| 585 | mov %o3, %g1 |
| 586 | mov %o5, %g7 |
| 587 | clr %o0 /* ARG0: CPU lists unimplemented */ |
| 588 | clr %o1 /* ARG1: CPU lists unimplemented */ |
| 589 | mov %g5, %o2 /* ARG2: mmu context */ |
| 590 | mov HV_MMU_ALL, %o3 /* ARG3: flags */ |
| 591 | mov HV_FAST_MMU_DEMAP_CTX, %o5 |
| 592 | ta HV_FAST_TRAP |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 593 | mov HV_FAST_MMU_DEMAP_CTX, %g6 |
| 594 | brnz,pn %o0, __hypervisor_tlb_xcall_error |
| 595 | mov %o0, %g5 |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 596 | mov %g2, %o0 |
| 597 | mov %g3, %o1 |
| 598 | mov %g4, %o2 |
| 599 | mov %g1, %o3 |
| 600 | mov %g7, %o5 |
| 601 | membar #Sync |
| 602 | retry |
| 603 | |
| 604 | .globl __hypervisor_xcall_flush_tlb_pending |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 605 | __hypervisor_xcall_flush_tlb_pending: /* 21 insns */ |
| 606 | /* %g5=ctx, %g1=nr, %g7=vaddrs[], %g2,%g3,%g4,g6=scratch */ |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 607 | sllx %g1, 3, %g1 |
| 608 | mov %o0, %g2 |
| 609 | mov %o1, %g3 |
| 610 | mov %o2, %g4 |
| 611 | 1: sub %g1, (1 << 3), %g1 |
| 612 | ldx [%g7 + %g1], %o0 /* ARG0: virtual address */ |
| 613 | mov %g5, %o1 /* ARG1: mmu context */ |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 614 | mov HV_MMU_ALL, %o2 /* ARG2: flags */ |
| 615 | srlx %o0, PAGE_SHIFT, %o0 |
| 616 | sllx %o0, PAGE_SHIFT, %o0 |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 617 | ta HV_MMU_UNMAP_ADDR_TRAP |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 618 | mov HV_MMU_UNMAP_ADDR_TRAP, %g6 |
| 619 | brnz,a,pn %o0, __hypervisor_tlb_xcall_error |
| 620 | mov %o0, %g5 |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 621 | brnz,pt %g1, 1b |
| 622 | nop |
| 623 | mov %g2, %o0 |
| 624 | mov %g3, %o1 |
| 625 | mov %g4, %o2 |
| 626 | membar #Sync |
| 627 | retry |
| 628 | |
| 629 | .globl __hypervisor_xcall_flush_tlb_kernel_range |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 630 | __hypervisor_xcall_flush_tlb_kernel_range: /* 25 insns */ |
| 631 | /* %g1=start, %g7=end, g2,g3,g4,g5,g6=scratch */ |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 632 | sethi %hi(PAGE_SIZE - 1), %g2 |
| 633 | or %g2, %lo(PAGE_SIZE - 1), %g2 |
| 634 | andn %g1, %g2, %g1 |
| 635 | andn %g7, %g2, %g7 |
| 636 | sub %g7, %g1, %g3 |
| 637 | add %g2, 1, %g2 |
| 638 | sub %g3, %g2, %g3 |
| 639 | mov %o0, %g2 |
| 640 | mov %o1, %g4 |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 641 | mov %o2, %g7 |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 642 | 1: add %g1, %g3, %o0 /* ARG0: virtual address */ |
| 643 | mov 0, %o1 /* ARG1: mmu context */ |
| 644 | mov HV_MMU_ALL, %o2 /* ARG2: flags */ |
| 645 | ta HV_MMU_UNMAP_ADDR_TRAP |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 646 | mov HV_MMU_UNMAP_ADDR_TRAP, %g6 |
| 647 | brnz,pn %o0, __hypervisor_tlb_xcall_error |
| 648 | mov %o0, %g5 |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 649 | sethi %hi(PAGE_SIZE), %o2 |
| 650 | brnz,pt %g3, 1b |
| 651 | sub %g3, %o2, %g3 |
| 652 | mov %g2, %o0 |
| 653 | mov %g4, %o1 |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 654 | mov %g7, %o2 |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 655 | membar #Sync |
| 656 | retry |
| 657 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 658 | /* These just get rescheduled to PIL vectors. */ |
| 659 | .globl xcall_call_function |
| 660 | xcall_call_function: |
| 661 | wr %g0, (1 << PIL_SMP_CALL_FUNC), %set_softint |
| 662 | retry |
| 663 | |
| 664 | .globl xcall_receive_signal |
| 665 | xcall_receive_signal: |
| 666 | wr %g0, (1 << PIL_SMP_RECEIVE_SIGNAL), %set_softint |
| 667 | retry |
| 668 | |
| 669 | .globl xcall_capture |
| 670 | xcall_capture: |
| 671 | wr %g0, (1 << PIL_SMP_CAPTURE), %set_softint |
| 672 | retry |
| 673 | |
David S. Miller | ee29074 | 2006-03-06 22:50:44 -0800 | [diff] [blame] | 674 | .globl xcall_new_mmu_context_version |
| 675 | xcall_new_mmu_context_version: |
| 676 | wr %g0, (1 << PIL_SMP_CTX_NEW_VERSION), %set_softint |
| 677 | retry |
| 678 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 679 | #endif /* CONFIG_SMP */ |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 680 | |
| 681 | |
| 682 | .globl hypervisor_patch_cachetlbops |
| 683 | hypervisor_patch_cachetlbops: |
| 684 | save %sp, -128, %sp |
| 685 | |
| 686 | sethi %hi(__flush_tlb_mm), %o0 |
| 687 | or %o0, %lo(__flush_tlb_mm), %o0 |
| 688 | sethi %hi(__hypervisor_flush_tlb_mm), %o1 |
| 689 | or %o1, %lo(__hypervisor_flush_tlb_mm), %o1 |
| 690 | call tlb_patch_one |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 691 | mov 10, %o2 |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 692 | |
| 693 | sethi %hi(__flush_tlb_pending), %o0 |
| 694 | or %o0, %lo(__flush_tlb_pending), %o0 |
| 695 | sethi %hi(__hypervisor_flush_tlb_pending), %o1 |
| 696 | or %o1, %lo(__hypervisor_flush_tlb_pending), %o1 |
| 697 | call tlb_patch_one |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 698 | mov 16, %o2 |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 699 | |
| 700 | sethi %hi(__flush_tlb_kernel_range), %o0 |
| 701 | or %o0, %lo(__flush_tlb_kernel_range), %o0 |
| 702 | sethi %hi(__hypervisor_flush_tlb_kernel_range), %o1 |
| 703 | or %o1, %lo(__hypervisor_flush_tlb_kernel_range), %o1 |
| 704 | call tlb_patch_one |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 705 | mov 16, %o2 |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 706 | |
| 707 | #ifdef DCACHE_ALIASING_POSSIBLE |
| 708 | sethi %hi(__flush_dcache_page), %o0 |
| 709 | or %o0, %lo(__flush_dcache_page), %o0 |
| 710 | sethi %hi(__hypervisor_flush_dcache_page), %o1 |
| 711 | or %o1, %lo(__hypervisor_flush_dcache_page), %o1 |
| 712 | call tlb_patch_one |
| 713 | mov 2, %o2 |
| 714 | #endif /* DCACHE_ALIASING_POSSIBLE */ |
| 715 | |
| 716 | #ifdef CONFIG_SMP |
| 717 | sethi %hi(xcall_flush_tlb_mm), %o0 |
| 718 | or %o0, %lo(xcall_flush_tlb_mm), %o0 |
| 719 | sethi %hi(__hypervisor_xcall_flush_tlb_mm), %o1 |
| 720 | or %o1, %lo(__hypervisor_xcall_flush_tlb_mm), %o1 |
| 721 | call tlb_patch_one |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 722 | mov 21, %o2 |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 723 | |
| 724 | sethi %hi(xcall_flush_tlb_pending), %o0 |
| 725 | or %o0, %lo(xcall_flush_tlb_pending), %o0 |
| 726 | sethi %hi(__hypervisor_xcall_flush_tlb_pending), %o1 |
| 727 | or %o1, %lo(__hypervisor_xcall_flush_tlb_pending), %o1 |
| 728 | call tlb_patch_one |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 729 | mov 21, %o2 |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 730 | |
| 731 | sethi %hi(xcall_flush_tlb_kernel_range), %o0 |
| 732 | or %o0, %lo(xcall_flush_tlb_kernel_range), %o0 |
| 733 | sethi %hi(__hypervisor_xcall_flush_tlb_kernel_range), %o1 |
| 734 | or %o1, %lo(__hypervisor_xcall_flush_tlb_kernel_range), %o1 |
| 735 | call tlb_patch_one |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 736 | mov 25, %o2 |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 737 | #endif /* CONFIG_SMP */ |
| 738 | |
| 739 | ret |
| 740 | restore |