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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/arch/arm/mach-pxa/pxa25x.c
3 *
4 * Author: Nicolas Pitre
5 * Created: Jun 15, 2001
6 * Copyright: MontaVista Software Inc.
7 *
8 * Code specific to PXA21x/25x/26x variants.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * Since this file should be linked before any other machine specific file,
15 * the __initcall() here will be executed first. This serves as default
16 * initialization stuff for PXA machines which can be overridden later if
17 * need be.
18 */
19#include <linux/module.h>
20#include <linux/kernel.h>
21#include <linux/init.h>
Russell King34f32312007-05-15 10:39:49 +010022#include <linux/platform_device.h>
Rafael J. Wysocki95d9ffb2007-10-18 03:04:39 -070023#include <linux/suspend.h>
eric miaoc01655042008-01-28 23:00:02 +000024#include <linux/sysdev.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070025
26#include <asm/hardware.h>
Eric Miaocd491042007-06-22 04:14:09 +010027#include <asm/arch/irqs.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070028#include <asm/arch/pxa-regs.h>
Russell King0b0a9df2008-05-18 14:59:36 +010029#include <asm/arch/pxa2xx-regs.h>
eric miaoc0a596d2008-03-11 09:46:28 +080030#include <asm/arch/mfp-pxa25x.h>
Russell Kinge176bb02007-05-15 11:16:10 +010031#include <asm/arch/pm.h>
Eric Miaof53f0662007-06-22 05:40:17 +010032#include <asm/arch/dma.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070033
34#include "generic.h"
Russell King46c41e62007-05-15 15:39:36 +010035#include "devices.h"
Russell Kinga6dba202007-08-20 10:18:02 +010036#include "clock.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070037
38/*
39 * Various clock factors driven by the CCCR register.
40 */
41
42/* Crystal Frequency to Memory Frequency Multiplier (L) */
43static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };
44
45/* Memory Frequency to Run Mode Frequency Multiplier (M) */
46static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };
47
48/* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
49/* Note: we store the value N * 2 here. */
50static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };
51
52/* Crystal clock */
53#define BASE_CLK 3686400
54
55/*
56 * Get the clock frequency as reflected by CCCR and the turbo flag.
57 * We assume these values have been applied via a fcs.
58 * If info is not 0 we also display the current settings.
59 */
Russell King15a40332007-08-20 10:07:44 +010060unsigned int pxa25x_get_clk_frequency_khz(int info)
Linus Torvalds1da177e2005-04-16 15:20:36 -070061{
62 unsigned long cccr, turbo;
63 unsigned int l, L, m, M, n2, N;
64
65 cccr = CCCR;
66 asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) );
67
68 l = L_clk_mult[(cccr >> 0) & 0x1f];
69 m = M_clk_mult[(cccr >> 5) & 0x03];
70 n2 = N2_clk_mult[(cccr >> 7) & 0x07];
71
72 L = l * BASE_CLK;
73 M = m * L;
74 N = n2 * M / 2;
75
76 if(info)
77 {
78 L += 5000;
79 printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n",
80 L / 1000000, (L % 1000000) / 10000, l );
81 M += 5000;
82 printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
83 M / 1000000, (M % 1000000) / 10000, m );
84 N += 5000;
85 printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
86 N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5,
87 (turbo & 1) ? "" : "in" );
88 }
89
90 return (turbo & 1) ? (N/1000) : (M/1000);
91}
92
Linus Torvalds1da177e2005-04-16 15:20:36 -070093/*
94 * Return the current memory clock frequency in units of 10kHz
95 */
Russell King15a40332007-08-20 10:07:44 +010096unsigned int pxa25x_get_memclk_frequency_10khz(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -070097{
98 return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000;
99}
100
Russell Kinga6dba202007-08-20 10:18:02 +0100101static unsigned long clk_pxa25x_lcd_getrate(struct clk *clk)
102{
103 return pxa25x_get_memclk_frequency_10khz() * 10000;
104}
105
106static const struct clkops clk_pxa25x_lcd_ops = {
107 .enable = clk_cken_enable,
108 .disable = clk_cken_disable,
109 .getrate = clk_pxa25x_lcd_getrate,
110};
111
112/*
113 * 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz)
114 * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz
115 * 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly)
116 */
Dmitry Baryshkove01dbdb2008-01-27 23:11:48 +0100117static struct clk pxa25x_hwuart_clk =
118 INIT_CKEN("UARTCLK", HWUART, 14745600, 1, &pxa_device_hwuart.dev)
119;
120
Russell Kingbdb08cb2008-06-30 19:47:59 +0100121/*
122 * PXA 2xx clock declarations. Order is important (see aliases below)
123 * Please be careful not to disrupt the ordering.
124 */
Russell Kinga6dba202007-08-20 10:18:02 +0100125static struct clk pxa25x_clks[] = {
126 INIT_CK("LCDCLK", LCD, &clk_pxa25x_lcd_ops, &pxa_device_fb.dev),
127 INIT_CKEN("UARTCLK", FFUART, 14745600, 1, &pxa_device_ffuart.dev),
128 INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev),
Russell King435b6e92007-09-02 17:08:42 +0100129 INIT_CKEN("UARTCLK", STUART, 14745600, 1, NULL),
Philipp Zabel7a857622008-06-22 23:36:39 +0100130 INIT_CKEN("UDCCLK", USB, 47923000, 5, &pxa25x_device_udc.dev),
Russell Kinga6dba202007-08-20 10:18:02 +0100131 INIT_CKEN("MMCCLK", MMC, 19169000, 0, &pxa_device_mci.dev),
132 INIT_CKEN("I2CCLK", I2C, 31949000, 0, &pxa_device_i2c.dev),
eric miaod8e0db12007-12-10 17:54:36 +0800133
134 INIT_CKEN("SSPCLK", SSP, 3686400, 0, &pxa25x_device_ssp.dev),
135 INIT_CKEN("SSPCLK", NSSP, 3686400, 0, &pxa25x_device_nssp.dev),
136 INIT_CKEN("SSPCLK", ASSP, 3686400, 0, &pxa25x_device_assp.dev),
eric miao75540c12008-04-13 21:44:04 +0100137 INIT_CKEN("PWMCLK", PWM0, 3686400, 0, &pxa25x_device_pwm0.dev),
138 INIT_CKEN("PWMCLK", PWM1, 3686400, 0, &pxa25x_device_pwm1.dev),
eric miaod8e0db12007-12-10 17:54:36 +0800139
Mark Brown27b98a62008-03-04 11:14:22 +0100140 INIT_CKEN("AC97CLK", AC97, 24576000, 0, NULL),
141
Russell Kinga6dba202007-08-20 10:18:02 +0100142 /*
Russell Kinga6dba202007-08-20 10:18:02 +0100143 INIT_CKEN("I2SCLK", I2S, 14745600, 0, NULL),
Russell Kinga6dba202007-08-20 10:18:02 +0100144 */
Russell King435b6e92007-09-02 17:08:42 +0100145 INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL),
Russell Kinga6dba202007-08-20 10:18:02 +0100146};
147
Russell Kingbdb08cb2008-06-30 19:47:59 +0100148static struct clk gpio7_clk = INIT_CKOTHER("GPIO7_CK", &pxa25x_clks[4], NULL);
149
Nicolas Pitrea8fa3f02005-06-13 22:35:41 +0100150#ifdef CONFIG_PM
Todd Poynor87754202005-06-03 20:52:27 +0100151
Eric Miao711be5c2007-07-18 11:38:45 +0100152#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
153#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
154
Eric Miao711be5c2007-07-18 11:38:45 +0100155/*
156 * List of global PXA peripheral registers to preserve.
157 * More ones like CP and general purpose register values are preserved
158 * with the stack pointer in sleep.S.
159 */
Robert Jarzmik649de512008-05-02 21:17:06 +0100160enum { SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2,
Eric Miao711be5c2007-07-18 11:38:45 +0100161
162 SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
163 SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U,
164 SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U,
165
166 SLEEP_SAVE_PSTR,
167
Eric Miao711be5c2007-07-18 11:38:45 +0100168 SLEEP_SAVE_CKEN,
169
Robert Jarzmik649de512008-05-02 21:17:06 +0100170 SLEEP_SAVE_COUNT
Eric Miao711be5c2007-07-18 11:38:45 +0100171};
172
173
174static void pxa25x_cpu_pm_save(unsigned long *sleep_save)
175{
Eric Miao711be5c2007-07-18 11:38:45 +0100176 SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2);
177
178 SAVE(GAFR0_L); SAVE(GAFR0_U);
179 SAVE(GAFR1_L); SAVE(GAFR1_U);
180 SAVE(GAFR2_L); SAVE(GAFR2_U);
181
Eric Miao711be5c2007-07-18 11:38:45 +0100182 SAVE(CKEN);
183 SAVE(PSTR);
Richard Purdie56b11282008-01-02 00:54:49 +0100184
185 /* Clear GPIO transition detect bits */
186 GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2;
Eric Miao711be5c2007-07-18 11:38:45 +0100187}
188
189static void pxa25x_cpu_pm_restore(unsigned long *sleep_save)
190{
Richard Purdie56b11282008-01-02 00:54:49 +0100191 /* ensure not to come back here if it wasn't intended */
192 PSPR = 0;
193
Eric Miao711be5c2007-07-18 11:38:45 +0100194 /* restore registers */
Eric Miao711be5c2007-07-18 11:38:45 +0100195 RESTORE(GAFR0_L); RESTORE(GAFR0_U);
196 RESTORE(GAFR1_L); RESTORE(GAFR1_U);
197 RESTORE(GAFR2_L); RESTORE(GAFR2_U);
Eric Miao711be5c2007-07-18 11:38:45 +0100198 RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2);
199
Richard Purdie56b11282008-01-02 00:54:49 +0100200 PSSR = PSSR_RDH | PSSR_PH;
201
Eric Miao711be5c2007-07-18 11:38:45 +0100202 RESTORE(CKEN);
Eric Miao711be5c2007-07-18 11:38:45 +0100203 RESTORE(PSTR);
204}
205
206static void pxa25x_cpu_pm_enter(suspend_state_t state)
Todd Poynor87754202005-06-03 20:52:27 +0100207{
Russell Kingdc38e2a2008-05-08 16:50:39 +0100208 /* Clear reset status */
209 RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
210
Todd Poynor87754202005-06-03 20:52:27 +0100211 switch (state) {
212 case PM_SUSPEND_MEM:
213 /* set resume return address */
214 PSPR = virt_to_phys(pxa_cpu_resume);
Eric Miaob750a092007-07-18 11:40:13 +0100215 pxa25x_cpu_suspend(PWRMODE_SLEEP);
Todd Poynor87754202005-06-03 20:52:27 +0100216 break;
217 }
218}
Nicolas Pitrea8fa3f02005-06-13 22:35:41 +0100219
Eric Miao711be5c2007-07-18 11:38:45 +0100220static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = {
Robert Jarzmik649de512008-05-02 21:17:06 +0100221 .save_count = SLEEP_SAVE_COUNT,
Rafael J. Wysocki26398a72007-10-18 03:04:40 -0700222 .valid = suspend_valid_only_mem,
Eric Miao711be5c2007-07-18 11:38:45 +0100223 .save = pxa25x_cpu_pm_save,
224 .restore = pxa25x_cpu_pm_restore,
225 .enter = pxa25x_cpu_pm_enter,
Russell Kinge176bb02007-05-15 11:16:10 +0100226};
Eric Miao711be5c2007-07-18 11:38:45 +0100227
228static void __init pxa25x_init_pm(void)
229{
230 pxa_cpu_pm_fns = &pxa25x_cpu_pm_fns;
231}
eric miaof79299c2008-01-02 08:24:49 +0800232#else
233static inline void pxa25x_init_pm(void) {}
Nicolas Pitrea8fa3f02005-06-13 22:35:41 +0100234#endif
Russell Kinge176bb02007-05-15 11:16:10 +0100235
eric miaoc95530c2007-08-29 10:22:17 +0100236/* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm
237 */
238
239static int pxa25x_set_wake(unsigned int irq, unsigned int on)
240{
241 int gpio = IRQ_TO_GPIO(irq);
eric miaoc0a596d2008-03-11 09:46:28 +0800242 uint32_t mask = 0;
eric miaoc95530c2007-08-29 10:22:17 +0100243
eric miaoc0a596d2008-03-11 09:46:28 +0800244 if (gpio >= 0 && gpio < 85)
245 return gpio_set_wake(gpio, on);
eric miaoc95530c2007-08-29 10:22:17 +0100246
247 if (irq == IRQ_RTCAlrm) {
248 mask = PWER_RTC;
249 goto set_pwer;
250 }
251
252 return -EINVAL;
253
254set_pwer:
255 if (on)
256 PWER |= mask;
257 else
258 PWER &=~mask;
259
260 return 0;
261}
262
Eric Miaocd491042007-06-22 04:14:09 +0100263void __init pxa25x_init_irq(void)
264{
eric miaob9e25ac2008-03-04 14:19:58 +0800265 pxa_init_irq(32, pxa25x_set_wake);
266 pxa_init_gpio(85, pxa25x_set_wake);
Eric Miaocd491042007-06-22 04:14:09 +0100267}
268
Russell King34f32312007-05-15 10:39:49 +0100269static struct platform_device *pxa25x_devices[] __initdata = {
Philipp Zabel7a857622008-06-22 23:36:39 +0100270 &pxa25x_device_udc,
Eric Miaoe09d02e2007-07-17 10:45:58 +0100271 &pxa_device_ffuart,
272 &pxa_device_btuart,
273 &pxa_device_stuart,
Eric Miaoe09d02e2007-07-17 10:45:58 +0100274 &pxa_device_i2s,
Eric Miaoe09d02e2007-07-17 10:45:58 +0100275 &pxa_device_rtc,
eric miaod8e0db12007-12-10 17:54:36 +0800276 &pxa25x_device_ssp,
277 &pxa25x_device_nssp,
278 &pxa25x_device_assp,
eric miao75540c12008-04-13 21:44:04 +0100279 &pxa25x_device_pwm0,
280 &pxa25x_device_pwm1,
Russell King34f32312007-05-15 10:39:49 +0100281};
282
eric miaoc01655042008-01-28 23:00:02 +0000283static struct sys_device pxa25x_sysdev[] = {
284 {
285 .cls = &pxa_irq_sysclass,
eric miao16dfdbf2008-01-28 23:00:02 +0000286 }, {
287 .cls = &pxa_gpio_sysclass,
eric miaoc01655042008-01-28 23:00:02 +0000288 },
289};
290
Russell Kinge176bb02007-05-15 11:16:10 +0100291static int __init pxa25x_init(void)
292{
eric miaoc01655042008-01-28 23:00:02 +0000293 int i, ret = 0;
Eric Miaof53f0662007-06-22 05:40:17 +0100294
Dmitry Baryshkove01dbdb2008-01-27 23:11:48 +0100295 /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */
296 if (cpu_is_pxa25x())
297 clks_register(&pxa25x_hwuart_clk, 1);
298
Russell Kinge176bb02007-05-15 11:16:10 +0100299 if (cpu_is_pxa21x() || cpu_is_pxa25x()) {
Russell Kinga6dba202007-08-20 10:18:02 +0100300 clks_register(pxa25x_clks, ARRAY_SIZE(pxa25x_clks));
301
Eric Miaof53f0662007-06-22 05:40:17 +0100302 if ((ret = pxa_init_dma(16)))
303 return ret;
eric miaof79299c2008-01-02 08:24:49 +0800304
Eric Miao711be5c2007-07-18 11:38:45 +0100305 pxa25x_init_pm();
eric miaof79299c2008-01-02 08:24:49 +0800306
eric miaoc01655042008-01-28 23:00:02 +0000307 for (i = 0; i < ARRAY_SIZE(pxa25x_sysdev); i++) {
308 ret = sysdev_register(&pxa25x_sysdev[i]);
309 if (ret)
310 pr_err("failed to register sysdev[%d]\n", i);
311 }
312
Russell King34f32312007-05-15 10:39:49 +0100313 ret = platform_add_devices(pxa25x_devices,
314 ARRAY_SIZE(pxa25x_devices));
eric miaoc01655042008-01-28 23:00:02 +0000315 if (ret)
316 return ret;
Russell Kinge176bb02007-05-15 11:16:10 +0100317 }
eric miaoc01655042008-01-28 23:00:02 +0000318
Russell King34f32312007-05-15 10:39:49 +0100319 /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */
320 if (cpu_is_pxa25x())
Eric Miaoe09d02e2007-07-17 10:45:58 +0100321 ret = platform_device_register(&pxa_device_hwuart);
Russell King34f32312007-05-15 10:39:49 +0100322
Russell Kingbdb08cb2008-06-30 19:47:59 +0100323 clks_register(&gpio7_clk, 1);
324
Russell King34f32312007-05-15 10:39:49 +0100325 return ret;
Russell Kinge176bb02007-05-15 11:16:10 +0100326}
327
Russell King1c104e02008-04-19 10:59:24 +0100328postcore_initcall(pxa25x_init);