Siddartha Mohanadoss | 7b116e1 | 2012-06-05 23:27:46 -0700 | [diff] [blame^] | 1 | /* Copyright (c) 2012, Code Aurora Forum. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #define pr_fmt(fmt) "%s: " fmt, __func__ |
| 14 | |
| 15 | #include <linux/kernel.h> |
| 16 | #include <linux/of.h> |
| 17 | #include <linux/err.h> |
| 18 | #include <linux/init.h> |
| 19 | #include <linux/slab.h> |
| 20 | #include <linux/delay.h> |
| 21 | #include <linux/mutex.h> |
| 22 | #include <linux/types.h> |
| 23 | #include <linux/hwmon.h> |
| 24 | #include <linux/module.h> |
| 25 | #include <linux/debugfs.h> |
| 26 | #include <linux/spmi.h> |
| 27 | #include <linux/of_irq.h> |
| 28 | #include <linux/interrupt.h> |
| 29 | #include <linux/completion.h> |
| 30 | #include <linux/hwmon-sysfs.h> |
| 31 | #include <linux/qpnp/qpnp-adc.h> |
| 32 | #include <linux/platform_device.h> |
| 33 | |
| 34 | /* QPNP VADC register definition */ |
| 35 | #define QPNP_VADC_STATUS1 0x8 |
| 36 | #define QPNP_VADC_STATUS1_OP_MODE 4 |
| 37 | #define QPNP_VADC_STATUS1_MEAS_INTERVAL_EN_STS BIT(2) |
| 38 | #define QPNP_VADC_STATUS1_REQ_STS BIT(1) |
| 39 | #define QPNP_VADC_STATUS1_EOC BIT(0) |
| 40 | #define QPNP_VADC_STATUS2 0x9 |
| 41 | #define QPNP_VADC_STATUS2_CONV_SEQ_STATE 6 |
| 42 | #define QPNP_VADC_STATUS2_FIFO_NOT_EMPTY_FLAG BIT(1) |
| 43 | #define QPNP_VADC_STATUS2_CONV_SEQ_TIMEOUT_STS BIT(0) |
| 44 | #define QPNP_VADC_STATUS2_CONV_SEQ_STATE_SHIFT 4 |
| 45 | #define QPNP_VADC_CONV_TIMEOUT_ERR 2 |
| 46 | |
| 47 | #define QPNP_VADC_INT_SET_TYPE 0x11 |
| 48 | #define QPNP_VADC_INT_POLARITY_HIGH 0x12 |
| 49 | #define QPNP_VADC_INT_POLARITY_LOW 0x13 |
| 50 | #define QPNP_VADC_INT_LATCHED_CLR 0x14 |
| 51 | #define QPNP_VADC_INT_EN_SET 0x15 |
| 52 | #define QPNP_VADC_INT_CLR 0x16 |
| 53 | #define QPNP_VADC_INT_LOW_THR_BIT BIT(4) |
| 54 | #define QPNP_VADC_INT_HIGH_THR_BIT BIT(3) |
| 55 | #define QPNP_VADC_INT_CONV_SEQ_TIMEOUT_BIT BIT(2) |
| 56 | #define QPNP_VADC_INT_FIFO_NOT_EMPTY_BIT BIT(1) |
| 57 | #define QPNP_VADC_INT_EOC_BIT BIT(0) |
| 58 | #define QPNP_VADC_INT_CLR_MASK 0x1f |
| 59 | #define QPNP_VADC_MODE_CTL 0x40 |
| 60 | #define QPNP_VADC_OP_MODE_SHIFT 4 |
| 61 | #define QPNP_VADC_VREF_XO_THM_FORCE BIT(2) |
| 62 | #define QPNP_VADC_AMUX_TRIM_EN BIT(1) |
| 63 | #define QPNP_VADC_ADC_TRIM_EN BIT(0) |
| 64 | #define QPNP_VADC_EN_CTL1 0x46 |
| 65 | #define QPNP_VADC_ADC_EN BIT(7) |
| 66 | #define QPNP_VADC_ADC_CH_SEL_CTL 0x48 |
| 67 | #define QPNP_VADC_ADC_DIG_PARAM 0x50 |
| 68 | #define QPNP_VADC_ADC_DIG_DEC_RATIO_SEL_SHIFT 3 |
| 69 | #define QPNP_VADC_HW_SETTLE_DELAY 0x51 |
| 70 | #define QPNP_VADC_CONV_REQ 0x52 |
| 71 | #define QPNP_VADC_CONV_REQ_SET BIT(7) |
| 72 | #define QPNP_VADC_CONV_SEQ_CTL 0x54 |
| 73 | #define QPNP_VADC_CONV_SEQ_HOLDOFF_SHIFT 4 |
| 74 | #define QPNP_VADC_CONV_SEQ_TRIG_CTL 0x55 |
| 75 | #define QPNP_VADC_CONV_SEQ_FALLING_EDGE 0x0 |
| 76 | #define QPNP_VADC_CONV_SEQ_RISING_EDGE 0x1 |
| 77 | #define QPNP_VADC_CONV_SEQ_EDGE_SHIFT 7 |
| 78 | #define QPNP_VADC_FAST_AVG_CTL 0x5a |
| 79 | |
| 80 | #define QPNP_VADC_M0_LOW_THR_LSB 0x5c |
| 81 | #define QPNP_VADC_M0_LOW_THR_MSB 0x5d |
| 82 | #define QPNP_VADC_M0_HIGH_THR_LSB 0x5e |
| 83 | #define QPNP_VADC_M0_HIGH_THR_MSB 0x5f |
| 84 | #define QPNP_VADC_M1_LOW_THR_LSB 0x69 |
| 85 | #define QPNP_VADC_M1_LOW_THR_MSB 0x6a |
| 86 | #define QPNP_VADC_M1_HIGH_THR_LSB 0x6b |
| 87 | #define QPNP_VADC_M1_HIGH_THR_MSB 0x6c |
| 88 | |
| 89 | #define QPNP_VADC_DATA0 0x60 |
| 90 | #define QPNP_VADC_DATA1 0x61 |
| 91 | #define QPNP_VADC_CONV_TIMEOUT_ERR 2 |
| 92 | #define QPNP_VADC_CONV_TIME_MIN 2000 |
| 93 | #define QPNP_VADC_CONV_TIME_MAX 2100 |
| 94 | |
| 95 | #define QPNP_ADC_HWMON_NAME_LENGTH 16 |
| 96 | |
| 97 | struct qpnp_vadc_drv { |
| 98 | struct qpnp_adc_drv *adc; |
| 99 | struct dentry *dent; |
| 100 | struct device *vadc_hwmon; |
| 101 | bool vadc_init_calib; |
| 102 | struct sensor_device_attribute sens_attr[0]; |
| 103 | }; |
| 104 | |
| 105 | struct qpnp_vadc_drv *qpnp_vadc; |
| 106 | |
| 107 | static struct qpnp_vadc_scale_fn vadc_scale_fn[] = { |
| 108 | [SCALE_DEFAULT] = {qpnp_adc_scale_default}, |
| 109 | }; |
| 110 | |
| 111 | static int32_t qpnp_vadc_read_reg(int16_t reg, u8 *data) |
| 112 | { |
| 113 | struct qpnp_vadc_drv *vadc = qpnp_vadc; |
| 114 | int rc; |
| 115 | |
| 116 | rc = spmi_ext_register_readl(vadc->adc->spmi->ctrl, vadc->adc->slave, |
| 117 | reg, data, 1); |
| 118 | if (rc < 0) { |
| 119 | pr_err("qpnp adc read reg %d failed with %d\n", reg, rc); |
| 120 | return rc; |
| 121 | } |
| 122 | |
| 123 | return 0; |
| 124 | } |
| 125 | |
| 126 | static int32_t qpnp_vadc_write_reg(int16_t reg, u8 data) |
| 127 | { |
| 128 | struct qpnp_vadc_drv *vadc = qpnp_vadc; |
| 129 | int rc; |
| 130 | u8 *buf; |
| 131 | |
| 132 | buf = &data; |
| 133 | |
| 134 | rc = spmi_ext_register_writel(vadc->adc->spmi->ctrl, vadc->adc->slave, |
| 135 | reg, buf, 1); |
| 136 | if (rc < 0) { |
| 137 | pr_err("qpnp adc write reg %d failed with %d\n", reg, rc); |
| 138 | return rc; |
| 139 | } |
| 140 | |
| 141 | return 0; |
| 142 | } |
| 143 | |
| 144 | static int32_t qpnp_vadc_configure_interrupt(void) |
| 145 | { |
| 146 | int rc = 0; |
| 147 | u8 data = 0; |
| 148 | |
| 149 | /* Configure interrupt as an Edge trigger */ |
| 150 | rc = qpnp_vadc_write_reg(QPNP_VADC_INT_SET_TYPE, |
| 151 | QPNP_VADC_INT_CLR_MASK); |
| 152 | if (rc < 0) { |
| 153 | pr_err("%s Interrupt configure failed\n", __func__); |
| 154 | return rc; |
| 155 | } |
| 156 | |
| 157 | /* Configure interrupt for rising edge trigger */ |
| 158 | rc = qpnp_vadc_write_reg(QPNP_VADC_INT_POLARITY_HIGH, |
| 159 | QPNP_VADC_INT_CLR_MASK); |
| 160 | if (rc < 0) { |
| 161 | pr_err("%s Rising edge trigger configure failed\n", __func__); |
| 162 | return rc; |
| 163 | } |
| 164 | |
| 165 | /* Disable low level interrupt triggering */ |
| 166 | data = QPNP_VADC_INT_CLR_MASK; |
| 167 | rc = qpnp_vadc_write_reg(QPNP_VADC_INT_POLARITY_LOW, |
| 168 | (~data & QPNP_VADC_INT_CLR_MASK)); |
| 169 | if (rc < 0) { |
| 170 | pr_err("%s Setting level low to disable failed\n", __func__); |
| 171 | return rc; |
| 172 | } |
| 173 | |
| 174 | return 0; |
| 175 | } |
| 176 | |
| 177 | static int32_t qpnp_vadc_enable(bool state) |
| 178 | { |
| 179 | int rc = 0; |
| 180 | u8 data = 0; |
| 181 | |
| 182 | data = QPNP_VADC_ADC_EN; |
| 183 | if (state) { |
| 184 | rc = qpnp_vadc_write_reg(QPNP_VADC_EN_CTL1, |
| 185 | data); |
| 186 | if (rc < 0) { |
| 187 | pr_err("VADC enable failed\n"); |
| 188 | return rc; |
| 189 | } |
| 190 | } else { |
| 191 | rc = qpnp_vadc_write_reg(QPNP_VADC_EN_CTL1, |
| 192 | (~data & QPNP_VADC_ADC_EN)); |
| 193 | if (rc < 0) { |
| 194 | pr_err("VADC disable failed\n"); |
| 195 | return rc; |
| 196 | } |
| 197 | } |
| 198 | |
| 199 | return 0; |
| 200 | } |
| 201 | |
| 202 | int32_t qpnp_vadc_configure( |
| 203 | struct qpnp_vadc_amux_properties *chan_prop) |
| 204 | { |
| 205 | u8 decimation = 0, conv_sequence = 0, conv_sequence_trig = 0; |
| 206 | int rc = 0; |
| 207 | |
| 208 | rc = qpnp_vadc_write_reg(QPNP_VADC_INT_EN_SET, |
| 209 | QPNP_VADC_INT_EOC_BIT); |
| 210 | if (rc < 0) { |
| 211 | pr_err("qpnp adc configure error for interrupt setup\n"); |
| 212 | return rc; |
| 213 | } |
| 214 | |
| 215 | rc = qpnp_vadc_write_reg(QPNP_VADC_MODE_CTL, chan_prop->mode_sel); |
| 216 | if (rc < 0) { |
| 217 | pr_err("qpnp adc configure error for mode selection\n"); |
| 218 | return rc; |
| 219 | } |
| 220 | |
| 221 | rc = qpnp_vadc_write_reg(QPNP_VADC_ADC_CH_SEL_CTL, |
| 222 | chan_prop->amux_channel); |
| 223 | if (rc < 0) { |
| 224 | pr_err("qpnp adc configure error for channel selection\n"); |
| 225 | return rc; |
| 226 | } |
| 227 | |
| 228 | decimation |= chan_prop->decimation << |
| 229 | QPNP_VADC_ADC_DIG_DEC_RATIO_SEL_SHIFT; |
| 230 | rc = qpnp_vadc_write_reg(QPNP_VADC_ADC_DIG_PARAM, decimation); |
| 231 | if (rc < 0) { |
| 232 | pr_err("qpnp adc configure error for digital parameter setup\n"); |
| 233 | return rc; |
| 234 | } |
| 235 | |
| 236 | rc = qpnp_vadc_write_reg(QPNP_VADC_HW_SETTLE_DELAY, |
| 237 | chan_prop->hw_settle_time); |
| 238 | if (rc < 0) { |
| 239 | pr_err("qpnp adc configure error for hw settling time setup\n"); |
| 240 | return rc; |
| 241 | } |
| 242 | |
| 243 | if (chan_prop->mode_sel == (ADC_OP_NORMAL_MODE << |
| 244 | QPNP_VADC_OP_MODE_SHIFT)) { |
| 245 | rc = qpnp_vadc_write_reg(QPNP_VADC_FAST_AVG_CTL, |
| 246 | chan_prop->fast_avg_setup); |
| 247 | if (rc < 0) { |
| 248 | pr_err("qpnp adc fast averaging configure error\n"); |
| 249 | return rc; |
| 250 | } |
| 251 | } else if (chan_prop->mode_sel == (ADC_OP_CONVERSION_SEQUENCER << |
| 252 | QPNP_VADC_OP_MODE_SHIFT)) { |
| 253 | conv_sequence = ((ADC_SEQ_HOLD_100US << |
| 254 | QPNP_VADC_CONV_SEQ_HOLDOFF_SHIFT) | |
| 255 | ADC_CONV_SEQ_TIMEOUT_5MS); |
| 256 | rc = qpnp_vadc_write_reg(QPNP_VADC_CONV_SEQ_CTL, |
| 257 | conv_sequence); |
| 258 | if (rc < 0) { |
| 259 | pr_err("qpnp adc conversion sequence error\n"); |
| 260 | return rc; |
| 261 | } |
| 262 | |
| 263 | conv_sequence_trig = ((QPNP_VADC_CONV_SEQ_RISING_EDGE << |
| 264 | QPNP_VADC_CONV_SEQ_EDGE_SHIFT) | |
| 265 | chan_prop->trigger_channel); |
| 266 | rc = qpnp_vadc_write_reg(QPNP_VADC_CONV_SEQ_TRIG_CTL, |
| 267 | conv_sequence_trig); |
| 268 | if (rc < 0) { |
| 269 | pr_err("qpnp adc conversion trigger error\n"); |
| 270 | return rc; |
| 271 | } |
| 272 | } |
| 273 | |
| 274 | rc = qpnp_vadc_write_reg(QPNP_VADC_CONV_REQ, QPNP_VADC_CONV_REQ_SET); |
| 275 | if (rc < 0) { |
| 276 | pr_err("qpnp adc request conversion failed\n"); |
| 277 | return rc; |
| 278 | } |
| 279 | |
| 280 | return 0; |
| 281 | } |
| 282 | EXPORT_SYMBOL(qpnp_vadc_configure); |
| 283 | |
| 284 | static int32_t qpnp_vadc_read_conversion_result(int32_t *data) |
| 285 | { |
| 286 | uint8_t rslt_lsb, rslt_msb; |
| 287 | int rc = 0; |
| 288 | |
| 289 | rc = qpnp_vadc_read_reg(QPNP_VADC_DATA0, &rslt_lsb); |
| 290 | if (rc < 0) { |
| 291 | pr_err("qpnp adc result read failed for data0 with %d\n", rc); |
| 292 | return rc; |
| 293 | } |
| 294 | |
| 295 | rc = qpnp_vadc_read_reg(QPNP_VADC_DATA1, &rslt_msb); |
| 296 | if (rc < 0) { |
| 297 | pr_err("qpnp adc result read failed for data1 with %d\n", rc); |
| 298 | return rc; |
| 299 | } |
| 300 | |
| 301 | *data = (rslt_msb << 8) | rslt_lsb; |
| 302 | |
| 303 | rc = qpnp_vadc_check_result(data); |
| 304 | if (rc < 0) { |
| 305 | pr_err("VADC data check failed\n"); |
| 306 | return rc; |
| 307 | } |
| 308 | |
| 309 | return 0; |
| 310 | } |
| 311 | |
| 312 | static int32_t qpnp_vadc_read_status(int mode_sel) |
| 313 | { |
| 314 | u8 status1, status2, status2_conv_seq_state; |
| 315 | u8 status_err = QPNP_VADC_CONV_TIMEOUT_ERR; |
| 316 | int rc; |
| 317 | |
| 318 | switch (mode_sel) { |
| 319 | case (ADC_OP_CONVERSION_SEQUENCER << QPNP_VADC_OP_MODE_SHIFT): |
| 320 | rc = qpnp_vadc_read_reg(QPNP_VADC_STATUS1, &status1); |
| 321 | if (rc) { |
| 322 | pr_err("qpnp_vadc read mask interrupt failed\n"); |
| 323 | return rc; |
| 324 | } |
| 325 | |
| 326 | rc = qpnp_vadc_read_reg(QPNP_VADC_STATUS2, &status2); |
| 327 | if (rc) { |
| 328 | pr_err("qpnp_vadc read mask interrupt failed\n"); |
| 329 | return rc; |
| 330 | } |
| 331 | |
| 332 | if (!(status2 & ~QPNP_VADC_STATUS2_CONV_SEQ_TIMEOUT_STS) && |
| 333 | (status1 & (~QPNP_VADC_STATUS1_REQ_STS | |
| 334 | QPNP_VADC_STATUS1_EOC))) { |
| 335 | rc = status_err; |
| 336 | return rc; |
| 337 | } |
| 338 | |
| 339 | status2_conv_seq_state = status2 >> |
| 340 | QPNP_VADC_STATUS2_CONV_SEQ_STATE_SHIFT; |
| 341 | if (status2_conv_seq_state != ADC_CONV_SEQ_IDLE) { |
| 342 | pr_err("qpnp vadc seq error with status %d\n", |
| 343 | status2); |
| 344 | rc = -EINVAL; |
| 345 | return rc; |
| 346 | } |
| 347 | } |
| 348 | |
| 349 | return 0; |
| 350 | } |
| 351 | |
| 352 | static void qpnp_vadc_work(struct work_struct *work) |
| 353 | { |
| 354 | struct qpnp_vadc_drv *vadc = qpnp_vadc; |
| 355 | int rc; |
| 356 | |
| 357 | rc = qpnp_vadc_write_reg(QPNP_VADC_INT_CLR, QPNP_VADC_INT_EOC_BIT); |
| 358 | if (rc) |
| 359 | pr_err("qpnp_vadc clear mask interrupt failed with %d\n", rc); |
| 360 | |
| 361 | complete(&vadc->adc->adc_rslt_completion); |
| 362 | |
| 363 | return; |
| 364 | } |
| 365 | DECLARE_WORK(trigger_completion_work, qpnp_vadc_work); |
| 366 | |
| 367 | static irqreturn_t qpnp_vadc_isr(int irq, void *dev_id) |
| 368 | { |
| 369 | schedule_work(&trigger_completion_work); |
| 370 | |
| 371 | return IRQ_HANDLED; |
| 372 | } |
| 373 | |
| 374 | static uint32_t qpnp_vadc_calib_device(void) |
| 375 | { |
| 376 | struct qpnp_vadc_drv *vadc = qpnp_vadc; |
| 377 | struct qpnp_vadc_amux_properties conv; |
| 378 | int rc, calib_read_1, calib_read_2; |
| 379 | u8 status1 = 0; |
| 380 | |
| 381 | conv.amux_channel = REF_125V; |
| 382 | conv.decimation = DECIMATION_TYPE2; |
| 383 | conv.mode_sel = ADC_OP_NORMAL_MODE << QPNP_VADC_OP_MODE_SHIFT; |
| 384 | conv.hw_settle_time = ADC_CHANNEL_HW_SETTLE_DELAY_0US; |
| 385 | conv.fast_avg_setup = ADC_FAST_AVG_SAMPLE_1; |
| 386 | |
| 387 | rc = qpnp_vadc_configure(&conv); |
| 388 | if (rc) { |
| 389 | pr_err("qpnp_vadc configure failed with %d\n", rc); |
| 390 | goto calib_fail; |
| 391 | } |
| 392 | |
| 393 | while (status1 != (~QPNP_VADC_STATUS1_REQ_STS | |
| 394 | QPNP_VADC_STATUS1_EOC)) { |
| 395 | rc = qpnp_vadc_read_reg(QPNP_VADC_STATUS1, &status1); |
| 396 | if (rc < 0) |
| 397 | return rc; |
| 398 | usleep_range(QPNP_VADC_CONV_TIME_MIN, |
| 399 | QPNP_VADC_CONV_TIME_MAX); |
| 400 | } |
| 401 | |
| 402 | rc = qpnp_vadc_read_conversion_result(&calib_read_1); |
| 403 | if (rc) { |
| 404 | pr_err("qpnp adc read adc failed with %d\n", rc); |
| 405 | goto calib_fail; |
| 406 | } |
| 407 | |
| 408 | conv.amux_channel = REF_625MV; |
| 409 | conv.decimation = DECIMATION_TYPE2; |
| 410 | conv.mode_sel = ADC_OP_NORMAL_MODE << QPNP_VADC_OP_MODE_SHIFT; |
| 411 | conv.hw_settle_time = ADC_CHANNEL_HW_SETTLE_DELAY_0US; |
| 412 | conv.fast_avg_setup = ADC_FAST_AVG_SAMPLE_1; |
| 413 | rc = qpnp_vadc_configure(&conv); |
| 414 | if (rc) { |
| 415 | pr_err("qpnp adc configure failed with %d\n", rc); |
| 416 | goto calib_fail; |
| 417 | } |
| 418 | |
| 419 | while (status1 != (~QPNP_VADC_STATUS1_REQ_STS | |
| 420 | QPNP_VADC_STATUS1_EOC)) { |
| 421 | rc = qpnp_vadc_read_reg(QPNP_VADC_STATUS1, &status1); |
| 422 | if (rc < 0) |
| 423 | return rc; |
| 424 | usleep_range(QPNP_VADC_CONV_TIME_MIN, |
| 425 | QPNP_VADC_CONV_TIME_MAX); |
| 426 | } |
| 427 | |
| 428 | rc = qpnp_vadc_read_conversion_result(&calib_read_1); |
| 429 | if (rc) { |
| 430 | pr_err("qpnp adc read adc failed with %d\n", rc); |
| 431 | goto calib_fail; |
| 432 | } |
| 433 | |
| 434 | vadc->adc->amux_prop->chan_prop->adc_graph[CALIB_ABSOLUTE].dy = |
| 435 | (calib_read_1 - calib_read_2); |
| 436 | vadc->adc->amux_prop->chan_prop->adc_graph[CALIB_ABSOLUTE].dx |
| 437 | = QPNP_ADC_625_UV; |
| 438 | vadc->adc->amux_prop->chan_prop->adc_graph[CALIB_ABSOLUTE].adc_vref = |
| 439 | calib_read_1; |
| 440 | vadc->adc->amux_prop->chan_prop->adc_graph[CALIB_ABSOLUTE].adc_gnd = |
| 441 | calib_read_2; |
| 442 | /* Ratiometric Calibration */ |
| 443 | conv.amux_channel = VDD_VADC; |
| 444 | conv.decimation = DECIMATION_TYPE2; |
| 445 | conv.mode_sel = ADC_OP_NORMAL_MODE << QPNP_VADC_OP_MODE_SHIFT; |
| 446 | conv.hw_settle_time = ADC_CHANNEL_HW_SETTLE_DELAY_0US; |
| 447 | conv.fast_avg_setup = ADC_FAST_AVG_SAMPLE_1; |
| 448 | rc = qpnp_vadc_configure(&conv); |
| 449 | if (rc) { |
| 450 | pr_err("qpnp adc configure failed with %d\n", rc); |
| 451 | goto calib_fail; |
| 452 | } |
| 453 | |
| 454 | while (status1 != (~QPNP_VADC_STATUS1_REQ_STS | |
| 455 | QPNP_VADC_STATUS1_EOC)) { |
| 456 | rc = qpnp_vadc_read_reg(QPNP_VADC_STATUS1, &status1); |
| 457 | if (rc < 0) |
| 458 | return rc; |
| 459 | usleep_range(QPNP_VADC_CONV_TIME_MIN, |
| 460 | QPNP_VADC_CONV_TIME_MAX); |
| 461 | } |
| 462 | |
| 463 | rc = qpnp_vadc_read_conversion_result(&calib_read_1); |
| 464 | if (rc) { |
| 465 | pr_err("qpnp adc read adc failed with %d\n", rc); |
| 466 | goto calib_fail; |
| 467 | } |
| 468 | |
| 469 | conv.amux_channel = VDD_VADC; |
| 470 | conv.decimation = DECIMATION_TYPE2; |
| 471 | conv.mode_sel = ADC_OP_NORMAL_MODE << QPNP_VADC_OP_MODE_SHIFT; |
| 472 | conv.hw_settle_time = ADC_CHANNEL_HW_SETTLE_DELAY_0US; |
| 473 | conv.fast_avg_setup = ADC_FAST_AVG_SAMPLE_1; |
| 474 | rc = qpnp_vadc_configure(&conv); |
| 475 | if (rc) { |
| 476 | pr_err("qpnp adc configure failed with %d\n", rc); |
| 477 | goto calib_fail; |
| 478 | } |
| 479 | |
| 480 | while (status1 != (~QPNP_VADC_STATUS1_REQ_STS | |
| 481 | QPNP_VADC_STATUS1_EOC)) { |
| 482 | rc = qpnp_vadc_read_reg(QPNP_VADC_STATUS1, &status1); |
| 483 | if (rc < 0) |
| 484 | return rc; |
| 485 | usleep_range(QPNP_VADC_CONV_TIME_MIN, |
| 486 | QPNP_VADC_CONV_TIME_MAX); |
| 487 | } |
| 488 | |
| 489 | rc = qpnp_vadc_read_conversion_result(&calib_read_1); |
| 490 | if (rc) { |
| 491 | pr_err("qpnp adc read adc failed with %d\n", rc); |
| 492 | goto calib_fail; |
| 493 | } |
| 494 | |
| 495 | vadc->adc->amux_prop->chan_prop->adc_graph[CALIB_RATIOMETRIC].dy = |
| 496 | (calib_read_1 - calib_read_2); |
| 497 | vadc->adc->amux_prop->chan_prop->adc_graph[CALIB_RATIOMETRIC].dx = |
| 498 | vadc->adc->adc_prop->adc_vdd_reference; |
| 499 | vadc->adc->amux_prop->chan_prop->adc_graph[CALIB_RATIOMETRIC].adc_vref = |
| 500 | calib_read_1; |
| 501 | vadc->adc->amux_prop->chan_prop->adc_graph[CALIB_RATIOMETRIC].adc_gnd = |
| 502 | calib_read_2; |
| 503 | |
| 504 | calib_fail: |
| 505 | return rc; |
| 506 | } |
| 507 | |
| 508 | int32_t qpnp_vadc_conv_seq_request(enum qpnp_vadc_trigger trigger_channel, |
| 509 | enum qpnp_vadc_channels channel, |
| 510 | struct qpnp_vadc_result *result) |
| 511 | { |
| 512 | struct qpnp_vadc_drv *vadc = qpnp_vadc; |
| 513 | int rc, scale_type, amux_prescaling; |
| 514 | |
| 515 | if (!vadc->vadc_init_calib) { |
| 516 | rc = qpnp_vadc_calib_device(); |
| 517 | if (rc) { |
| 518 | pr_err("Calibration failed\n"); |
| 519 | return rc; |
| 520 | } else |
| 521 | vadc->vadc_init_calib = true; |
| 522 | } |
| 523 | |
| 524 | mutex_lock(&vadc->adc->adc_lock); |
| 525 | |
| 526 | rc = qpnp_vadc_enable(true); |
| 527 | if (rc) |
| 528 | goto fail_unlock; |
| 529 | |
| 530 | vadc->adc->amux_prop->amux_channel = channel; |
| 531 | vadc->adc->amux_prop->decimation = |
| 532 | vadc->adc->adc_channels[channel].adc_decimation; |
| 533 | vadc->adc->amux_prop->hw_settle_time = |
| 534 | vadc->adc->adc_channels[channel].hw_settle_time; |
| 535 | vadc->adc->amux_prop->fast_avg_setup = |
| 536 | vadc->adc->adc_channels[channel].fast_avg_setup; |
| 537 | |
| 538 | if (trigger_channel < ADC_SEQ_NONE) |
| 539 | vadc->adc->amux_prop->mode_sel = (ADC_OP_CONVERSION_SEQUENCER |
| 540 | << QPNP_VADC_OP_MODE_SHIFT); |
| 541 | else if (trigger_channel == ADC_SEQ_NONE) |
| 542 | vadc->adc->amux_prop->mode_sel = (ADC_OP_NORMAL_MODE |
| 543 | << QPNP_VADC_OP_MODE_SHIFT); |
| 544 | else { |
| 545 | pr_err("Invalid trigger channel:%d\n", trigger_channel); |
| 546 | goto fail; |
| 547 | } |
| 548 | |
| 549 | vadc->adc->amux_prop->trigger_channel = trigger_channel; |
| 550 | |
| 551 | rc = qpnp_vadc_configure(vadc->adc->amux_prop); |
| 552 | if (rc) { |
| 553 | pr_info("qpnp vadc configure failed with %d\n", rc); |
| 554 | goto fail; |
| 555 | } |
| 556 | |
| 557 | wait_for_completion(&vadc->adc->adc_rslt_completion); |
| 558 | |
| 559 | if (trigger_channel < ADC_SEQ_NONE) { |
| 560 | rc = qpnp_vadc_read_status(vadc->adc->amux_prop->mode_sel); |
| 561 | if (rc) |
| 562 | pr_info("Conversion sequence timed out - %d\n", rc); |
| 563 | } |
| 564 | |
| 565 | rc = qpnp_vadc_read_conversion_result(&result->adc_code); |
| 566 | if (rc) { |
| 567 | pr_info("qpnp vadc read adc code failed with %d\n", rc); |
| 568 | goto fail; |
| 569 | } |
| 570 | |
| 571 | amux_prescaling = vadc->adc->adc_channels[channel].chan_path_prescaling; |
| 572 | |
| 573 | vadc->adc->amux_prop->chan_prop->offset_gain_numerator = |
| 574 | qpnp_vadc_amux_scaling_ratio[amux_prescaling].num; |
| 575 | vadc->adc->amux_prop->chan_prop->offset_gain_denominator = |
| 576 | qpnp_vadc_amux_scaling_ratio[amux_prescaling].den; |
| 577 | |
| 578 | scale_type = vadc->adc->adc_channels[channel].adc_scale_fn; |
| 579 | if (scale_type >= SCALE_NONE) { |
| 580 | rc = -EBADF; |
| 581 | goto fail; |
| 582 | } |
| 583 | |
| 584 | vadc_scale_fn[scale_type].chan(result->adc_code, |
| 585 | vadc->adc->adc_prop, vadc->adc->amux_prop->chan_prop, result); |
| 586 | |
| 587 | fail: |
| 588 | rc = qpnp_vadc_enable(false); |
| 589 | if (rc) |
| 590 | pr_err("Disable ADC failed during configuration\n"); |
| 591 | |
| 592 | fail_unlock: |
| 593 | mutex_unlock(&vadc->adc->adc_lock); |
| 594 | |
| 595 | return rc; |
| 596 | } |
| 597 | EXPORT_SYMBOL(qpnp_vadc_conv_seq_request); |
| 598 | |
| 599 | int32_t qpnp_vadc_read(enum qpnp_vadc_channels channel, |
| 600 | struct qpnp_vadc_result *result) |
| 601 | { |
| 602 | return qpnp_vadc_conv_seq_request(ADC_SEQ_NONE, |
| 603 | channel, result); |
| 604 | } |
| 605 | EXPORT_SYMBOL_GPL(qpnp_vadc_read); |
| 606 | |
| 607 | static ssize_t qpnp_adc_show(struct device *dev, |
| 608 | struct device_attribute *devattr, char *buf) |
| 609 | { |
| 610 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); |
| 611 | struct qpnp_vadc_result result; |
| 612 | int rc = -1; |
| 613 | |
| 614 | rc = qpnp_vadc_read(attr->index, &result); |
| 615 | |
| 616 | if (rc) |
| 617 | return 0; |
| 618 | |
| 619 | return snprintf(buf, QPNP_ADC_HWMON_NAME_LENGTH, |
| 620 | "Result:%lld Raw:%d\n", result.physical, result.adc_code); |
| 621 | } |
| 622 | |
| 623 | static struct sensor_device_attribute qpnp_adc_attr = |
| 624 | SENSOR_ATTR(NULL, S_IRUGO, qpnp_adc_show, NULL, 0); |
| 625 | |
| 626 | static int32_t qpnp_vadc_init_hwmon(struct spmi_device *spmi) |
| 627 | { |
| 628 | struct qpnp_vadc_drv *vadc = qpnp_vadc; |
| 629 | struct device_node *child; |
| 630 | struct device_node *node = spmi->dev.of_node; |
| 631 | int rc = 0, i = 0, channel; |
| 632 | |
| 633 | for_each_child_of_node(node, child) { |
| 634 | channel = vadc->adc->adc_channels[i].channel_num; |
| 635 | qpnp_adc_attr.index = vadc->adc->adc_channels[i].channel_num; |
| 636 | qpnp_adc_attr.dev_attr.attr.name = |
| 637 | vadc->adc->adc_channels[i].name; |
| 638 | sysfs_attr_init(&vadc->sens_attr[i].dev_attr.attr); |
| 639 | memcpy(&vadc->sens_attr[i], &qpnp_adc_attr, |
| 640 | sizeof(qpnp_adc_attr)); |
| 641 | rc = device_create_file(&spmi->dev, |
| 642 | &vadc->sens_attr[i].dev_attr); |
| 643 | if (rc) { |
| 644 | dev_err(&spmi->dev, |
| 645 | "device_create_file failed for dev %s\n", |
| 646 | vadc->adc->adc_channels[i].name); |
| 647 | goto hwmon_err_sens; |
| 648 | } |
| 649 | i++; |
| 650 | } |
| 651 | |
| 652 | return 0; |
| 653 | hwmon_err_sens: |
| 654 | pr_info("Init HWMON failed for qpnp_adc with %d\n", rc); |
| 655 | return rc; |
| 656 | } |
| 657 | |
| 658 | static int __devinit qpnp_vadc_probe(struct spmi_device *spmi) |
| 659 | { |
| 660 | struct qpnp_vadc_drv *vadc; |
| 661 | struct qpnp_adc_drv *adc_qpnp; |
| 662 | struct device_node *node = spmi->dev.of_node; |
| 663 | struct device_node *child; |
| 664 | int rc, count_adc_channel_list = 0; |
| 665 | |
| 666 | if (!node) |
| 667 | return -EINVAL; |
| 668 | |
| 669 | if (qpnp_vadc) { |
| 670 | pr_err("VADC already in use\n"); |
| 671 | return -EBUSY; |
| 672 | } |
| 673 | |
| 674 | for_each_child_of_node(node, child) |
| 675 | count_adc_channel_list++; |
| 676 | |
| 677 | if (!count_adc_channel_list) { |
| 678 | pr_err("No channel listing\n"); |
| 679 | return -EINVAL; |
| 680 | } |
| 681 | |
| 682 | vadc = devm_kzalloc(&spmi->dev, sizeof(struct qpnp_vadc_drv) + |
| 683 | (sizeof(struct sensor_device_attribute) * |
| 684 | count_adc_channel_list), GFP_KERNEL); |
| 685 | if (!vadc) { |
| 686 | dev_err(&spmi->dev, "Unable to allocate memory\n"); |
| 687 | return -ENOMEM; |
| 688 | } |
| 689 | |
| 690 | adc_qpnp = devm_kzalloc(&spmi->dev, sizeof(struct qpnp_adc_drv), |
| 691 | GFP_KERNEL); |
| 692 | if (!adc_qpnp) { |
| 693 | dev_err(&spmi->dev, "Unable to allocate memory\n"); |
| 694 | return -ENOMEM; |
| 695 | } |
| 696 | |
| 697 | vadc->adc = adc_qpnp; |
| 698 | |
| 699 | rc = qpnp_adc_get_devicetree_data(spmi, vadc->adc); |
| 700 | if (rc) { |
| 701 | dev_err(&spmi->dev, "failed to read device tree\n"); |
| 702 | return rc; |
| 703 | } |
| 704 | |
| 705 | rc = devm_request_irq(&spmi->dev, vadc->adc->adc_irq, |
| 706 | qpnp_vadc_isr, IRQF_TRIGGER_RISING, |
| 707 | "qpnp_vadc_interrupt", vadc); |
| 708 | if (rc) { |
| 709 | dev_err(&spmi->dev, |
| 710 | "failed to request adc irq with error %d\n", rc); |
| 711 | return rc; |
| 712 | } |
| 713 | |
| 714 | qpnp_vadc = vadc; |
| 715 | dev_set_drvdata(&spmi->dev, vadc); |
| 716 | rc = qpnp_vadc_init_hwmon(spmi); |
| 717 | if (rc) { |
| 718 | dev_err(&spmi->dev, "failed to initialize qpnp hwmon adc\n"); |
| 719 | goto fail_free_irq; |
| 720 | } |
| 721 | vadc->vadc_hwmon = hwmon_device_register(&vadc->adc->spmi->dev); |
| 722 | vadc->vadc_init_calib = false; |
| 723 | |
| 724 | rc = qpnp_vadc_configure_interrupt(); |
| 725 | if (rc) { |
| 726 | dev_err(&spmi->dev, "failed to configure interrupt"); |
| 727 | goto fail_free_irq; |
| 728 | } |
| 729 | |
| 730 | return 0; |
| 731 | |
| 732 | fail_free_irq: |
| 733 | free_irq(vadc->adc->adc_irq, vadc); |
| 734 | |
| 735 | return rc; |
| 736 | } |
| 737 | |
| 738 | static int __devexit qpnp_vadc_remove(struct spmi_device *spmi) |
| 739 | { |
| 740 | struct qpnp_vadc_drv *vadc = dev_get_drvdata(&spmi->dev); |
| 741 | struct device_node *node = spmi->dev.of_node; |
| 742 | struct device_node *child; |
| 743 | int i = 0; |
| 744 | |
| 745 | for_each_child_of_node(node, child) { |
| 746 | device_remove_file(&spmi->dev, |
| 747 | &vadc->sens_attr[i].dev_attr); |
| 748 | i++; |
| 749 | } |
| 750 | free_irq(vadc->adc->adc_irq, vadc); |
| 751 | dev_set_drvdata(&spmi->dev, NULL); |
| 752 | |
| 753 | return 0; |
| 754 | } |
| 755 | |
| 756 | static const struct of_device_id qpnp_vadc_match_table[] = { |
| 757 | { .compatible = "qcom,qpnp-vadc", |
| 758 | }, |
| 759 | {} |
| 760 | }; |
| 761 | |
| 762 | static struct spmi_driver qpnp_vadc_driver = { |
| 763 | .driver = { |
| 764 | .name = "qcom,qpnp-vadc", |
| 765 | .of_match_table = qpnp_vadc_match_table, |
| 766 | }, |
| 767 | .probe = qpnp_vadc_probe, |
| 768 | .remove = qpnp_vadc_remove, |
| 769 | }; |
| 770 | |
| 771 | static int __init qpnp_vadc_init(void) |
| 772 | { |
| 773 | return spmi_driver_register(&qpnp_vadc_driver); |
| 774 | } |
| 775 | module_init(qpnp_vadc_init); |
| 776 | |
| 777 | static void __exit qpnp_vadc_exit(void) |
| 778 | { |
| 779 | spmi_driver_unregister(&qpnp_vadc_driver); |
| 780 | } |
| 781 | module_exit(qpnp_vadc_exit); |
| 782 | |
| 783 | MODULE_DESCRIPTION("QPNP PMIC Voltage ADC driver"); |
| 784 | MODULE_LICENSE("GPL v2"); |