blob: 257865778f923ce628b673bf52f9eb4e292bd10e [file] [log] [blame]
Jaya Kumarf5b2d8b2005-11-09 23:58:16 +01001/*
2 * linux/drivers/ide/pci/cs5535.c
3 *
4 * Copyright (C) 2004-2005 Advanced Micro Devices, Inc.
Bartlomiej Zolnierkiewiczbc0b0b52007-08-01 23:46:45 +02005 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
Jaya Kumarf5b2d8b2005-11-09 23:58:16 +01006 *
7 * History:
8 * 09/20/2005 - Jaya Kumar <jayakumar.ide@gmail.com>
9 * - Reworked tuneproc, set_drive, misc mods to prep for mainline
10 * - Work was sponsored by CIS (M) Sdn Bhd.
11 * Ported to Kernel 2.6.11 on June 26, 2005 by
12 * Wolfgang Zuleger <wolfgang.zuleger@gmx.de>
13 * Alexander Kiausch <alex.kiausch@t-online.de>
14 * Originally developed by AMD for 2.4/2.6
15 *
16 * Development of this chipset driver was funded
17 * by the nice folks at National Semiconductor/AMD.
18 *
19 * This program is free software; you can redistribute it and/or modify it
20 * under the terms of the GNU General Public License version 2 as published by
21 * the Free Software Foundation.
22 *
23 * Documentation:
24 * CS5535 documentation available from AMD
25 */
26
Jaya Kumarf5b2d8b2005-11-09 23:58:16 +010027#include <linux/module.h>
28#include <linux/pci.h>
29#include <linux/ide.h>
30
31#include "ide-timing.h"
32
33#define MSR_ATAC_BASE 0x51300000
34#define ATAC_GLD_MSR_CAP (MSR_ATAC_BASE+0)
35#define ATAC_GLD_MSR_CONFIG (MSR_ATAC_BASE+0x01)
36#define ATAC_GLD_MSR_SMI (MSR_ATAC_BASE+0x02)
37#define ATAC_GLD_MSR_ERROR (MSR_ATAC_BASE+0x03)
38#define ATAC_GLD_MSR_PM (MSR_ATAC_BASE+0x04)
39#define ATAC_GLD_MSR_DIAG (MSR_ATAC_BASE+0x05)
40#define ATAC_IO_BAR (MSR_ATAC_BASE+0x08)
41#define ATAC_RESET (MSR_ATAC_BASE+0x10)
42#define ATAC_CH0D0_PIO (MSR_ATAC_BASE+0x20)
43#define ATAC_CH0D0_DMA (MSR_ATAC_BASE+0x21)
44#define ATAC_CH0D1_PIO (MSR_ATAC_BASE+0x22)
45#define ATAC_CH0D1_DMA (MSR_ATAC_BASE+0x23)
46#define ATAC_PCI_ABRTERR (MSR_ATAC_BASE+0x24)
47#define ATAC_BM0_CMD_PRIM 0x00
48#define ATAC_BM0_STS_PRIM 0x02
49#define ATAC_BM0_PRD 0x04
50#define CS5535_CABLE_DETECT 0x48
51
52/* Format I PIO settings. We seperate out cmd and data for safer timings */
53
54static unsigned int cs5535_pio_cmd_timings[5] =
55{ 0xF7F4, 0x53F3, 0x13F1, 0x5131, 0x1131 };
56static unsigned int cs5535_pio_dta_timings[5] =
57{ 0xF7F4, 0xF173, 0x8141, 0x5131, 0x1131 };
58
59static unsigned int cs5535_mwdma_timings[3] =
60{ 0x7F0FFFF3, 0x7F035352, 0x7f024241 };
61
62static unsigned int cs5535_udma_timings[5] =
63{ 0x7F7436A1, 0x7F733481, 0x7F723261, 0x7F713161, 0x7F703061 };
64
65/* Macros to check if the register is the reset value - reset value is an
66 invalid timing and indicates the register has not been set previously */
67
68#define CS5535_BAD_PIO(timings) ( (timings&~0x80000000UL) == 0x00009172 )
69#define CS5535_BAD_DMA(timings) ( (timings & 0x000FFFFF) == 0x00077771 )
70
71/****
72 * cs5535_set_speed - Configure the chipset to the new speed
73 * @drive: Drive to set up
74 * @speed: desired speed
75 *
76 * cs5535_set_speed() configures the chipset to a new speed.
77 */
Bartlomiej Zolnierkiewiczf212ff22007-10-11 23:53:59 +020078static void cs5535_set_speed(ide_drive_t *drive, const u8 speed)
Jaya Kumarf5b2d8b2005-11-09 23:58:16 +010079{
80
81 u32 reg = 0, dummy;
82 int unit = drive->select.b.unit;
83
84
85 /* Set the PIO timings */
86 if ((speed & XFER_MODE) == XFER_PIO) {
Bartlomiej Zolnierkiewiczbc0b0b52007-08-01 23:46:45 +020087 ide_drive_t *pair = &drive->hwif->drives[drive->dn ^ 1];
88 u8 cmd, pioa;
Jaya Kumarf5b2d8b2005-11-09 23:58:16 +010089
Bartlomiej Zolnierkiewiczbc0b0b52007-08-01 23:46:45 +020090 cmd = pioa = speed - XFER_PIO_0;
91
92 if (pair->present) {
93 u8 piob = ide_get_best_pio_mode(pair, 255, 4);
94
95 if (piob < cmd)
96 cmd = piob;
97 }
Jaya Kumarf5b2d8b2005-11-09 23:58:16 +010098
99 /* Write the speed of the current drive */
100 reg = (cs5535_pio_cmd_timings[cmd] << 16) |
101 cs5535_pio_dta_timings[pioa];
102 wrmsr(unit ? ATAC_CH0D1_PIO : ATAC_CH0D0_PIO, reg, 0);
103
104 /* And if nessesary - change the speed of the other drive */
105 rdmsr(unit ? ATAC_CH0D0_PIO : ATAC_CH0D1_PIO, reg, dummy);
106
107 if (((reg >> 16) & cs5535_pio_cmd_timings[cmd]) !=
108 cs5535_pio_cmd_timings[cmd]) {
109 reg &= 0x0000FFFF;
110 reg |= cs5535_pio_cmd_timings[cmd] << 16;
111 wrmsr(unit ? ATAC_CH0D0_PIO : ATAC_CH0D1_PIO, reg, 0);
112 }
113
114 /* Set bit 31 of the DMA register for PIO format 1 timings */
115 rdmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, dummy);
116 wrmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA,
117 reg | 0x80000000UL, 0);
118 } else {
119 rdmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, dummy);
120
121 reg &= 0x80000000UL; /* Preserve the PIO format bit */
122
Jordan Crouse32a70a82007-08-01 23:46:42 +0200123 if (speed >= XFER_UDMA_0 && speed <= XFER_UDMA_4)
Jaya Kumarf5b2d8b2005-11-09 23:58:16 +0100124 reg |= cs5535_udma_timings[speed - XFER_UDMA_0];
125 else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2)
126 reg |= cs5535_mwdma_timings[speed - XFER_MW_DMA_0];
127 else
128 return;
129
130 wrmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, 0);
131 }
132}
133
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200134/**
135 * cs5535_set_dma_mode - set host controller for DMA mode
136 * @drive: drive
137 * @speed: DMA mode
Jaya Kumarf5b2d8b2005-11-09 23:58:16 +0100138 *
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200139 * Programs the chipset for DMA mode.
Jaya Kumarf5b2d8b2005-11-09 23:58:16 +0100140 */
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200141
142static void cs5535_set_dma_mode(ide_drive_t *drive, const u8 speed)
Jaya Kumarf5b2d8b2005-11-09 23:58:16 +0100143{
Jaya Kumarf5b2d8b2005-11-09 23:58:16 +0100144 cs5535_set_speed(drive, speed);
Jaya Kumarf5b2d8b2005-11-09 23:58:16 +0100145}
146
Bartlomiej Zolnierkiewicz26bcb872007-10-11 23:54:00 +0200147/**
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200148 * cs5535_set_pio_mode - set host controller for PIO mode
Bartlomiej Zolnierkiewicz26bcb872007-10-11 23:54:00 +0200149 * @drive: drive
150 * @pio: PIO mode number
Jaya Kumarf5b2d8b2005-11-09 23:58:16 +0100151 *
152 * A callback from the upper layers for PIO-only tuning.
153 */
Bartlomiej Zolnierkiewicz26bcb872007-10-11 23:54:00 +0200154
155static void cs5535_set_pio_mode(ide_drive_t *drive, const u8 pio)
Jaya Kumarf5b2d8b2005-11-09 23:58:16 +0100156{
Bartlomiej Zolnierkiewiczbc0b0b52007-08-01 23:46:45 +0200157 cs5535_set_speed(drive, XFER_PIO_0 + pio);
Jaya Kumarf5b2d8b2005-11-09 23:58:16 +0100158}
159
Jaya Kumarf5b2d8b2005-11-09 23:58:16 +0100160static int cs5535_dma_check(ide_drive_t *drive)
161{
Jaya Kumarf5b2d8b2005-11-09 23:58:16 +0100162 drive->init_speed = 0;
163
Bartlomiej Zolnierkiewicz29e744d2007-05-10 00:01:09 +0200164 if (ide_tune_dma(drive))
Bartlomiej Zolnierkiewicz3608b5d2007-02-17 02:40:26 +0100165 return 0;
Jaya Kumarf5b2d8b2005-11-09 23:58:16 +0100166
Bartlomiej Zolnierkiewiczbc0b0b52007-08-01 23:46:45 +0200167 if (ide_use_fast_pio(drive))
Bartlomiej Zolnierkiewicz26bcb872007-10-11 23:54:00 +0200168 ide_set_max_pio(drive);
Bartlomiej Zolnierkiewiczd8f44692007-02-17 02:40:25 +0100169
Bartlomiej Zolnierkiewicz3608b5d2007-02-17 02:40:26 +0100170 return -1;
Jaya Kumarf5b2d8b2005-11-09 23:58:16 +0100171}
172
173static u8 __devinit cs5535_cable_detect(struct pci_dev *dev)
174{
175 u8 bit;
176
177 /* if a 80 wire cable was detected */
178 pci_read_config_byte(dev, CS5535_CABLE_DETECT, &bit);
Bartlomiej Zolnierkiewicz49521f92007-07-09 23:17:58 +0200179
180 return (bit & 1) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
Jaya Kumarf5b2d8b2005-11-09 23:58:16 +0100181}
182
183/****
184 * init_hwif_cs5535 - Initialize one ide cannel
185 * @hwif: Channel descriptor
186 *
187 * This gets invoked by the IDE driver once for each channel. It
188 * performs channel-specific pre-initialization before drive probing.
189 *
190 */
191static void __devinit init_hwif_cs5535(ide_hwif_t *hwif)
192{
Jaya Kumarf5b2d8b2005-11-09 23:58:16 +0100193 hwif->autodma = 0;
194
Bartlomiej Zolnierkiewicz26bcb872007-10-11 23:54:00 +0200195 hwif->set_pio_mode = &cs5535_set_pio_mode;
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200196 hwif->set_dma_mode = &cs5535_set_dma_mode;
Bartlomiej Zolnierkiewicz7bda2922007-10-13 17:47:52 +0200197
198 hwif->drives[1].autotune = hwif->drives[0].autotune = 1;
199
200 if (hwif->dma_base == 0)
201 return;
202
Jaya Kumarf5b2d8b2005-11-09 23:58:16 +0100203 hwif->ide_dma_check = &cs5535_dma_check;
204
205 hwif->atapi_dma = 1;
206 hwif->ultra_mask = 0x1F;
207 hwif->mwdma_mask = 0x07;
208
Bartlomiej Zolnierkiewicz49521f92007-07-09 23:17:58 +0200209 hwif->cbl = cs5535_cable_detect(hwif->pci_dev);
Jaya Kumarf5b2d8b2005-11-09 23:58:16 +0100210
211 if (!noautodma)
212 hwif->autodma = 1;
213
Bartlomiej Zolnierkiewicz7bda2922007-10-13 17:47:52 +0200214 hwif->drives[1].autodma = hwif->drives[0].autodma = hwif->autodma;
Jaya Kumarf5b2d8b2005-11-09 23:58:16 +0100215}
216
217static ide_pci_device_t cs5535_chipset __devinitdata = {
218 .name = "CS5535",
219 .init_hwif = init_hwif_cs5535,
Jaya Kumarf5b2d8b2005-11-09 23:58:16 +0100220 .autodma = AUTODMA,
221 .bootable = ON_BOARD,
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200222 .host_flags = IDE_HFLAG_SINGLE | IDE_HFLAG_POST_SET_MODE,
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +0200223 .pio_mask = ATA_PIO4,
Jaya Kumarf5b2d8b2005-11-09 23:58:16 +0100224};
225
226static int __devinit cs5535_init_one(struct pci_dev *dev,
227 const struct pci_device_id *id)
228{
229 return ide_setup_pci_device(dev, &cs5535_chipset);
230}
231
232static struct pci_device_id cs5535_pci_tbl[] =
233{
234 { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_CS5535_IDE, PCI_ANY_ID,
235 PCI_ANY_ID, 0, 0, 0},
236 { 0, },
237};
238
239MODULE_DEVICE_TABLE(pci, cs5535_pci_tbl);
240
241static struct pci_driver driver = {
242 .name = "CS5535_IDE",
243 .id_table = cs5535_pci_tbl,
244 .probe = cs5535_init_one,
245};
246
247static int __init cs5535_ide_init(void)
248{
249 return ide_pci_register_driver(&driver);
250}
251
252module_init(cs5535_ide_init);
253
254MODULE_AUTHOR("AMD");
255MODULE_DESCRIPTION("PCI driver module for AMD/NS CS5535 IDE");
256MODULE_LICENSE("GPL");