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Sascha Hauer1f1846c2010-10-06 10:25:55 +02001/*
2 * drivers/dma/imx-dma.c
3 *
4 * This file contains a driver for the Freescale i.MX DMA engine
5 * found on i.MX1/21/27
6 *
7 * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
8 *
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16#include <linux/init.h>
Axel Linf8de8f42011-08-30 15:08:24 +080017#include <linux/module.h>
Sascha Hauer1f1846c2010-10-06 10:25:55 +020018#include <linux/types.h>
19#include <linux/mm.h>
20#include <linux/interrupt.h>
21#include <linux/spinlock.h>
22#include <linux/device.h>
23#include <linux/dma-mapping.h>
24#include <linux/slab.h>
25#include <linux/platform_device.h>
26#include <linux/dmaengine.h>
Paul Gortmaker5c45ad72011-07-31 16:14:17 -040027#include <linux/module.h>
Sascha Hauer1f1846c2010-10-06 10:25:55 +020028
29#include <asm/irq.h>
30#include <mach/dma-v1.h>
31#include <mach/hardware.h>
32
Russell King - ARM Linuxd2ebfb32012-03-06 22:34:26 +000033#include "dmaengine.h"
34
Sascha Hauer1f1846c2010-10-06 10:25:55 +020035struct imxdma_channel {
36 struct imxdma_engine *imxdma;
37 unsigned int channel;
38 unsigned int imxdma_channel;
39
40 enum dma_slave_buswidth word_size;
41 dma_addr_t per_address;
42 u32 watermark_level;
43 struct dma_chan chan;
44 spinlock_t lock;
45 struct dma_async_tx_descriptor desc;
Sascha Hauer1f1846c2010-10-06 10:25:55 +020046 enum dma_status status;
47 int dma_request;
48 struct scatterlist *sg_list;
49};
50
51#define MAX_DMA_CHANNELS 8
52
53struct imxdma_engine {
54 struct device *dev;
Sascha Hauer1e070a62011-01-12 13:14:37 +010055 struct device_dma_parameters dma_parms;
Sascha Hauer1f1846c2010-10-06 10:25:55 +020056 struct dma_device dma_device;
57 struct imxdma_channel channel[MAX_DMA_CHANNELS];
58};
59
60static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan)
61{
62 return container_of(chan, struct imxdma_channel, chan);
63}
64
65static void imxdma_handle(struct imxdma_channel *imxdmac)
66{
67 if (imxdmac->desc.callback)
68 imxdmac->desc.callback(imxdmac->desc.callback_param);
Russell King - ARM Linuxf7fbce02012-03-06 22:35:07 +000069 dma_cookie_complete(&imxdmac->desc);
Sascha Hauer1f1846c2010-10-06 10:25:55 +020070}
71
72static void imxdma_irq_handler(int channel, void *data)
73{
74 struct imxdma_channel *imxdmac = data;
75
76 imxdmac->status = DMA_SUCCESS;
77 imxdma_handle(imxdmac);
78}
79
80static void imxdma_err_handler(int channel, void *data, int error)
81{
82 struct imxdma_channel *imxdmac = data;
83
84 imxdmac->status = DMA_ERROR;
85 imxdma_handle(imxdmac);
86}
87
88static void imxdma_progression(int channel, void *data,
89 struct scatterlist *sg)
90{
91 struct imxdma_channel *imxdmac = data;
92
93 imxdmac->status = DMA_SUCCESS;
94 imxdma_handle(imxdmac);
95}
96
97static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
98 unsigned long arg)
99{
100 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
101 struct dma_slave_config *dmaengine_cfg = (void *)arg;
102 int ret;
103 unsigned int mode = 0;
104
105 switch (cmd) {
106 case DMA_TERMINATE_ALL:
107 imxdmac->status = DMA_ERROR;
108 imx_dma_disable(imxdmac->imxdma_channel);
109 return 0;
110 case DMA_SLAVE_CONFIG:
Vinod Kouldb8196d2011-10-13 22:34:23 +0530111 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200112 imxdmac->per_address = dmaengine_cfg->src_addr;
113 imxdmac->watermark_level = dmaengine_cfg->src_maxburst;
114 imxdmac->word_size = dmaengine_cfg->src_addr_width;
115 } else {
116 imxdmac->per_address = dmaengine_cfg->dst_addr;
117 imxdmac->watermark_level = dmaengine_cfg->dst_maxburst;
118 imxdmac->word_size = dmaengine_cfg->dst_addr_width;
119 }
120
121 switch (imxdmac->word_size) {
122 case DMA_SLAVE_BUSWIDTH_1_BYTE:
123 mode = IMX_DMA_MEMSIZE_8;
124 break;
125 case DMA_SLAVE_BUSWIDTH_2_BYTES:
126 mode = IMX_DMA_MEMSIZE_16;
127 break;
128 default:
129 case DMA_SLAVE_BUSWIDTH_4_BYTES:
130 mode = IMX_DMA_MEMSIZE_32;
131 break;
132 }
133 ret = imx_dma_config_channel(imxdmac->imxdma_channel,
134 mode | IMX_DMA_TYPE_FIFO,
135 IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
136 imxdmac->dma_request, 1);
137
138 if (ret)
139 return ret;
140
Sascha Hauer6584cb82011-07-06 11:18:33 +0200141 imx_dma_config_burstlen(imxdmac->imxdma_channel,
142 imxdmac->watermark_level * imxdmac->word_size);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200143
144 return 0;
145 default:
146 return -ENOSYS;
147 }
148
149 return -EINVAL;
150}
151
152static enum dma_status imxdma_tx_status(struct dma_chan *chan,
153 dma_cookie_t cookie,
154 struct dma_tx_state *txstate)
155{
Russell King - ARM Linux96a2af42012-03-06 22:35:27 +0000156 return dma_cookie_status(chan, cookie, txstate);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200157}
158
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200159static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx)
160{
161 struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan);
162 dma_cookie_t cookie;
163
164 spin_lock_irq(&imxdmac->lock);
165
Russell King - ARM Linux884485e2012-03-06 22:34:46 +0000166 cookie = dma_cookie_assign(tx);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200167
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200168 spin_unlock_irq(&imxdmac->lock);
169
170 return cookie;
171}
172
173static int imxdma_alloc_chan_resources(struct dma_chan *chan)
174{
175 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
176 struct imx_dma_data *data = chan->private;
177
178 imxdmac->dma_request = data->dma_request;
179
180 dma_async_tx_descriptor_init(&imxdmac->desc, chan);
181 imxdmac->desc.tx_submit = imxdma_tx_submit;
182 /* txd.flags will be overwritten in prep funcs */
183 imxdmac->desc.flags = DMA_CTRL_ACK;
184
185 imxdmac->status = DMA_SUCCESS;
186
187 return 0;
188}
189
190static void imxdma_free_chan_resources(struct dma_chan *chan)
191{
192 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
193
194 imx_dma_disable(imxdmac->imxdma_channel);
195
196 if (imxdmac->sg_list) {
197 kfree(imxdmac->sg_list);
198 imxdmac->sg_list = NULL;
199 }
200}
201
202static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
203 struct dma_chan *chan, struct scatterlist *sgl,
Vinod Kouldb8196d2011-10-13 22:34:23 +0530204 unsigned int sg_len, enum dma_transfer_direction direction,
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200205 unsigned long flags)
206{
207 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
208 struct scatterlist *sg;
209 int i, ret, dma_length = 0;
210 unsigned int dmamode;
211
212 if (imxdmac->status == DMA_IN_PROGRESS)
213 return NULL;
214
215 imxdmac->status = DMA_IN_PROGRESS;
216
217 for_each_sg(sgl, sg, sg_len, i) {
218 dma_length += sg->length;
219 }
220
Vinod Kouldb8196d2011-10-13 22:34:23 +0530221 if (direction == DMA_DEV_TO_MEM)
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200222 dmamode = DMA_MODE_READ;
223 else
224 dmamode = DMA_MODE_WRITE;
225
Sascha Hauerd07102a2011-01-12 14:13:23 +0100226 switch (imxdmac->word_size) {
227 case DMA_SLAVE_BUSWIDTH_4_BYTES:
228 if (sgl->length & 3 || sgl->dma_address & 3)
229 return NULL;
230 break;
231 case DMA_SLAVE_BUSWIDTH_2_BYTES:
232 if (sgl->length & 1 || sgl->dma_address & 1)
233 return NULL;
234 break;
235 case DMA_SLAVE_BUSWIDTH_1_BYTE:
236 break;
237 default:
238 return NULL;
239 }
240
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200241 ret = imx_dma_setup_sg(imxdmac->imxdma_channel, sgl, sg_len,
242 dma_length, imxdmac->per_address, dmamode);
243 if (ret)
244 return NULL;
245
246 return &imxdmac->desc;
247}
248
249static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
250 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
Vinod Kouldb8196d2011-10-13 22:34:23 +0530251 size_t period_len, enum dma_transfer_direction direction)
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200252{
253 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
254 struct imxdma_engine *imxdma = imxdmac->imxdma;
255 int i, ret;
256 unsigned int periods = buf_len / period_len;
257 unsigned int dmamode;
258
259 dev_dbg(imxdma->dev, "%s channel: %d buf_len=%d period_len=%d\n",
260 __func__, imxdmac->channel, buf_len, period_len);
261
262 if (imxdmac->status == DMA_IN_PROGRESS)
263 return NULL;
264 imxdmac->status = DMA_IN_PROGRESS;
265
266 ret = imx_dma_setup_progression_handler(imxdmac->imxdma_channel,
267 imxdma_progression);
268 if (ret) {
269 dev_err(imxdma->dev, "Failed to setup the DMA handler\n");
270 return NULL;
271 }
272
273 if (imxdmac->sg_list)
274 kfree(imxdmac->sg_list);
275
276 imxdmac->sg_list = kcalloc(periods + 1,
277 sizeof(struct scatterlist), GFP_KERNEL);
278 if (!imxdmac->sg_list)
279 return NULL;
280
281 sg_init_table(imxdmac->sg_list, periods);
282
283 for (i = 0; i < periods; i++) {
284 imxdmac->sg_list[i].page_link = 0;
285 imxdmac->sg_list[i].offset = 0;
286 imxdmac->sg_list[i].dma_address = dma_addr;
287 imxdmac->sg_list[i].length = period_len;
288 dma_addr += period_len;
289 }
290
291 /* close the loop */
292 imxdmac->sg_list[periods].offset = 0;
293 imxdmac->sg_list[periods].length = 0;
294 imxdmac->sg_list[periods].page_link =
295 ((unsigned long)imxdmac->sg_list | 0x01) & ~0x02;
296
Vinod Kouldb8196d2011-10-13 22:34:23 +0530297 if (direction == DMA_DEV_TO_MEM)
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200298 dmamode = DMA_MODE_READ;
299 else
300 dmamode = DMA_MODE_WRITE;
301
302 ret = imx_dma_setup_sg(imxdmac->imxdma_channel, imxdmac->sg_list, periods,
303 IMX_DMA_LENGTH_LOOP, imxdmac->per_address, dmamode);
304 if (ret)
305 return NULL;
306
307 return &imxdmac->desc;
308}
309
310static void imxdma_issue_pending(struct dma_chan *chan)
311{
Sascha Hauer5b316872012-01-09 10:32:49 +0100312 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
313
314 if (imxdmac->status == DMA_IN_PROGRESS)
315 imx_dma_enable(imxdmac->imxdma_channel);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200316}
317
318static int __init imxdma_probe(struct platform_device *pdev)
319{
320 struct imxdma_engine *imxdma;
321 int ret, i;
322
323 imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL);
324 if (!imxdma)
325 return -ENOMEM;
326
327 INIT_LIST_HEAD(&imxdma->dma_device.channels);
328
Sascha Hauerf8a356f2011-01-31 11:35:59 +0100329 dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask);
330 dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask);
331
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200332 /* Initialize channel parameters */
333 for (i = 0; i < MAX_DMA_CHANNELS; i++) {
334 struct imxdma_channel *imxdmac = &imxdma->channel[i];
335
336 imxdmac->imxdma_channel = imx_dma_request_by_prio("dmaengine",
337 DMA_PRIO_MEDIUM);
Sascha Hauer8267f162010-10-20 08:37:19 +0200338 if ((int)imxdmac->channel < 0) {
339 ret = -ENODEV;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200340 goto err_init;
Sascha Hauer8267f162010-10-20 08:37:19 +0200341 }
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200342
343 imx_dma_setup_handlers(imxdmac->imxdma_channel,
344 imxdma_irq_handler, imxdma_err_handler, imxdmac);
345
346 imxdmac->imxdma = imxdma;
347 spin_lock_init(&imxdmac->lock);
348
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200349 imxdmac->chan.device = &imxdma->dma_device;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200350 imxdmac->channel = i;
351
352 /* Add the channel to the DMAC list */
353 list_add_tail(&imxdmac->chan.device_node, &imxdma->dma_device.channels);
354 }
355
356 imxdma->dev = &pdev->dev;
357 imxdma->dma_device.dev = &pdev->dev;
358
359 imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources;
360 imxdma->dma_device.device_free_chan_resources = imxdma_free_chan_resources;
361 imxdma->dma_device.device_tx_status = imxdma_tx_status;
362 imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg;
363 imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic;
364 imxdma->dma_device.device_control = imxdma_control;
365 imxdma->dma_device.device_issue_pending = imxdma_issue_pending;
366
367 platform_set_drvdata(pdev, imxdma);
368
Sascha Hauer1e070a62011-01-12 13:14:37 +0100369 imxdma->dma_device.dev->dma_parms = &imxdma->dma_parms;
370 dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff);
371
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200372 ret = dma_async_device_register(&imxdma->dma_device);
373 if (ret) {
374 dev_err(&pdev->dev, "unable to register\n");
375 goto err_init;
376 }
377
378 return 0;
379
380err_init:
Axel Lincbeae412010-11-02 09:12:57 +0800381 while (--i >= 0) {
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200382 struct imxdma_channel *imxdmac = &imxdma->channel[i];
383 imx_dma_free(imxdmac->imxdma_channel);
384 }
385
386 kfree(imxdma);
387 return ret;
388}
389
390static int __exit imxdma_remove(struct platform_device *pdev)
391{
392 struct imxdma_engine *imxdma = platform_get_drvdata(pdev);
393 int i;
394
395 dma_async_device_unregister(&imxdma->dma_device);
396
397 for (i = 0; i < MAX_DMA_CHANNELS; i++) {
398 struct imxdma_channel *imxdmac = &imxdma->channel[i];
399
400 imx_dma_free(imxdmac->imxdma_channel);
401 }
402
403 kfree(imxdma);
404
405 return 0;
406}
407
408static struct platform_driver imxdma_driver = {
409 .driver = {
410 .name = "imx-dma",
411 },
412 .remove = __exit_p(imxdma_remove),
413};
414
415static int __init imxdma_module_init(void)
416{
417 return platform_driver_probe(&imxdma_driver, imxdma_probe);
418}
419subsys_initcall(imxdma_module_init);
420
421MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
422MODULE_DESCRIPTION("i.MX dma driver");
423MODULE_LICENSE("GPL");