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Paul Mundtcad82442006-01-16 22:14:19 -08001menu "Memory management options"
2
Paul Mundt5f8c9902007-05-08 11:55:21 +09003config QUICKLIST
4 def_bool y
5
Paul Mundtcad82442006-01-16 22:14:19 -08006config MMU
7 bool "Support for memory management hardware"
8 depends on !CPU_SH2
9 default y
10 help
11 Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
12 boot on these systems, this option must not be set.
13
14 On other systems (such as the SH-3 and 4) where an MMU exists,
15 turning this off will boot the kernel on these machines with the
16 MMU implicitly switched off.
17
Paul Mundte7f93a32006-09-27 17:19:13 +090018config PAGE_OFFSET
19 hex
20 default "0x80000000" if MMU
21 default "0x00000000"
22
23config MEMORY_START
24 hex "Physical memory start address"
25 default "0x08000000"
26 ---help---
27 Computers built with Hitachi SuperH processors always
28 map the ROM starting at address zero. But the processor
29 does not specify the range that RAM takes.
30
31 The physical memory (RAM) start address will be automatically
32 set to 08000000. Other platforms, such as the Solution Engine
33 boards typically map RAM at 0C000000.
34
35 Tweak this only when porting to a new machine which does not
36 already have a defconfig. Changing it from the known correct
37 value on any of the known systems will only lead to disaster.
38
39config MEMORY_SIZE
40 hex "Physical memory size"
41 default "0x00400000"
42 help
43 This sets the default memory size assumed by your SH kernel. It can
44 be overridden as normal by the 'mem=' argument on the kernel command
45 line. If unsure, consult your board specifications or just leave it
46 as 0x00400000 which was the default value before this became
47 configurable.
48
Paul Mundtcad82442006-01-16 22:14:19 -080049config 32BIT
50 bool "Support 32-bit physical addressing through PMB"
Paul Mundt50f63f22007-06-15 18:30:42 +090051 depends on MMU && (CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785)
Paul Mundtcad82442006-01-16 22:14:19 -080052 default y
53 help
54 If you say Y here, physical addressing will be extended to
55 32-bits through the SH-4A PMB. If this is not set, legacy
56 29-bit physical addressing will be used.
57
Paul Mundt21440cf2006-11-20 14:30:26 +090058config X2TLB
59 bool "Enable extended TLB mode"
Paul Mundtc3af3972007-09-27 18:08:46 +090060 depends on (CPU_SHX2 || CPU_SHX3) && MMU && EXPERIMENTAL
Paul Mundt21440cf2006-11-20 14:30:26 +090061 help
62 Selecting this option will enable the extended mode of the SH-X2
63 TLB. For legacy SH-X behaviour and interoperability, say N. For
64 all of the fun new features and a willingless to submit bug reports,
65 say Y.
66
Paul Mundt19f9a342006-09-27 18:33:49 +090067config VSYSCALL
68 bool "Support vsyscall page"
Paul Mundta09063d2007-11-08 18:54:16 +090069 depends on MMU && (CPU_SH3 || CPU_SH4)
Paul Mundt19f9a342006-09-27 18:33:49 +090070 default y
71 help
72 This will enable support for the kernel mapping a vDSO page
73 in process space, and subsequently handing down the entry point
74 to the libc through the ELF auxiliary vector.
75
76 From the kernel side this is used for the signal trampoline.
77 For systems with an MMU that can afford to give up a page,
78 (the default value) say Y.
79
Paul Mundtb241cb02007-06-06 17:52:19 +090080config NUMA
81 bool "Non Uniform Memory Access (NUMA) Support"
Paul Mundt357d5942007-06-11 15:32:07 +090082 depends on MMU && SYS_SUPPORTS_NUMA && EXPERIMENTAL
Paul Mundtb241cb02007-06-06 17:52:19 +090083 default n
84 help
85 Some SH systems have many various memories scattered around
86 the address space, each with varying latencies. This enables
87 support for these blocks by binding them to nodes and allowing
88 memory policies to be used for prioritizing and controlling
89 allocation behaviour.
90
Paul Mundt01066622007-03-28 16:38:13 +090091config NODES_SHIFT
92 int
Paul Mundt99044942007-08-08 16:45:07 +090093 default "3" if CPU_SUBTYPE_SHX3
Paul Mundt01066622007-03-28 16:38:13 +090094 default "1"
95 depends on NEED_MULTIPLE_NODES
96
97config ARCH_FLATMEM_ENABLE
98 def_bool y
Paul Mundt357d5942007-06-11 15:32:07 +090099 depends on !NUMA
Paul Mundt01066622007-03-28 16:38:13 +0900100
Paul Mundtdfbb9042007-05-23 17:48:36 +0900101config ARCH_SPARSEMEM_ENABLE
102 def_bool y
103 select SPARSEMEM_STATIC
104
105config ARCH_SPARSEMEM_DEFAULT
106 def_bool y
107
Paul Mundt1ce7ddd2007-05-09 13:20:52 +0900108config MAX_ACTIVE_REGIONS
109 int
Paul Mundt7da3b8e2007-08-01 17:52:47 +0900110 default "6" if (CPU_SUBTYPE_SHX3 && SPARSEMEM)
Paul Mundtdc47e9d2007-09-27 16:48:00 +0900111 default "2" if SPARSEMEM && (CPU_SUBTYPE_SH7722 || \
112 CPU_SUBTYPE_SH7785)
Paul Mundt1ce7ddd2007-05-09 13:20:52 +0900113 default "1"
114
Paul Mundt01066622007-03-28 16:38:13 +0900115config ARCH_POPULATES_NODE_MAP
116 def_bool y
117
Paul Mundtdfbb9042007-05-23 17:48:36 +0900118config ARCH_SELECT_MEMORY_MODEL
119 def_bool y
120
Paul Mundt33d63bd2007-06-07 11:32:52 +0900121config ARCH_ENABLE_MEMORY_HOTPLUG
122 def_bool y
123 depends on SPARSEMEM
124
125config ARCH_MEMORY_PROBE
126 def_bool y
127 depends on MEMORY_HOTPLUG
128
Paul Mundtcad82442006-01-16 22:14:19 -0800129choice
Paul Mundt21440cf2006-11-20 14:30:26 +0900130 prompt "Kernel page size"
Paul Mundt4d2cab72007-09-27 10:47:00 +0900131 default PAGE_SIZE_8KB if X2TLB
Paul Mundt21440cf2006-11-20 14:30:26 +0900132 default PAGE_SIZE_4KB
133
134config PAGE_SIZE_4KB
135 bool "4kB"
Paul Mundt4d2cab72007-09-27 10:47:00 +0900136 depends on !X2TLB
Paul Mundt21440cf2006-11-20 14:30:26 +0900137 help
138 This is the default page size used by all SuperH CPUs.
139
140config PAGE_SIZE_8KB
141 bool "8kB"
Paul Mundt4d2cab72007-09-27 10:47:00 +0900142 depends on X2TLB
Paul Mundt21440cf2006-11-20 14:30:26 +0900143 help
144 This enables 8kB pages as supported by SH-X2 and later MMUs.
145
146config PAGE_SIZE_64KB
147 bool "64kB"
Paul Mundt4d2cab72007-09-27 10:47:00 +0900148 depends on CPU_SH4
Paul Mundt21440cf2006-11-20 14:30:26 +0900149 help
150 This enables support for 64kB pages, possible on all SH-4
Paul Mundt4d2cab72007-09-27 10:47:00 +0900151 CPUs and later.
Paul Mundt21440cf2006-11-20 14:30:26 +0900152
153endchoice
154
155choice
Paul Mundtcad82442006-01-16 22:14:19 -0800156 prompt "HugeTLB page size"
157 depends on HUGETLB_PAGE && CPU_SH4 && MMU
158 default HUGETLB_PAGE_SIZE_64K
159
160config HUGETLB_PAGE_SIZE_64K
Paul Mundt21440cf2006-11-20 14:30:26 +0900161 bool "64kB"
162
163config HUGETLB_PAGE_SIZE_256K
164 bool "256kB"
165 depends on X2TLB
Paul Mundtcad82442006-01-16 22:14:19 -0800166
167config HUGETLB_PAGE_SIZE_1MB
168 bool "1MB"
169
Paul Mundt21440cf2006-11-20 14:30:26 +0900170config HUGETLB_PAGE_SIZE_4MB
171 bool "4MB"
172 depends on X2TLB
173
174config HUGETLB_PAGE_SIZE_64MB
175 bool "64MB"
176 depends on X2TLB
177
Paul Mundta09063d2007-11-08 18:54:16 +0900178config HUGETLB_PAGE_SIZE_512MB
179 bool "512MB"
180 depends on CPU_SH5
181
Paul Mundtcad82442006-01-16 22:14:19 -0800182endchoice
183
184source "mm/Kconfig"
185
186endmenu
187
188menu "Cache configuration"
189
190config SH7705_CACHE_32KB
191 bool "Enable 32KB cache size for SH7705"
192 depends on CPU_SUBTYPE_SH7705
193 default y
194
195config SH_DIRECT_MAPPED
196 bool "Use direct-mapped caching"
197 default n
198 help
199 Selecting this option will configure the caches to be direct-mapped,
200 even if the cache supports a 2 or 4-way mode. This is useful primarily
201 for debugging on platforms with 2 and 4-way caches (SH7750R/SH7751R,
202 SH4-202, SH4-501, etc.)
203
204 Turn this option off for platforms that do not have a direct-mapped
205 cache, and you have no need to run the caches in such a configuration.
206
Paul Mundte7bd34a2007-07-31 17:07:28 +0900207choice
208 prompt "Cache mode"
Paul Mundta09063d2007-11-08 18:54:16 +0900209 default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4 || CPU_SH5
Paul Mundte7bd34a2007-07-31 17:07:28 +0900210 default CACHE_WRITETHROUGH if (CPU_SH2 && !CPU_SH2A)
211
212config CACHE_WRITEBACK
213 bool "Write-back"
Paul Mundta09063d2007-11-08 18:54:16 +0900214 depends on CPU_SH2A || CPU_SH3 || CPU_SH4 || CPU_SH5
Paul Mundte7bd34a2007-07-31 17:07:28 +0900215
216config CACHE_WRITETHROUGH
217 bool "Write-through"
Paul Mundtcad82442006-01-16 22:14:19 -0800218 help
219 Selecting this option will configure the caches in write-through
220 mode, as opposed to the default write-back configuration.
221
222 Since there's sill some aliasing issues on SH-4, this option will
223 unfortunately still require the majority of flushing functions to
224 be implemented to deal with aliasing.
225
226 If unsure, say N.
227
Paul Mundte7bd34a2007-07-31 17:07:28 +0900228config CACHE_OFF
229 bool "Off"
230
231endchoice
232
Paul Mundtcad82442006-01-16 22:14:19 -0800233endmenu