blob: b79ced8f3c61e832f76f451576444ce0e5b89226 [file] [log] [blame]
Eric Anholt673a3942008-07-30 12:06:12 -07001/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28#include "drmP.h"
29#include "drm.h"
30#include "i915_drm.h"
31#include "i915_drv.h"
32#include <linux/swap.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080033#include <linux/pci.h>
Eric Anholt673a3942008-07-30 12:06:12 -070034
Eric Anholt28dfe522008-11-13 15:00:55 -080035#define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
36
Keith Packardc0d90822008-11-20 23:11:08 -080037static void
38i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj,
39 uint32_t read_domains,
40 uint32_t write_domain);
Eric Anholte47c68e2008-11-14 13:35:19 -080041static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
42static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
43static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
Eric Anholte47c68e2008-11-14 13:35:19 -080044static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
45 int write);
46static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
47 uint64_t offset,
48 uint64_t size);
49static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
Eric Anholt673a3942008-07-30 12:06:12 -070050static int i915_gem_object_get_page_list(struct drm_gem_object *obj);
51static void i915_gem_object_free_page_list(struct drm_gem_object *obj);
52static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
Jesse Barnesde151cf2008-11-12 10:03:55 -080053static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
54 unsigned alignment);
Jesse Barnes0f973f22009-01-26 17:10:45 -080055static int i915_gem_object_get_fence_reg(struct drm_gem_object *obj, bool write);
Jesse Barnesde151cf2008-11-12 10:03:55 -080056static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
57static int i915_gem_evict_something(struct drm_device *dev);
Dave Airlie71acb5e2008-12-30 20:31:46 +100058static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
59 struct drm_i915_gem_pwrite *args,
60 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -070061
Jesse Barnes79e53942008-11-07 14:24:08 -080062int i915_gem_do_init(struct drm_device *dev, unsigned long start,
63 unsigned long end)
64{
65 drm_i915_private_t *dev_priv = dev->dev_private;
66
67 if (start >= end ||
68 (start & (PAGE_SIZE - 1)) != 0 ||
69 (end & (PAGE_SIZE - 1)) != 0) {
70 return -EINVAL;
71 }
72
73 drm_mm_init(&dev_priv->mm.gtt_space, start,
74 end - start);
75
76 dev->gtt_total = (uint32_t) (end - start);
77
78 return 0;
79}
Keith Packard6dbe2772008-10-14 21:41:13 -070080
Eric Anholt673a3942008-07-30 12:06:12 -070081int
82i915_gem_init_ioctl(struct drm_device *dev, void *data,
83 struct drm_file *file_priv)
84{
Eric Anholt673a3942008-07-30 12:06:12 -070085 struct drm_i915_gem_init *args = data;
Jesse Barnes79e53942008-11-07 14:24:08 -080086 int ret;
Eric Anholt673a3942008-07-30 12:06:12 -070087
88 mutex_lock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -080089 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
Eric Anholt673a3942008-07-30 12:06:12 -070090 mutex_unlock(&dev->struct_mutex);
91
Jesse Barnes79e53942008-11-07 14:24:08 -080092 return ret;
Eric Anholt673a3942008-07-30 12:06:12 -070093}
94
Eric Anholt5a125c32008-10-22 21:40:13 -070095int
96i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
97 struct drm_file *file_priv)
98{
Eric Anholt5a125c32008-10-22 21:40:13 -070099 struct drm_i915_gem_get_aperture *args = data;
Eric Anholt5a125c32008-10-22 21:40:13 -0700100
101 if (!(dev->driver->driver_features & DRIVER_GEM))
102 return -ENODEV;
103
104 args->aper_size = dev->gtt_total;
Keith Packard2678d9d2008-11-20 22:54:54 -0800105 args->aper_available_size = (args->aper_size -
106 atomic_read(&dev->pin_memory));
Eric Anholt5a125c32008-10-22 21:40:13 -0700107
108 return 0;
109}
110
Eric Anholt673a3942008-07-30 12:06:12 -0700111
112/**
113 * Creates a new mm object and returns a handle to it.
114 */
115int
116i915_gem_create_ioctl(struct drm_device *dev, void *data,
117 struct drm_file *file_priv)
118{
119 struct drm_i915_gem_create *args = data;
120 struct drm_gem_object *obj;
121 int handle, ret;
122
123 args->size = roundup(args->size, PAGE_SIZE);
124
125 /* Allocate the new object */
126 obj = drm_gem_object_alloc(dev, args->size);
127 if (obj == NULL)
128 return -ENOMEM;
129
130 ret = drm_gem_handle_create(file_priv, obj, &handle);
131 mutex_lock(&dev->struct_mutex);
132 drm_gem_object_handle_unreference(obj);
133 mutex_unlock(&dev->struct_mutex);
134
135 if (ret)
136 return ret;
137
138 args->handle = handle;
139
140 return 0;
141}
142
143/**
144 * Reads data from the object referenced by handle.
145 *
146 * On error, the contents of *data are undefined.
147 */
148int
149i915_gem_pread_ioctl(struct drm_device *dev, void *data,
150 struct drm_file *file_priv)
151{
152 struct drm_i915_gem_pread *args = data;
153 struct drm_gem_object *obj;
154 struct drm_i915_gem_object *obj_priv;
155 ssize_t read;
156 loff_t offset;
157 int ret;
158
159 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
160 if (obj == NULL)
161 return -EBADF;
162 obj_priv = obj->driver_private;
163
164 /* Bounds check source.
165 *
166 * XXX: This could use review for overflow issues...
167 */
168 if (args->offset > obj->size || args->size > obj->size ||
169 args->offset + args->size > obj->size) {
170 drm_gem_object_unreference(obj);
171 return -EINVAL;
172 }
173
174 mutex_lock(&dev->struct_mutex);
175
Eric Anholte47c68e2008-11-14 13:35:19 -0800176 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
177 args->size);
Eric Anholt673a3942008-07-30 12:06:12 -0700178 if (ret != 0) {
179 drm_gem_object_unreference(obj);
180 mutex_unlock(&dev->struct_mutex);
Dave Airliee7d22bc2008-10-07 13:40:36 +1000181 return ret;
Eric Anholt673a3942008-07-30 12:06:12 -0700182 }
183
184 offset = args->offset;
185
186 read = vfs_read(obj->filp, (char __user *)(uintptr_t)args->data_ptr,
187 args->size, &offset);
188 if (read != args->size) {
189 drm_gem_object_unreference(obj);
190 mutex_unlock(&dev->struct_mutex);
191 if (read < 0)
192 return read;
193 else
194 return -EINVAL;
195 }
196
197 drm_gem_object_unreference(obj);
198 mutex_unlock(&dev->struct_mutex);
199
200 return 0;
201}
202
Keith Packard0839ccb2008-10-30 19:38:48 -0700203/* This is the fast write path which cannot handle
204 * page faults in the source data
Linus Torvalds9b7530cc2008-10-20 14:16:43 -0700205 */
Linus Torvalds9b7530cc2008-10-20 14:16:43 -0700206
Keith Packard0839ccb2008-10-30 19:38:48 -0700207static inline int
208fast_user_write(struct io_mapping *mapping,
209 loff_t page_base, int page_offset,
210 char __user *user_data,
211 int length)
212{
213 char *vaddr_atomic;
214 unsigned long unwritten;
215
216 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
217 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
218 user_data, length);
219 io_mapping_unmap_atomic(vaddr_atomic);
220 if (unwritten)
221 return -EFAULT;
Linus Torvalds9b7530cc2008-10-20 14:16:43 -0700222 return 0;
Keith Packard0839ccb2008-10-30 19:38:48 -0700223}
224
225/* Here's the write path which can sleep for
226 * page faults
227 */
228
229static inline int
230slow_user_write(struct io_mapping *mapping,
231 loff_t page_base, int page_offset,
232 char __user *user_data,
233 int length)
234{
235 char __iomem *vaddr;
236 unsigned long unwritten;
237
238 vaddr = io_mapping_map_wc(mapping, page_base);
239 if (vaddr == NULL)
240 return -EFAULT;
241 unwritten = __copy_from_user(vaddr + page_offset,
242 user_data, length);
243 io_mapping_unmap(vaddr);
244 if (unwritten)
245 return -EFAULT;
246 return 0;
Linus Torvalds9b7530cc2008-10-20 14:16:43 -0700247}
248
Eric Anholt673a3942008-07-30 12:06:12 -0700249static int
250i915_gem_gtt_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
251 struct drm_i915_gem_pwrite *args,
252 struct drm_file *file_priv)
253{
254 struct drm_i915_gem_object *obj_priv = obj->driver_private;
Keith Packard0839ccb2008-10-30 19:38:48 -0700255 drm_i915_private_t *dev_priv = dev->dev_private;
Eric Anholt673a3942008-07-30 12:06:12 -0700256 ssize_t remain;
Keith Packard0839ccb2008-10-30 19:38:48 -0700257 loff_t offset, page_base;
Eric Anholt673a3942008-07-30 12:06:12 -0700258 char __user *user_data;
Keith Packard0839ccb2008-10-30 19:38:48 -0700259 int page_offset, page_length;
260 int ret;
Eric Anholt673a3942008-07-30 12:06:12 -0700261
262 user_data = (char __user *) (uintptr_t) args->data_ptr;
263 remain = args->size;
264 if (!access_ok(VERIFY_READ, user_data, remain))
265 return -EFAULT;
266
267
268 mutex_lock(&dev->struct_mutex);
269 ret = i915_gem_object_pin(obj, 0);
270 if (ret) {
271 mutex_unlock(&dev->struct_mutex);
272 return ret;
273 }
Eric Anholt2ef7eea2008-11-10 10:53:25 -0800274 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
Eric Anholt673a3942008-07-30 12:06:12 -0700275 if (ret)
276 goto fail;
277
278 obj_priv = obj->driver_private;
279 offset = obj_priv->gtt_offset + args->offset;
280 obj_priv->dirty = 1;
281
282 while (remain > 0) {
283 /* Operation in this page
284 *
Keith Packard0839ccb2008-10-30 19:38:48 -0700285 * page_base = page offset within aperture
286 * page_offset = offset within page
287 * page_length = bytes to copy for this page
Eric Anholt673a3942008-07-30 12:06:12 -0700288 */
Keith Packard0839ccb2008-10-30 19:38:48 -0700289 page_base = (offset & ~(PAGE_SIZE-1));
290 page_offset = offset & (PAGE_SIZE-1);
291 page_length = remain;
292 if ((page_offset + remain) > PAGE_SIZE)
293 page_length = PAGE_SIZE - page_offset;
Eric Anholt673a3942008-07-30 12:06:12 -0700294
Keith Packard0839ccb2008-10-30 19:38:48 -0700295 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
296 page_offset, user_data, page_length);
Eric Anholt673a3942008-07-30 12:06:12 -0700297
Keith Packard0839ccb2008-10-30 19:38:48 -0700298 /* If we get a fault while copying data, then (presumably) our
299 * source page isn't available. In this case, use the
300 * non-atomic function
301 */
302 if (ret) {
303 ret = slow_user_write (dev_priv->mm.gtt_mapping,
304 page_base, page_offset,
305 user_data, page_length);
306 if (ret)
Eric Anholt673a3942008-07-30 12:06:12 -0700307 goto fail;
Eric Anholt673a3942008-07-30 12:06:12 -0700308 }
309
Keith Packard0839ccb2008-10-30 19:38:48 -0700310 remain -= page_length;
311 user_data += page_length;
312 offset += page_length;
Eric Anholt673a3942008-07-30 12:06:12 -0700313 }
Eric Anholt673a3942008-07-30 12:06:12 -0700314
315fail:
316 i915_gem_object_unpin(obj);
317 mutex_unlock(&dev->struct_mutex);
318
319 return ret;
320}
321
Eric Anholt3043c602008-10-02 12:24:47 -0700322static int
Eric Anholt673a3942008-07-30 12:06:12 -0700323i915_gem_shmem_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
324 struct drm_i915_gem_pwrite *args,
325 struct drm_file *file_priv)
326{
327 int ret;
328 loff_t offset;
329 ssize_t written;
330
331 mutex_lock(&dev->struct_mutex);
332
Eric Anholte47c68e2008-11-14 13:35:19 -0800333 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
Eric Anholt673a3942008-07-30 12:06:12 -0700334 if (ret) {
335 mutex_unlock(&dev->struct_mutex);
336 return ret;
337 }
338
339 offset = args->offset;
340
341 written = vfs_write(obj->filp,
342 (char __user *)(uintptr_t) args->data_ptr,
343 args->size, &offset);
344 if (written != args->size) {
345 mutex_unlock(&dev->struct_mutex);
346 if (written < 0)
347 return written;
348 else
349 return -EINVAL;
350 }
351
352 mutex_unlock(&dev->struct_mutex);
353
354 return 0;
355}
356
357/**
358 * Writes data to the object referenced by handle.
359 *
360 * On error, the contents of the buffer that were to be modified are undefined.
361 */
362int
363i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
364 struct drm_file *file_priv)
365{
366 struct drm_i915_gem_pwrite *args = data;
367 struct drm_gem_object *obj;
368 struct drm_i915_gem_object *obj_priv;
369 int ret = 0;
370
371 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
372 if (obj == NULL)
373 return -EBADF;
374 obj_priv = obj->driver_private;
375
376 /* Bounds check destination.
377 *
378 * XXX: This could use review for overflow issues...
379 */
380 if (args->offset > obj->size || args->size > obj->size ||
381 args->offset + args->size > obj->size) {
382 drm_gem_object_unreference(obj);
383 return -EINVAL;
384 }
385
386 /* We can only do the GTT pwrite on untiled buffers, as otherwise
387 * it would end up going through the fenced access, and we'll get
388 * different detiling behavior between reading and writing.
389 * pread/pwrite currently are reading and writing from the CPU
390 * perspective, requiring manual detiling by the client.
391 */
Dave Airlie71acb5e2008-12-30 20:31:46 +1000392 if (obj_priv->phys_obj)
393 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
394 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
395 dev->gtt_total != 0)
Eric Anholt673a3942008-07-30 12:06:12 -0700396 ret = i915_gem_gtt_pwrite(dev, obj, args, file_priv);
397 else
398 ret = i915_gem_shmem_pwrite(dev, obj, args, file_priv);
399
400#if WATCH_PWRITE
401 if (ret)
402 DRM_INFO("pwrite failed %d\n", ret);
403#endif
404
405 drm_gem_object_unreference(obj);
406
407 return ret;
408}
409
410/**
Eric Anholt2ef7eea2008-11-10 10:53:25 -0800411 * Called when user space prepares to use an object with the CPU, either
412 * through the mmap ioctl's mapping or a GTT mapping.
Eric Anholt673a3942008-07-30 12:06:12 -0700413 */
414int
415i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
416 struct drm_file *file_priv)
417{
418 struct drm_i915_gem_set_domain *args = data;
419 struct drm_gem_object *obj;
Eric Anholt2ef7eea2008-11-10 10:53:25 -0800420 uint32_t read_domains = args->read_domains;
421 uint32_t write_domain = args->write_domain;
Eric Anholt673a3942008-07-30 12:06:12 -0700422 int ret;
423
424 if (!(dev->driver->driver_features & DRIVER_GEM))
425 return -ENODEV;
426
Eric Anholt2ef7eea2008-11-10 10:53:25 -0800427 /* Only handle setting domains to types used by the CPU. */
428 if (write_domain & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
429 return -EINVAL;
430
431 if (read_domains & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
432 return -EINVAL;
433
434 /* Having something in the write domain implies it's in the read
435 * domain, and only that read domain. Enforce that in the request.
436 */
437 if (write_domain != 0 && read_domains != write_domain)
438 return -EINVAL;
439
Eric Anholt673a3942008-07-30 12:06:12 -0700440 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
441 if (obj == NULL)
442 return -EBADF;
443
444 mutex_lock(&dev->struct_mutex);
445#if WATCH_BUF
446 DRM_INFO("set_domain_ioctl %p(%d), %08x %08x\n",
Eric Anholt2ef7eea2008-11-10 10:53:25 -0800447 obj, obj->size, read_domains, write_domain);
Eric Anholt673a3942008-07-30 12:06:12 -0700448#endif
Eric Anholt2ef7eea2008-11-10 10:53:25 -0800449 if (read_domains & I915_GEM_DOMAIN_GTT) {
450 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
Eric Anholt02354392008-11-26 13:58:13 -0800451
452 /* Silently promote "you're not bound, there was nothing to do"
453 * to success, since the client was just asking us to
454 * make sure everything was done.
455 */
456 if (ret == -EINVAL)
457 ret = 0;
Eric Anholt2ef7eea2008-11-10 10:53:25 -0800458 } else {
Eric Anholte47c68e2008-11-14 13:35:19 -0800459 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
Eric Anholt2ef7eea2008-11-10 10:53:25 -0800460 }
461
Eric Anholt673a3942008-07-30 12:06:12 -0700462 drm_gem_object_unreference(obj);
463 mutex_unlock(&dev->struct_mutex);
464 return ret;
465}
466
467/**
468 * Called when user space has done writes to this buffer
469 */
470int
471i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
472 struct drm_file *file_priv)
473{
474 struct drm_i915_gem_sw_finish *args = data;
475 struct drm_gem_object *obj;
476 struct drm_i915_gem_object *obj_priv;
477 int ret = 0;
478
479 if (!(dev->driver->driver_features & DRIVER_GEM))
480 return -ENODEV;
481
482 mutex_lock(&dev->struct_mutex);
483 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
484 if (obj == NULL) {
485 mutex_unlock(&dev->struct_mutex);
486 return -EBADF;
487 }
488
489#if WATCH_BUF
490 DRM_INFO("%s: sw_finish %d (%p %d)\n",
491 __func__, args->handle, obj, obj->size);
492#endif
493 obj_priv = obj->driver_private;
494
495 /* Pinned buffers may be scanout, so flush the cache */
Eric Anholte47c68e2008-11-14 13:35:19 -0800496 if (obj_priv->pin_count)
497 i915_gem_object_flush_cpu_write_domain(obj);
498
Eric Anholt673a3942008-07-30 12:06:12 -0700499 drm_gem_object_unreference(obj);
500 mutex_unlock(&dev->struct_mutex);
501 return ret;
502}
503
504/**
505 * Maps the contents of an object, returning the address it is mapped
506 * into.
507 *
508 * While the mapping holds a reference on the contents of the object, it doesn't
509 * imply a ref on the object itself.
510 */
511int
512i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
513 struct drm_file *file_priv)
514{
515 struct drm_i915_gem_mmap *args = data;
516 struct drm_gem_object *obj;
517 loff_t offset;
518 unsigned long addr;
519
520 if (!(dev->driver->driver_features & DRIVER_GEM))
521 return -ENODEV;
522
523 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
524 if (obj == NULL)
525 return -EBADF;
526
527 offset = args->offset;
528
529 down_write(&current->mm->mmap_sem);
530 addr = do_mmap(obj->filp, 0, args->size,
531 PROT_READ | PROT_WRITE, MAP_SHARED,
532 args->offset);
533 up_write(&current->mm->mmap_sem);
534 mutex_lock(&dev->struct_mutex);
535 drm_gem_object_unreference(obj);
536 mutex_unlock(&dev->struct_mutex);
537 if (IS_ERR((void *)addr))
538 return addr;
539
540 args->addr_ptr = (uint64_t) addr;
541
542 return 0;
543}
544
Jesse Barnesde151cf2008-11-12 10:03:55 -0800545/**
546 * i915_gem_fault - fault a page into the GTT
547 * vma: VMA in question
548 * vmf: fault info
549 *
550 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
551 * from userspace. The fault handler takes care of binding the object to
552 * the GTT (if needed), allocating and programming a fence register (again,
553 * only if needed based on whether the old reg is still valid or the object
554 * is tiled) and inserting a new PTE into the faulting process.
555 *
556 * Note that the faulting process may involve evicting existing objects
557 * from the GTT and/or fence registers to make room. So performance may
558 * suffer if the GTT working set is large or there are few fence registers
559 * left.
560 */
561int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
562{
563 struct drm_gem_object *obj = vma->vm_private_data;
564 struct drm_device *dev = obj->dev;
565 struct drm_i915_private *dev_priv = dev->dev_private;
566 struct drm_i915_gem_object *obj_priv = obj->driver_private;
567 pgoff_t page_offset;
568 unsigned long pfn;
569 int ret = 0;
Jesse Barnes0f973f22009-01-26 17:10:45 -0800570 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
Jesse Barnesde151cf2008-11-12 10:03:55 -0800571
572 /* We don't use vmf->pgoff since that has the fake offset */
573 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
574 PAGE_SHIFT;
575
576 /* Now bind it into the GTT if needed */
577 mutex_lock(&dev->struct_mutex);
578 if (!obj_priv->gtt_space) {
579 ret = i915_gem_object_bind_to_gtt(obj, obj_priv->gtt_alignment);
580 if (ret) {
581 mutex_unlock(&dev->struct_mutex);
582 return VM_FAULT_SIGBUS;
583 }
584 list_add(&obj_priv->list, &dev_priv->mm.inactive_list);
585 }
586
587 /* Need a new fence register? */
588 if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
Eric Anholtd9ddcb92009-01-27 10:33:49 -0800589 obj_priv->tiling_mode != I915_TILING_NONE) {
Jesse Barnes0f973f22009-01-26 17:10:45 -0800590 ret = i915_gem_object_get_fence_reg(obj, write);
Chris Wilson7d8d58b2009-02-04 14:15:10 +0000591 if (ret) {
592 mutex_unlock(&dev->struct_mutex);
Eric Anholtd9ddcb92009-01-27 10:33:49 -0800593 return VM_FAULT_SIGBUS;
Chris Wilson7d8d58b2009-02-04 14:15:10 +0000594 }
Eric Anholtd9ddcb92009-01-27 10:33:49 -0800595 }
Jesse Barnesde151cf2008-11-12 10:03:55 -0800596
597 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
598 page_offset;
599
600 /* Finally, remap it using the new GTT offset */
601 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
602
603 mutex_unlock(&dev->struct_mutex);
604
605 switch (ret) {
606 case -ENOMEM:
607 case -EAGAIN:
608 return VM_FAULT_OOM;
609 case -EFAULT:
610 case -EBUSY:
611 DRM_ERROR("can't insert pfn?? fault or busy...\n");
612 return VM_FAULT_SIGBUS;
613 default:
614 return VM_FAULT_NOPAGE;
615 }
616}
617
618/**
619 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
620 * @obj: obj in question
621 *
622 * GEM memory mapping works by handing back to userspace a fake mmap offset
623 * it can use in a subsequent mmap(2) call. The DRM core code then looks
624 * up the object based on the offset and sets up the various memory mapping
625 * structures.
626 *
627 * This routine allocates and attaches a fake offset for @obj.
628 */
629static int
630i915_gem_create_mmap_offset(struct drm_gem_object *obj)
631{
632 struct drm_device *dev = obj->dev;
633 struct drm_gem_mm *mm = dev->mm_private;
634 struct drm_i915_gem_object *obj_priv = obj->driver_private;
635 struct drm_map_list *list;
636 struct drm_map *map;
637 int ret = 0;
638
639 /* Set the object up for mmap'ing */
640 list = &obj->map_list;
641 list->map = drm_calloc(1, sizeof(struct drm_map_list),
642 DRM_MEM_DRIVER);
643 if (!list->map)
644 return -ENOMEM;
645
646 map = list->map;
647 map->type = _DRM_GEM;
648 map->size = obj->size;
649 map->handle = obj;
650
651 /* Get a DRM GEM mmap offset allocated... */
652 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
653 obj->size / PAGE_SIZE, 0, 0);
654 if (!list->file_offset_node) {
655 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
656 ret = -ENOMEM;
657 goto out_free_list;
658 }
659
660 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
661 obj->size / PAGE_SIZE, 0);
662 if (!list->file_offset_node) {
663 ret = -ENOMEM;
664 goto out_free_list;
665 }
666
667 list->hash.key = list->file_offset_node->start;
668 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
669 DRM_ERROR("failed to add to map hash\n");
670 goto out_free_mm;
671 }
672
673 /* By now we should be all set, any drm_mmap request on the offset
674 * below will get to our mmap & fault handler */
675 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
676
677 return 0;
678
679out_free_mm:
680 drm_mm_put_block(list->file_offset_node);
681out_free_list:
682 drm_free(list->map, sizeof(struct drm_map_list), DRM_MEM_DRIVER);
683
684 return ret;
685}
686
687/**
688 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
689 * @obj: object to check
690 *
691 * Return the required GTT alignment for an object, taking into account
692 * potential fence register mapping if needed.
693 */
694static uint32_t
695i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
696{
697 struct drm_device *dev = obj->dev;
698 struct drm_i915_gem_object *obj_priv = obj->driver_private;
699 int start, i;
700
701 /*
702 * Minimum alignment is 4k (GTT page size), but might be greater
703 * if a fence register is needed for the object.
704 */
705 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
706 return 4096;
707
708 /*
709 * Previous chips need to be aligned to the size of the smallest
710 * fence register that can contain the object.
711 */
712 if (IS_I9XX(dev))
713 start = 1024*1024;
714 else
715 start = 512*1024;
716
717 for (i = start; i < obj->size; i <<= 1)
718 ;
719
720 return i;
721}
722
723/**
724 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
725 * @dev: DRM device
726 * @data: GTT mapping ioctl data
727 * @file_priv: GEM object info
728 *
729 * Simply returns the fake offset to userspace so it can mmap it.
730 * The mmap call will end up in drm_gem_mmap(), which will set things
731 * up so we can get faults in the handler above.
732 *
733 * The fault handler will take care of binding the object into the GTT
734 * (since it may have been evicted to make room for something), allocating
735 * a fence register, and mapping the appropriate aperture address into
736 * userspace.
737 */
738int
739i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
740 struct drm_file *file_priv)
741{
742 struct drm_i915_gem_mmap_gtt *args = data;
743 struct drm_i915_private *dev_priv = dev->dev_private;
744 struct drm_gem_object *obj;
745 struct drm_i915_gem_object *obj_priv;
746 int ret;
747
748 if (!(dev->driver->driver_features & DRIVER_GEM))
749 return -ENODEV;
750
751 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
752 if (obj == NULL)
753 return -EBADF;
754
755 mutex_lock(&dev->struct_mutex);
756
757 obj_priv = obj->driver_private;
758
759 if (!obj_priv->mmap_offset) {
760 ret = i915_gem_create_mmap_offset(obj);
761 if (ret)
762 return ret;
763 }
764
765 args->offset = obj_priv->mmap_offset;
766
767 obj_priv->gtt_alignment = i915_gem_get_gtt_alignment(obj);
768
769 /* Make sure the alignment is correct for fence regs etc */
770 if (obj_priv->agp_mem &&
771 (obj_priv->gtt_offset & (obj_priv->gtt_alignment - 1))) {
772 drm_gem_object_unreference(obj);
773 mutex_unlock(&dev->struct_mutex);
774 return -EINVAL;
775 }
776
777 /*
778 * Pull it into the GTT so that we have a page list (makes the
779 * initial fault faster and any subsequent flushing possible).
780 */
781 if (!obj_priv->agp_mem) {
782 ret = i915_gem_object_bind_to_gtt(obj, obj_priv->gtt_alignment);
783 if (ret) {
784 drm_gem_object_unreference(obj);
785 mutex_unlock(&dev->struct_mutex);
786 return ret;
787 }
788 list_add(&obj_priv->list, &dev_priv->mm.inactive_list);
789 }
790
791 drm_gem_object_unreference(obj);
792 mutex_unlock(&dev->struct_mutex);
793
794 return 0;
795}
796
Eric Anholt673a3942008-07-30 12:06:12 -0700797static void
798i915_gem_object_free_page_list(struct drm_gem_object *obj)
799{
800 struct drm_i915_gem_object *obj_priv = obj->driver_private;
801 int page_count = obj->size / PAGE_SIZE;
802 int i;
803
804 if (obj_priv->page_list == NULL)
805 return;
806
807
808 for (i = 0; i < page_count; i++)
809 if (obj_priv->page_list[i] != NULL) {
810 if (obj_priv->dirty)
811 set_page_dirty(obj_priv->page_list[i]);
812 mark_page_accessed(obj_priv->page_list[i]);
813 page_cache_release(obj_priv->page_list[i]);
814 }
815 obj_priv->dirty = 0;
816
817 drm_free(obj_priv->page_list,
818 page_count * sizeof(struct page *),
819 DRM_MEM_DRIVER);
820 obj_priv->page_list = NULL;
821}
822
823static void
Eric Anholtce44b0e2008-11-06 16:00:31 -0800824i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
Eric Anholt673a3942008-07-30 12:06:12 -0700825{
826 struct drm_device *dev = obj->dev;
827 drm_i915_private_t *dev_priv = dev->dev_private;
828 struct drm_i915_gem_object *obj_priv = obj->driver_private;
829
830 /* Add a reference if we're newly entering the active list. */
831 if (!obj_priv->active) {
832 drm_gem_object_reference(obj);
833 obj_priv->active = 1;
834 }
835 /* Move from whatever list we were on to the tail of execution. */
836 list_move_tail(&obj_priv->list,
837 &dev_priv->mm.active_list);
Eric Anholtce44b0e2008-11-06 16:00:31 -0800838 obj_priv->last_rendering_seqno = seqno;
Eric Anholt673a3942008-07-30 12:06:12 -0700839}
840
Eric Anholtce44b0e2008-11-06 16:00:31 -0800841static void
842i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
843{
844 struct drm_device *dev = obj->dev;
845 drm_i915_private_t *dev_priv = dev->dev_private;
846 struct drm_i915_gem_object *obj_priv = obj->driver_private;
847
848 BUG_ON(!obj_priv->active);
849 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
850 obj_priv->last_rendering_seqno = 0;
851}
Eric Anholt673a3942008-07-30 12:06:12 -0700852
853static void
854i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
855{
856 struct drm_device *dev = obj->dev;
857 drm_i915_private_t *dev_priv = dev->dev_private;
858 struct drm_i915_gem_object *obj_priv = obj->driver_private;
859
860 i915_verify_inactive(dev, __FILE__, __LINE__);
861 if (obj_priv->pin_count != 0)
862 list_del_init(&obj_priv->list);
863 else
864 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
865
Eric Anholtce44b0e2008-11-06 16:00:31 -0800866 obj_priv->last_rendering_seqno = 0;
Eric Anholt673a3942008-07-30 12:06:12 -0700867 if (obj_priv->active) {
868 obj_priv->active = 0;
869 drm_gem_object_unreference(obj);
870 }
871 i915_verify_inactive(dev, __FILE__, __LINE__);
872}
873
874/**
875 * Creates a new sequence number, emitting a write of it to the status page
876 * plus an interrupt, which will trigger i915_user_interrupt_handler.
877 *
878 * Must be called with struct_lock held.
879 *
880 * Returned sequence numbers are nonzero on success.
881 */
882static uint32_t
883i915_add_request(struct drm_device *dev, uint32_t flush_domains)
884{
885 drm_i915_private_t *dev_priv = dev->dev_private;
886 struct drm_i915_gem_request *request;
887 uint32_t seqno;
888 int was_empty;
889 RING_LOCALS;
890
891 request = drm_calloc(1, sizeof(*request), DRM_MEM_DRIVER);
892 if (request == NULL)
893 return 0;
894
895 /* Grab the seqno we're going to make this request be, and bump the
896 * next (skipping 0 so it can be the reserved no-seqno value).
897 */
898 seqno = dev_priv->mm.next_gem_seqno;
899 dev_priv->mm.next_gem_seqno++;
900 if (dev_priv->mm.next_gem_seqno == 0)
901 dev_priv->mm.next_gem_seqno++;
902
903 BEGIN_LP_RING(4);
904 OUT_RING(MI_STORE_DWORD_INDEX);
905 OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
906 OUT_RING(seqno);
907
908 OUT_RING(MI_USER_INTERRUPT);
909 ADVANCE_LP_RING();
910
911 DRM_DEBUG("%d\n", seqno);
912
913 request->seqno = seqno;
914 request->emitted_jiffies = jiffies;
Eric Anholt673a3942008-07-30 12:06:12 -0700915 was_empty = list_empty(&dev_priv->mm.request_list);
916 list_add_tail(&request->list, &dev_priv->mm.request_list);
917
Eric Anholtce44b0e2008-11-06 16:00:31 -0800918 /* Associate any objects on the flushing list matching the write
919 * domain we're flushing with our flush.
920 */
921 if (flush_domains != 0) {
922 struct drm_i915_gem_object *obj_priv, *next;
923
924 list_for_each_entry_safe(obj_priv, next,
925 &dev_priv->mm.flushing_list, list) {
926 struct drm_gem_object *obj = obj_priv->obj;
927
928 if ((obj->write_domain & flush_domains) ==
929 obj->write_domain) {
930 obj->write_domain = 0;
931 i915_gem_object_move_to_active(obj, seqno);
932 }
933 }
934
935 }
936
Keith Packard6dbe2772008-10-14 21:41:13 -0700937 if (was_empty && !dev_priv->mm.suspended)
Eric Anholt673a3942008-07-30 12:06:12 -0700938 schedule_delayed_work(&dev_priv->mm.retire_work, HZ);
939 return seqno;
940}
941
942/**
943 * Command execution barrier
944 *
945 * Ensures that all commands in the ring are finished
946 * before signalling the CPU
947 */
Eric Anholt3043c602008-10-02 12:24:47 -0700948static uint32_t
Eric Anholt673a3942008-07-30 12:06:12 -0700949i915_retire_commands(struct drm_device *dev)
950{
951 drm_i915_private_t *dev_priv = dev->dev_private;
952 uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
953 uint32_t flush_domains = 0;
954 RING_LOCALS;
955
956 /* The sampler always gets flushed on i965 (sigh) */
957 if (IS_I965G(dev))
958 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
959 BEGIN_LP_RING(2);
960 OUT_RING(cmd);
961 OUT_RING(0); /* noop */
962 ADVANCE_LP_RING();
963 return flush_domains;
964}
965
966/**
967 * Moves buffers associated only with the given active seqno from the active
968 * to inactive list, potentially freeing them.
969 */
970static void
971i915_gem_retire_request(struct drm_device *dev,
972 struct drm_i915_gem_request *request)
973{
974 drm_i915_private_t *dev_priv = dev->dev_private;
975
976 /* Move any buffers on the active list that are no longer referenced
977 * by the ringbuffer to the flushing/inactive lists as appropriate.
978 */
979 while (!list_empty(&dev_priv->mm.active_list)) {
980 struct drm_gem_object *obj;
981 struct drm_i915_gem_object *obj_priv;
982
983 obj_priv = list_first_entry(&dev_priv->mm.active_list,
984 struct drm_i915_gem_object,
985 list);
986 obj = obj_priv->obj;
987
988 /* If the seqno being retired doesn't match the oldest in the
989 * list, then the oldest in the list must still be newer than
990 * this seqno.
991 */
992 if (obj_priv->last_rendering_seqno != request->seqno)
993 return;
Jesse Barnesde151cf2008-11-12 10:03:55 -0800994
Eric Anholt673a3942008-07-30 12:06:12 -0700995#if WATCH_LRU
996 DRM_INFO("%s: retire %d moves to inactive list %p\n",
997 __func__, request->seqno, obj);
998#endif
999
Eric Anholtce44b0e2008-11-06 16:00:31 -08001000 if (obj->write_domain != 0)
1001 i915_gem_object_move_to_flushing(obj);
1002 else
Eric Anholt673a3942008-07-30 12:06:12 -07001003 i915_gem_object_move_to_inactive(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07001004 }
1005}
1006
1007/**
1008 * Returns true if seq1 is later than seq2.
1009 */
1010static int
1011i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1012{
1013 return (int32_t)(seq1 - seq2) >= 0;
1014}
1015
1016uint32_t
1017i915_get_gem_seqno(struct drm_device *dev)
1018{
1019 drm_i915_private_t *dev_priv = dev->dev_private;
1020
1021 return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
1022}
1023
1024/**
1025 * This function clears the request list as sequence numbers are passed.
1026 */
1027void
1028i915_gem_retire_requests(struct drm_device *dev)
1029{
1030 drm_i915_private_t *dev_priv = dev->dev_private;
1031 uint32_t seqno;
1032
1033 seqno = i915_get_gem_seqno(dev);
1034
1035 while (!list_empty(&dev_priv->mm.request_list)) {
1036 struct drm_i915_gem_request *request;
1037 uint32_t retiring_seqno;
1038
1039 request = list_first_entry(&dev_priv->mm.request_list,
1040 struct drm_i915_gem_request,
1041 list);
1042 retiring_seqno = request->seqno;
1043
1044 if (i915_seqno_passed(seqno, retiring_seqno) ||
1045 dev_priv->mm.wedged) {
1046 i915_gem_retire_request(dev, request);
1047
1048 list_del(&request->list);
1049 drm_free(request, sizeof(*request), DRM_MEM_DRIVER);
1050 } else
1051 break;
1052 }
1053}
1054
1055void
1056i915_gem_retire_work_handler(struct work_struct *work)
1057{
1058 drm_i915_private_t *dev_priv;
1059 struct drm_device *dev;
1060
1061 dev_priv = container_of(work, drm_i915_private_t,
1062 mm.retire_work.work);
1063 dev = dev_priv->dev;
1064
1065 mutex_lock(&dev->struct_mutex);
1066 i915_gem_retire_requests(dev);
Keith Packard6dbe2772008-10-14 21:41:13 -07001067 if (!dev_priv->mm.suspended &&
1068 !list_empty(&dev_priv->mm.request_list))
Eric Anholt673a3942008-07-30 12:06:12 -07001069 schedule_delayed_work(&dev_priv->mm.retire_work, HZ);
1070 mutex_unlock(&dev->struct_mutex);
1071}
1072
1073/**
1074 * Waits for a sequence number to be signaled, and cleans up the
1075 * request and object lists appropriately for that event.
1076 */
Eric Anholt3043c602008-10-02 12:24:47 -07001077static int
Eric Anholt673a3942008-07-30 12:06:12 -07001078i915_wait_request(struct drm_device *dev, uint32_t seqno)
1079{
1080 drm_i915_private_t *dev_priv = dev->dev_private;
1081 int ret = 0;
1082
1083 BUG_ON(seqno == 0);
1084
1085 if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
1086 dev_priv->mm.waiting_gem_seqno = seqno;
1087 i915_user_irq_get(dev);
1088 ret = wait_event_interruptible(dev_priv->irq_queue,
1089 i915_seqno_passed(i915_get_gem_seqno(dev),
1090 seqno) ||
1091 dev_priv->mm.wedged);
1092 i915_user_irq_put(dev);
1093 dev_priv->mm.waiting_gem_seqno = 0;
1094 }
1095 if (dev_priv->mm.wedged)
1096 ret = -EIO;
1097
1098 if (ret && ret != -ERESTARTSYS)
1099 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1100 __func__, ret, seqno, i915_get_gem_seqno(dev));
1101
1102 /* Directly dispatch request retiring. While we have the work queue
1103 * to handle this, the waiter on a request often wants an associated
1104 * buffer to have made it to the inactive list, and we would need
1105 * a separate wait queue to handle that.
1106 */
1107 if (ret == 0)
1108 i915_gem_retire_requests(dev);
1109
1110 return ret;
1111}
1112
1113static void
1114i915_gem_flush(struct drm_device *dev,
1115 uint32_t invalidate_domains,
1116 uint32_t flush_domains)
1117{
1118 drm_i915_private_t *dev_priv = dev->dev_private;
1119 uint32_t cmd;
1120 RING_LOCALS;
1121
1122#if WATCH_EXEC
1123 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
1124 invalidate_domains, flush_domains);
1125#endif
1126
1127 if (flush_domains & I915_GEM_DOMAIN_CPU)
1128 drm_agp_chipset_flush(dev);
1129
1130 if ((invalidate_domains | flush_domains) & ~(I915_GEM_DOMAIN_CPU |
1131 I915_GEM_DOMAIN_GTT)) {
1132 /*
1133 * read/write caches:
1134 *
1135 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1136 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
1137 * also flushed at 2d versus 3d pipeline switches.
1138 *
1139 * read-only caches:
1140 *
1141 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1142 * MI_READ_FLUSH is set, and is always flushed on 965.
1143 *
1144 * I915_GEM_DOMAIN_COMMAND may not exist?
1145 *
1146 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1147 * invalidated when MI_EXE_FLUSH is set.
1148 *
1149 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1150 * invalidated with every MI_FLUSH.
1151 *
1152 * TLBs:
1153 *
1154 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1155 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1156 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1157 * are flushed at any MI_FLUSH.
1158 */
1159
1160 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1161 if ((invalidate_domains|flush_domains) &
1162 I915_GEM_DOMAIN_RENDER)
1163 cmd &= ~MI_NO_WRITE_FLUSH;
1164 if (!IS_I965G(dev)) {
1165 /*
1166 * On the 965, the sampler cache always gets flushed
1167 * and this bit is reserved.
1168 */
1169 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
1170 cmd |= MI_READ_FLUSH;
1171 }
1172 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
1173 cmd |= MI_EXE_FLUSH;
1174
1175#if WATCH_EXEC
1176 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
1177#endif
1178 BEGIN_LP_RING(2);
1179 OUT_RING(cmd);
1180 OUT_RING(0); /* noop */
1181 ADVANCE_LP_RING();
1182 }
1183}
1184
1185/**
1186 * Ensures that all rendering to the object has completed and the object is
1187 * safe to unbind from the GTT or access from the CPU.
1188 */
1189static int
1190i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1191{
1192 struct drm_device *dev = obj->dev;
1193 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1194 int ret;
1195
Eric Anholte47c68e2008-11-14 13:35:19 -08001196 /* This function only exists to support waiting for existing rendering,
1197 * not for emitting required flushes.
Eric Anholt673a3942008-07-30 12:06:12 -07001198 */
Eric Anholte47c68e2008-11-14 13:35:19 -08001199 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
Eric Anholt673a3942008-07-30 12:06:12 -07001200
1201 /* If there is rendering queued on the buffer being evicted, wait for
1202 * it.
1203 */
1204 if (obj_priv->active) {
1205#if WATCH_BUF
1206 DRM_INFO("%s: object %p wait for seqno %08x\n",
1207 __func__, obj, obj_priv->last_rendering_seqno);
1208#endif
1209 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
1210 if (ret != 0)
1211 return ret;
1212 }
1213
1214 return 0;
1215}
1216
1217/**
1218 * Unbinds an object from the GTT aperture.
1219 */
Jesse Barnes0f973f22009-01-26 17:10:45 -08001220int
Eric Anholt673a3942008-07-30 12:06:12 -07001221i915_gem_object_unbind(struct drm_gem_object *obj)
1222{
1223 struct drm_device *dev = obj->dev;
1224 struct drm_i915_gem_object *obj_priv = obj->driver_private;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001225 loff_t offset;
Eric Anholt673a3942008-07-30 12:06:12 -07001226 int ret = 0;
1227
1228#if WATCH_BUF
1229 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1230 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1231#endif
1232 if (obj_priv->gtt_space == NULL)
1233 return 0;
1234
1235 if (obj_priv->pin_count != 0) {
1236 DRM_ERROR("Attempting to unbind pinned buffer\n");
1237 return -EINVAL;
1238 }
1239
Eric Anholt673a3942008-07-30 12:06:12 -07001240 /* Move the object to the CPU domain to ensure that
1241 * any possible CPU writes while it's not in the GTT
1242 * are flushed when we go to remap it. This will
1243 * also ensure that all pending GPU writes are finished
1244 * before we unbind.
1245 */
Eric Anholte47c68e2008-11-14 13:35:19 -08001246 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
Eric Anholt673a3942008-07-30 12:06:12 -07001247 if (ret) {
Eric Anholte47c68e2008-11-14 13:35:19 -08001248 if (ret != -ERESTARTSYS)
1249 DRM_ERROR("set_domain failed: %d\n", ret);
Eric Anholt673a3942008-07-30 12:06:12 -07001250 return ret;
1251 }
1252
1253 if (obj_priv->agp_mem != NULL) {
1254 drm_unbind_agp(obj_priv->agp_mem);
1255 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
1256 obj_priv->agp_mem = NULL;
1257 }
1258
1259 BUG_ON(obj_priv->active);
1260
Jesse Barnesde151cf2008-11-12 10:03:55 -08001261 /* blow away mappings if mapped through GTT */
1262 offset = ((loff_t) obj->map_list.hash.key) << PAGE_SHIFT;
Jesse Barnes79e53942008-11-07 14:24:08 -08001263 if (dev->dev_mapping)
1264 unmap_mapping_range(dev->dev_mapping, offset, obj->size, 1);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001265
1266 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
1267 i915_gem_clear_fence_reg(obj);
1268
Eric Anholt673a3942008-07-30 12:06:12 -07001269 i915_gem_object_free_page_list(obj);
1270
1271 if (obj_priv->gtt_space) {
1272 atomic_dec(&dev->gtt_count);
1273 atomic_sub(obj->size, &dev->gtt_memory);
1274
1275 drm_mm_put_block(obj_priv->gtt_space);
1276 obj_priv->gtt_space = NULL;
1277 }
1278
1279 /* Remove ourselves from the LRU list if present. */
1280 if (!list_empty(&obj_priv->list))
1281 list_del_init(&obj_priv->list);
1282
1283 return 0;
1284}
1285
1286static int
1287i915_gem_evict_something(struct drm_device *dev)
1288{
1289 drm_i915_private_t *dev_priv = dev->dev_private;
1290 struct drm_gem_object *obj;
1291 struct drm_i915_gem_object *obj_priv;
1292 int ret = 0;
1293
1294 for (;;) {
1295 /* If there's an inactive buffer available now, grab it
1296 * and be done.
1297 */
1298 if (!list_empty(&dev_priv->mm.inactive_list)) {
1299 obj_priv = list_first_entry(&dev_priv->mm.inactive_list,
1300 struct drm_i915_gem_object,
1301 list);
1302 obj = obj_priv->obj;
1303 BUG_ON(obj_priv->pin_count != 0);
1304#if WATCH_LRU
1305 DRM_INFO("%s: evicting %p\n", __func__, obj);
1306#endif
1307 BUG_ON(obj_priv->active);
1308
1309 /* Wait on the rendering and unbind the buffer. */
1310 ret = i915_gem_object_unbind(obj);
1311 break;
1312 }
1313
1314 /* If we didn't get anything, but the ring is still processing
1315 * things, wait for one of those things to finish and hopefully
1316 * leave us a buffer to evict.
1317 */
1318 if (!list_empty(&dev_priv->mm.request_list)) {
1319 struct drm_i915_gem_request *request;
1320
1321 request = list_first_entry(&dev_priv->mm.request_list,
1322 struct drm_i915_gem_request,
1323 list);
1324
1325 ret = i915_wait_request(dev, request->seqno);
1326 if (ret)
1327 break;
1328
1329 /* if waiting caused an object to become inactive,
1330 * then loop around and wait for it. Otherwise, we
1331 * assume that waiting freed and unbound something,
1332 * so there should now be some space in the GTT
1333 */
1334 if (!list_empty(&dev_priv->mm.inactive_list))
1335 continue;
1336 break;
1337 }
1338
1339 /* If we didn't have anything on the request list but there
1340 * are buffers awaiting a flush, emit one and try again.
1341 * When we wait on it, those buffers waiting for that flush
1342 * will get moved to inactive.
1343 */
1344 if (!list_empty(&dev_priv->mm.flushing_list)) {
1345 obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
1346 struct drm_i915_gem_object,
1347 list);
1348 obj = obj_priv->obj;
1349
1350 i915_gem_flush(dev,
1351 obj->write_domain,
1352 obj->write_domain);
1353 i915_add_request(dev, obj->write_domain);
1354
1355 obj = NULL;
1356 continue;
1357 }
1358
1359 DRM_ERROR("inactive empty %d request empty %d "
1360 "flushing empty %d\n",
1361 list_empty(&dev_priv->mm.inactive_list),
1362 list_empty(&dev_priv->mm.request_list),
1363 list_empty(&dev_priv->mm.flushing_list));
1364 /* If we didn't do any of the above, there's nothing to be done
1365 * and we just can't fit it in.
1366 */
1367 return -ENOMEM;
1368 }
1369 return ret;
1370}
1371
1372static int
Keith Packardac94a962008-11-20 23:30:27 -08001373i915_gem_evict_everything(struct drm_device *dev)
1374{
1375 int ret;
1376
1377 for (;;) {
1378 ret = i915_gem_evict_something(dev);
1379 if (ret != 0)
1380 break;
1381 }
Owain Ainsworth15c35332008-12-06 20:42:20 -08001382 if (ret == -ENOMEM)
1383 return 0;
Keith Packardac94a962008-11-20 23:30:27 -08001384 return ret;
1385}
1386
1387static int
Eric Anholt673a3942008-07-30 12:06:12 -07001388i915_gem_object_get_page_list(struct drm_gem_object *obj)
1389{
1390 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1391 int page_count, i;
1392 struct address_space *mapping;
1393 struct inode *inode;
1394 struct page *page;
1395 int ret;
1396
1397 if (obj_priv->page_list)
1398 return 0;
1399
1400 /* Get the list of pages out of our struct file. They'll be pinned
1401 * at this point until we release them.
1402 */
1403 page_count = obj->size / PAGE_SIZE;
1404 BUG_ON(obj_priv->page_list != NULL);
1405 obj_priv->page_list = drm_calloc(page_count, sizeof(struct page *),
1406 DRM_MEM_DRIVER);
1407 if (obj_priv->page_list == NULL) {
1408 DRM_ERROR("Faled to allocate page list\n");
1409 return -ENOMEM;
1410 }
1411
1412 inode = obj->filp->f_path.dentry->d_inode;
1413 mapping = inode->i_mapping;
1414 for (i = 0; i < page_count; i++) {
1415 page = read_mapping_page(mapping, i, NULL);
1416 if (IS_ERR(page)) {
1417 ret = PTR_ERR(page);
1418 DRM_ERROR("read_mapping_page failed: %d\n", ret);
1419 i915_gem_object_free_page_list(obj);
1420 return ret;
1421 }
1422 obj_priv->page_list[i] = page;
1423 }
1424 return 0;
1425}
1426
Jesse Barnesde151cf2008-11-12 10:03:55 -08001427static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
1428{
1429 struct drm_gem_object *obj = reg->obj;
1430 struct drm_device *dev = obj->dev;
1431 drm_i915_private_t *dev_priv = dev->dev_private;
1432 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1433 int regnum = obj_priv->fence_reg;
1434 uint64_t val;
1435
1436 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
1437 0xfffff000) << 32;
1438 val |= obj_priv->gtt_offset & 0xfffff000;
1439 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
1440 if (obj_priv->tiling_mode == I915_TILING_Y)
1441 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
1442 val |= I965_FENCE_REG_VALID;
1443
1444 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
1445}
1446
1447static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
1448{
1449 struct drm_gem_object *obj = reg->obj;
1450 struct drm_device *dev = obj->dev;
1451 drm_i915_private_t *dev_priv = dev->dev_private;
1452 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1453 int regnum = obj_priv->fence_reg;
Jesse Barnes0f973f22009-01-26 17:10:45 -08001454 int tile_width;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001455 uint32_t val;
1456 uint32_t pitch_val;
1457
1458 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
1459 (obj_priv->gtt_offset & (obj->size - 1))) {
Linus Torvaldsf06da262009-02-09 08:57:29 -08001460 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
Jesse Barnes0f973f22009-01-26 17:10:45 -08001461 __func__, obj_priv->gtt_offset, obj->size);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001462 return;
1463 }
1464
Jesse Barnes0f973f22009-01-26 17:10:45 -08001465 if (obj_priv->tiling_mode == I915_TILING_Y &&
1466 HAS_128_BYTE_Y_TILING(dev))
1467 tile_width = 128;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001468 else
Jesse Barnes0f973f22009-01-26 17:10:45 -08001469 tile_width = 512;
1470
1471 /* Note: pitch better be a power of two tile widths */
1472 pitch_val = obj_priv->stride / tile_width;
1473 pitch_val = ffs(pitch_val) - 1;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001474
1475 val = obj_priv->gtt_offset;
1476 if (obj_priv->tiling_mode == I915_TILING_Y)
1477 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
1478 val |= I915_FENCE_SIZE_BITS(obj->size);
1479 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
1480 val |= I830_FENCE_REG_VALID;
1481
1482 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
1483}
1484
1485static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
1486{
1487 struct drm_gem_object *obj = reg->obj;
1488 struct drm_device *dev = obj->dev;
1489 drm_i915_private_t *dev_priv = dev->dev_private;
1490 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1491 int regnum = obj_priv->fence_reg;
1492 uint32_t val;
1493 uint32_t pitch_val;
1494
1495 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
1496 (obj_priv->gtt_offset & (obj->size - 1))) {
Jesse Barnes0f973f22009-01-26 17:10:45 -08001497 WARN(1, "%s: object 0x%08x not 1M or size aligned\n",
1498 __func__, obj_priv->gtt_offset);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001499 return;
1500 }
1501
1502 pitch_val = (obj_priv->stride / 128) - 1;
1503
1504 val = obj_priv->gtt_offset;
1505 if (obj_priv->tiling_mode == I915_TILING_Y)
1506 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
1507 val |= I830_FENCE_SIZE_BITS(obj->size);
1508 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
1509 val |= I830_FENCE_REG_VALID;
1510
1511 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
1512
1513}
1514
1515/**
1516 * i915_gem_object_get_fence_reg - set up a fence reg for an object
1517 * @obj: object to map through a fence reg
Jesse Barnes0f973f22009-01-26 17:10:45 -08001518 * @write: object is about to be written
Jesse Barnesde151cf2008-11-12 10:03:55 -08001519 *
1520 * When mapping objects through the GTT, userspace wants to be able to write
1521 * to them without having to worry about swizzling if the object is tiled.
1522 *
1523 * This function walks the fence regs looking for a free one for @obj,
1524 * stealing one if it can't find any.
1525 *
1526 * It then sets up the reg based on the object's properties: address, pitch
1527 * and tiling format.
1528 */
Eric Anholtd9ddcb92009-01-27 10:33:49 -08001529static int
Jesse Barnes0f973f22009-01-26 17:10:45 -08001530i915_gem_object_get_fence_reg(struct drm_gem_object *obj, bool write)
Jesse Barnesde151cf2008-11-12 10:03:55 -08001531{
1532 struct drm_device *dev = obj->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08001533 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001534 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1535 struct drm_i915_fence_reg *reg = NULL;
1536 int i, ret;
1537
1538 switch (obj_priv->tiling_mode) {
1539 case I915_TILING_NONE:
1540 WARN(1, "allocating a fence for non-tiled object?\n");
1541 break;
1542 case I915_TILING_X:
Jesse Barnes0f973f22009-01-26 17:10:45 -08001543 if (!obj_priv->stride)
1544 return -EINVAL;
1545 WARN((obj_priv->stride & (512 - 1)),
1546 "object 0x%08x is X tiled but has non-512B pitch\n",
1547 obj_priv->gtt_offset);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001548 break;
1549 case I915_TILING_Y:
Jesse Barnes0f973f22009-01-26 17:10:45 -08001550 if (!obj_priv->stride)
1551 return -EINVAL;
1552 WARN((obj_priv->stride & (128 - 1)),
1553 "object 0x%08x is Y tiled but has non-128B pitch\n",
1554 obj_priv->gtt_offset);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001555 break;
1556 }
1557
1558 /* First try to find a free reg */
1559 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
1560 reg = &dev_priv->fence_regs[i];
1561 if (!reg->obj)
1562 break;
1563 }
1564
1565 /* None available, try to steal one or wait for a user to finish */
1566 if (i == dev_priv->num_fence_regs) {
1567 struct drm_i915_gem_object *old_obj_priv = NULL;
1568 loff_t offset;
1569
1570try_again:
1571 /* Could try to use LRU here instead... */
1572 for (i = dev_priv->fence_reg_start;
1573 i < dev_priv->num_fence_regs; i++) {
1574 reg = &dev_priv->fence_regs[i];
1575 old_obj_priv = reg->obj->driver_private;
1576 if (!old_obj_priv->pin_count)
1577 break;
1578 }
1579
1580 /*
1581 * Now things get ugly... we have to wait for one of the
1582 * objects to finish before trying again.
1583 */
1584 if (i == dev_priv->num_fence_regs) {
Eric Anholtd9ddcb92009-01-27 10:33:49 -08001585 ret = i915_gem_object_set_to_gtt_domain(reg->obj, 0);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001586 if (ret) {
Eric Anholtd9ddcb92009-01-27 10:33:49 -08001587 WARN(ret != -ERESTARTSYS,
1588 "switch to GTT domain failed: %d\n", ret);
1589 return ret;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001590 }
1591 goto try_again;
1592 }
1593
1594 /*
1595 * Zap this virtual mapping so we can set up a fence again
1596 * for this object next time we need it.
1597 */
1598 offset = ((loff_t) reg->obj->map_list.hash.key) << PAGE_SHIFT;
Jesse Barnes79e53942008-11-07 14:24:08 -08001599 if (dev->dev_mapping)
1600 unmap_mapping_range(dev->dev_mapping, offset,
1601 reg->obj->size, 1);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001602 old_obj_priv->fence_reg = I915_FENCE_REG_NONE;
1603 }
1604
1605 obj_priv->fence_reg = i;
1606 reg->obj = obj;
1607
1608 if (IS_I965G(dev))
1609 i965_write_fence_reg(reg);
1610 else if (IS_I9XX(dev))
1611 i915_write_fence_reg(reg);
1612 else
1613 i830_write_fence_reg(reg);
Eric Anholtd9ddcb92009-01-27 10:33:49 -08001614
1615 return 0;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001616}
1617
1618/**
1619 * i915_gem_clear_fence_reg - clear out fence register info
1620 * @obj: object to clear
1621 *
1622 * Zeroes out the fence register itself and clears out the associated
1623 * data structures in dev_priv and obj_priv.
1624 */
1625static void
1626i915_gem_clear_fence_reg(struct drm_gem_object *obj)
1627{
1628 struct drm_device *dev = obj->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08001629 drm_i915_private_t *dev_priv = dev->dev_private;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001630 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1631
1632 if (IS_I965G(dev))
1633 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
1634 else
1635 I915_WRITE(FENCE_REG_830_0 + (obj_priv->fence_reg * 4), 0);
1636
1637 dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL;
1638 obj_priv->fence_reg = I915_FENCE_REG_NONE;
1639}
1640
Eric Anholt673a3942008-07-30 12:06:12 -07001641/**
1642 * Finds free space in the GTT aperture and binds the object there.
1643 */
1644static int
1645i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
1646{
1647 struct drm_device *dev = obj->dev;
1648 drm_i915_private_t *dev_priv = dev->dev_private;
1649 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1650 struct drm_mm_node *free_space;
1651 int page_count, ret;
1652
Eric Anholt9bb2d6f2008-12-23 18:42:32 -08001653 if (dev_priv->mm.suspended)
1654 return -EBUSY;
Eric Anholt673a3942008-07-30 12:06:12 -07001655 if (alignment == 0)
Jesse Barnes0f973f22009-01-26 17:10:45 -08001656 alignment = i915_gem_get_gtt_alignment(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07001657 if (alignment & (PAGE_SIZE - 1)) {
1658 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
1659 return -EINVAL;
1660 }
1661
1662 search_free:
1663 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
1664 obj->size, alignment, 0);
1665 if (free_space != NULL) {
1666 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
1667 alignment);
1668 if (obj_priv->gtt_space != NULL) {
1669 obj_priv->gtt_space->private = obj;
1670 obj_priv->gtt_offset = obj_priv->gtt_space->start;
1671 }
1672 }
1673 if (obj_priv->gtt_space == NULL) {
1674 /* If the gtt is empty and we're still having trouble
1675 * fitting our object in, we're out of memory.
1676 */
1677#if WATCH_LRU
1678 DRM_INFO("%s: GTT full, evicting something\n", __func__);
1679#endif
1680 if (list_empty(&dev_priv->mm.inactive_list) &&
1681 list_empty(&dev_priv->mm.flushing_list) &&
1682 list_empty(&dev_priv->mm.active_list)) {
1683 DRM_ERROR("GTT full, but LRU list empty\n");
1684 return -ENOMEM;
1685 }
1686
1687 ret = i915_gem_evict_something(dev);
1688 if (ret != 0) {
Keith Packardac94a962008-11-20 23:30:27 -08001689 if (ret != -ERESTARTSYS)
1690 DRM_ERROR("Failed to evict a buffer %d\n", ret);
Eric Anholt673a3942008-07-30 12:06:12 -07001691 return ret;
1692 }
1693 goto search_free;
1694 }
1695
1696#if WATCH_BUF
1697 DRM_INFO("Binding object of size %d at 0x%08x\n",
1698 obj->size, obj_priv->gtt_offset);
1699#endif
1700 ret = i915_gem_object_get_page_list(obj);
1701 if (ret) {
1702 drm_mm_put_block(obj_priv->gtt_space);
1703 obj_priv->gtt_space = NULL;
1704 return ret;
1705 }
1706
1707 page_count = obj->size / PAGE_SIZE;
1708 /* Create an AGP memory structure pointing at our pages, and bind it
1709 * into the GTT.
1710 */
1711 obj_priv->agp_mem = drm_agp_bind_pages(dev,
1712 obj_priv->page_list,
1713 page_count,
Keith Packardba1eb1d2008-10-14 19:55:10 -07001714 obj_priv->gtt_offset,
1715 obj_priv->agp_type);
Eric Anholt673a3942008-07-30 12:06:12 -07001716 if (obj_priv->agp_mem == NULL) {
1717 i915_gem_object_free_page_list(obj);
1718 drm_mm_put_block(obj_priv->gtt_space);
1719 obj_priv->gtt_space = NULL;
1720 return -ENOMEM;
1721 }
1722 atomic_inc(&dev->gtt_count);
1723 atomic_add(obj->size, &dev->gtt_memory);
1724
1725 /* Assert that the object is not currently in any GPU domain. As it
1726 * wasn't in the GTT, there shouldn't be any way it could have been in
1727 * a GPU cache
1728 */
1729 BUG_ON(obj->read_domains & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
1730 BUG_ON(obj->write_domain & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
1731
1732 return 0;
1733}
1734
1735void
1736i915_gem_clflush_object(struct drm_gem_object *obj)
1737{
1738 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1739
1740 /* If we don't have a page list set up, then we're not pinned
1741 * to GPU, and we can ignore the cache flush because it'll happen
1742 * again at bind time.
1743 */
1744 if (obj_priv->page_list == NULL)
1745 return;
1746
1747 drm_clflush_pages(obj_priv->page_list, obj->size / PAGE_SIZE);
1748}
1749
Eric Anholte47c68e2008-11-14 13:35:19 -08001750/** Flushes any GPU write domain for the object if it's dirty. */
1751static void
1752i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
1753{
1754 struct drm_device *dev = obj->dev;
1755 uint32_t seqno;
1756
1757 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
1758 return;
1759
1760 /* Queue the GPU write cache flushing we need. */
1761 i915_gem_flush(dev, 0, obj->write_domain);
1762 seqno = i915_add_request(dev, obj->write_domain);
1763 obj->write_domain = 0;
1764 i915_gem_object_move_to_active(obj, seqno);
1765}
1766
1767/** Flushes the GTT write domain for the object if it's dirty. */
1768static void
1769i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
1770{
1771 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
1772 return;
1773
1774 /* No actual flushing is required for the GTT write domain. Writes
1775 * to it immediately go to main memory as far as we know, so there's
1776 * no chipset flush. It also doesn't land in render cache.
1777 */
1778 obj->write_domain = 0;
1779}
1780
1781/** Flushes the CPU write domain for the object if it's dirty. */
1782static void
1783i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
1784{
1785 struct drm_device *dev = obj->dev;
1786
1787 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
1788 return;
1789
1790 i915_gem_clflush_object(obj);
1791 drm_agp_chipset_flush(dev);
1792 obj->write_domain = 0;
1793}
1794
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001795/**
1796 * Moves a single object to the GTT read, and possibly write domain.
1797 *
1798 * This function returns when the move is complete, including waiting on
1799 * flushes to occur.
1800 */
Jesse Barnes79e53942008-11-07 14:24:08 -08001801int
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001802i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
1803{
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001804 struct drm_i915_gem_object *obj_priv = obj->driver_private;
Eric Anholte47c68e2008-11-14 13:35:19 -08001805 int ret;
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001806
Eric Anholt02354392008-11-26 13:58:13 -08001807 /* Not valid to be called on unbound objects. */
1808 if (obj_priv->gtt_space == NULL)
1809 return -EINVAL;
1810
Eric Anholte47c68e2008-11-14 13:35:19 -08001811 i915_gem_object_flush_gpu_write_domain(obj);
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001812 /* Wait on any GPU rendering and flushing to occur. */
Eric Anholte47c68e2008-11-14 13:35:19 -08001813 ret = i915_gem_object_wait_rendering(obj);
1814 if (ret != 0)
1815 return ret;
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001816
1817 /* If we're writing through the GTT domain, then CPU and GPU caches
1818 * will need to be invalidated at next use.
1819 */
1820 if (write)
Eric Anholte47c68e2008-11-14 13:35:19 -08001821 obj->read_domains &= I915_GEM_DOMAIN_GTT;
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001822
Eric Anholte47c68e2008-11-14 13:35:19 -08001823 i915_gem_object_flush_cpu_write_domain(obj);
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001824
1825 /* It should now be out of any other write domains, and we can update
1826 * the domain values for our changes.
1827 */
1828 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
1829 obj->read_domains |= I915_GEM_DOMAIN_GTT;
Eric Anholte47c68e2008-11-14 13:35:19 -08001830 if (write) {
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001831 obj->write_domain = I915_GEM_DOMAIN_GTT;
Eric Anholte47c68e2008-11-14 13:35:19 -08001832 obj_priv->dirty = 1;
1833 }
1834
1835 return 0;
1836}
1837
1838/**
1839 * Moves a single object to the CPU read, and possibly write domain.
1840 *
1841 * This function returns when the move is complete, including waiting on
1842 * flushes to occur.
1843 */
1844static int
1845i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
1846{
1847 struct drm_device *dev = obj->dev;
1848 int ret;
1849
1850 i915_gem_object_flush_gpu_write_domain(obj);
1851 /* Wait on any GPU rendering and flushing to occur. */
1852 ret = i915_gem_object_wait_rendering(obj);
1853 if (ret != 0)
1854 return ret;
1855
1856 i915_gem_object_flush_gtt_write_domain(obj);
1857
1858 /* If we have a partially-valid cache of the object in the CPU,
1859 * finish invalidating it and free the per-page flags.
1860 */
1861 i915_gem_object_set_to_full_cpu_read_domain(obj);
1862
1863 /* Flush the CPU cache if it's still invalid. */
1864 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
1865 i915_gem_clflush_object(obj);
1866 drm_agp_chipset_flush(dev);
1867
1868 obj->read_domains |= I915_GEM_DOMAIN_CPU;
1869 }
1870
1871 /* It should now be out of any other write domains, and we can update
1872 * the domain values for our changes.
1873 */
1874 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
1875
1876 /* If we're writing through the CPU, then the GPU read domains will
1877 * need to be invalidated at next use.
1878 */
1879 if (write) {
1880 obj->read_domains &= I915_GEM_DOMAIN_CPU;
1881 obj->write_domain = I915_GEM_DOMAIN_CPU;
1882 }
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001883
1884 return 0;
1885}
1886
Eric Anholt673a3942008-07-30 12:06:12 -07001887/*
1888 * Set the next domain for the specified object. This
1889 * may not actually perform the necessary flushing/invaliding though,
1890 * as that may want to be batched with other set_domain operations
1891 *
1892 * This is (we hope) the only really tricky part of gem. The goal
1893 * is fairly simple -- track which caches hold bits of the object
1894 * and make sure they remain coherent. A few concrete examples may
1895 * help to explain how it works. For shorthand, we use the notation
1896 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
1897 * a pair of read and write domain masks.
1898 *
1899 * Case 1: the batch buffer
1900 *
1901 * 1. Allocated
1902 * 2. Written by CPU
1903 * 3. Mapped to GTT
1904 * 4. Read by GPU
1905 * 5. Unmapped from GTT
1906 * 6. Freed
1907 *
1908 * Let's take these a step at a time
1909 *
1910 * 1. Allocated
1911 * Pages allocated from the kernel may still have
1912 * cache contents, so we set them to (CPU, CPU) always.
1913 * 2. Written by CPU (using pwrite)
1914 * The pwrite function calls set_domain (CPU, CPU) and
1915 * this function does nothing (as nothing changes)
1916 * 3. Mapped by GTT
1917 * This function asserts that the object is not
1918 * currently in any GPU-based read or write domains
1919 * 4. Read by GPU
1920 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
1921 * As write_domain is zero, this function adds in the
1922 * current read domains (CPU+COMMAND, 0).
1923 * flush_domains is set to CPU.
1924 * invalidate_domains is set to COMMAND
1925 * clflush is run to get data out of the CPU caches
1926 * then i915_dev_set_domain calls i915_gem_flush to
1927 * emit an MI_FLUSH and drm_agp_chipset_flush
1928 * 5. Unmapped from GTT
1929 * i915_gem_object_unbind calls set_domain (CPU, CPU)
1930 * flush_domains and invalidate_domains end up both zero
1931 * so no flushing/invalidating happens
1932 * 6. Freed
1933 * yay, done
1934 *
1935 * Case 2: The shared render buffer
1936 *
1937 * 1. Allocated
1938 * 2. Mapped to GTT
1939 * 3. Read/written by GPU
1940 * 4. set_domain to (CPU,CPU)
1941 * 5. Read/written by CPU
1942 * 6. Read/written by GPU
1943 *
1944 * 1. Allocated
1945 * Same as last example, (CPU, CPU)
1946 * 2. Mapped to GTT
1947 * Nothing changes (assertions find that it is not in the GPU)
1948 * 3. Read/written by GPU
1949 * execbuffer calls set_domain (RENDER, RENDER)
1950 * flush_domains gets CPU
1951 * invalidate_domains gets GPU
1952 * clflush (obj)
1953 * MI_FLUSH and drm_agp_chipset_flush
1954 * 4. set_domain (CPU, CPU)
1955 * flush_domains gets GPU
1956 * invalidate_domains gets CPU
1957 * wait_rendering (obj) to make sure all drawing is complete.
1958 * This will include an MI_FLUSH to get the data from GPU
1959 * to memory
1960 * clflush (obj) to invalidate the CPU cache
1961 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
1962 * 5. Read/written by CPU
1963 * cache lines are loaded and dirtied
1964 * 6. Read written by GPU
1965 * Same as last GPU access
1966 *
1967 * Case 3: The constant buffer
1968 *
1969 * 1. Allocated
1970 * 2. Written by CPU
1971 * 3. Read by GPU
1972 * 4. Updated (written) by CPU again
1973 * 5. Read by GPU
1974 *
1975 * 1. Allocated
1976 * (CPU, CPU)
1977 * 2. Written by CPU
1978 * (CPU, CPU)
1979 * 3. Read by GPU
1980 * (CPU+RENDER, 0)
1981 * flush_domains = CPU
1982 * invalidate_domains = RENDER
1983 * clflush (obj)
1984 * MI_FLUSH
1985 * drm_agp_chipset_flush
1986 * 4. Updated (written) by CPU again
1987 * (CPU, CPU)
1988 * flush_domains = 0 (no previous write domain)
1989 * invalidate_domains = 0 (no new read domains)
1990 * 5. Read by GPU
1991 * (CPU+RENDER, 0)
1992 * flush_domains = CPU
1993 * invalidate_domains = RENDER
1994 * clflush (obj)
1995 * MI_FLUSH
1996 * drm_agp_chipset_flush
1997 */
Keith Packardc0d90822008-11-20 23:11:08 -08001998static void
1999i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj,
2000 uint32_t read_domains,
2001 uint32_t write_domain)
Eric Anholt673a3942008-07-30 12:06:12 -07002002{
2003 struct drm_device *dev = obj->dev;
2004 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2005 uint32_t invalidate_domains = 0;
2006 uint32_t flush_domains = 0;
Eric Anholte47c68e2008-11-14 13:35:19 -08002007
2008 BUG_ON(read_domains & I915_GEM_DOMAIN_CPU);
2009 BUG_ON(write_domain == I915_GEM_DOMAIN_CPU);
Eric Anholt673a3942008-07-30 12:06:12 -07002010
2011#if WATCH_BUF
2012 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2013 __func__, obj,
2014 obj->read_domains, read_domains,
2015 obj->write_domain, write_domain);
2016#endif
2017 /*
2018 * If the object isn't moving to a new write domain,
2019 * let the object stay in multiple read domains
2020 */
2021 if (write_domain == 0)
2022 read_domains |= obj->read_domains;
2023 else
2024 obj_priv->dirty = 1;
2025
2026 /*
2027 * Flush the current write domain if
2028 * the new read domains don't match. Invalidate
2029 * any read domains which differ from the old
2030 * write domain
2031 */
2032 if (obj->write_domain && obj->write_domain != read_domains) {
2033 flush_domains |= obj->write_domain;
2034 invalidate_domains |= read_domains & ~obj->write_domain;
2035 }
2036 /*
2037 * Invalidate any read caches which may have
2038 * stale data. That is, any new read domains.
2039 */
2040 invalidate_domains |= read_domains & ~obj->read_domains;
2041 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
2042#if WATCH_BUF
2043 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
2044 __func__, flush_domains, invalidate_domains);
2045#endif
Eric Anholt673a3942008-07-30 12:06:12 -07002046 i915_gem_clflush_object(obj);
2047 }
2048
2049 if ((write_domain | flush_domains) != 0)
2050 obj->write_domain = write_domain;
Eric Anholt673a3942008-07-30 12:06:12 -07002051 obj->read_domains = read_domains;
2052
2053 dev->invalidate_domains |= invalidate_domains;
2054 dev->flush_domains |= flush_domains;
2055#if WATCH_BUF
2056 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
2057 __func__,
2058 obj->read_domains, obj->write_domain,
2059 dev->invalidate_domains, dev->flush_domains);
2060#endif
Eric Anholt673a3942008-07-30 12:06:12 -07002061}
2062
2063/**
Eric Anholte47c68e2008-11-14 13:35:19 -08002064 * Moves the object from a partially CPU read to a full one.
Eric Anholt673a3942008-07-30 12:06:12 -07002065 *
Eric Anholte47c68e2008-11-14 13:35:19 -08002066 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
2067 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
2068 */
2069static void
2070i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
2071{
2072 struct drm_device *dev = obj->dev;
2073 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2074
2075 if (!obj_priv->page_cpu_valid)
2076 return;
2077
2078 /* If we're partially in the CPU read domain, finish moving it in.
2079 */
2080 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
2081 int i;
2082
2083 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
2084 if (obj_priv->page_cpu_valid[i])
2085 continue;
2086 drm_clflush_pages(obj_priv->page_list + i, 1);
2087 }
2088 drm_agp_chipset_flush(dev);
2089 }
2090
2091 /* Free the page_cpu_valid mappings which are now stale, whether
2092 * or not we've got I915_GEM_DOMAIN_CPU.
2093 */
2094 drm_free(obj_priv->page_cpu_valid, obj->size / PAGE_SIZE,
2095 DRM_MEM_DRIVER);
2096 obj_priv->page_cpu_valid = NULL;
2097}
2098
2099/**
2100 * Set the CPU read domain on a range of the object.
2101 *
2102 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
2103 * not entirely valid. The page_cpu_valid member of the object flags which
2104 * pages have been flushed, and will be respected by
2105 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
2106 * of the whole object.
2107 *
2108 * This function returns when the move is complete, including waiting on
2109 * flushes to occur.
Eric Anholt673a3942008-07-30 12:06:12 -07002110 */
2111static int
Eric Anholte47c68e2008-11-14 13:35:19 -08002112i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
2113 uint64_t offset, uint64_t size)
Eric Anholt673a3942008-07-30 12:06:12 -07002114{
2115 struct drm_i915_gem_object *obj_priv = obj->driver_private;
Eric Anholte47c68e2008-11-14 13:35:19 -08002116 int i, ret;
Eric Anholt673a3942008-07-30 12:06:12 -07002117
Eric Anholte47c68e2008-11-14 13:35:19 -08002118 if (offset == 0 && size == obj->size)
2119 return i915_gem_object_set_to_cpu_domain(obj, 0);
2120
2121 i915_gem_object_flush_gpu_write_domain(obj);
2122 /* Wait on any GPU rendering and flushing to occur. */
2123 ret = i915_gem_object_wait_rendering(obj);
2124 if (ret != 0)
2125 return ret;
2126 i915_gem_object_flush_gtt_write_domain(obj);
2127
2128 /* If we're already fully in the CPU read domain, we're done. */
2129 if (obj_priv->page_cpu_valid == NULL &&
2130 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
Eric Anholt673a3942008-07-30 12:06:12 -07002131 return 0;
2132
Eric Anholte47c68e2008-11-14 13:35:19 -08002133 /* Otherwise, create/clear the per-page CPU read domain flag if we're
2134 * newly adding I915_GEM_DOMAIN_CPU
2135 */
Eric Anholt673a3942008-07-30 12:06:12 -07002136 if (obj_priv->page_cpu_valid == NULL) {
2137 obj_priv->page_cpu_valid = drm_calloc(1, obj->size / PAGE_SIZE,
2138 DRM_MEM_DRIVER);
Eric Anholte47c68e2008-11-14 13:35:19 -08002139 if (obj_priv->page_cpu_valid == NULL)
2140 return -ENOMEM;
2141 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
2142 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
Eric Anholt673a3942008-07-30 12:06:12 -07002143
2144 /* Flush the cache on any pages that are still invalid from the CPU's
2145 * perspective.
2146 */
Eric Anholte47c68e2008-11-14 13:35:19 -08002147 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
2148 i++) {
Eric Anholt673a3942008-07-30 12:06:12 -07002149 if (obj_priv->page_cpu_valid[i])
2150 continue;
2151
2152 drm_clflush_pages(obj_priv->page_list + i, 1);
2153
2154 obj_priv->page_cpu_valid[i] = 1;
2155 }
2156
Eric Anholte47c68e2008-11-14 13:35:19 -08002157 /* It should now be out of any other write domains, and we can update
2158 * the domain values for our changes.
2159 */
2160 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2161
2162 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2163
Eric Anholt673a3942008-07-30 12:06:12 -07002164 return 0;
2165}
2166
2167/**
Eric Anholt673a3942008-07-30 12:06:12 -07002168 * Pin an object to the GTT and evaluate the relocations landing in it.
2169 */
2170static int
2171i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
2172 struct drm_file *file_priv,
2173 struct drm_i915_gem_exec_object *entry)
2174{
2175 struct drm_device *dev = obj->dev;
Keith Packard0839ccb2008-10-30 19:38:48 -07002176 drm_i915_private_t *dev_priv = dev->dev_private;
Eric Anholt673a3942008-07-30 12:06:12 -07002177 struct drm_i915_gem_relocation_entry reloc;
2178 struct drm_i915_gem_relocation_entry __user *relocs;
2179 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2180 int i, ret;
Keith Packard0839ccb2008-10-30 19:38:48 -07002181 void __iomem *reloc_page;
Eric Anholt673a3942008-07-30 12:06:12 -07002182
2183 /* Choose the GTT offset for our buffer and put it there. */
2184 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
2185 if (ret)
2186 return ret;
2187
2188 entry->offset = obj_priv->gtt_offset;
2189
2190 relocs = (struct drm_i915_gem_relocation_entry __user *)
2191 (uintptr_t) entry->relocs_ptr;
2192 /* Apply the relocations, using the GTT aperture to avoid cache
2193 * flushing requirements.
2194 */
2195 for (i = 0; i < entry->relocation_count; i++) {
2196 struct drm_gem_object *target_obj;
2197 struct drm_i915_gem_object *target_obj_priv;
Eric Anholt3043c602008-10-02 12:24:47 -07002198 uint32_t reloc_val, reloc_offset;
2199 uint32_t __iomem *reloc_entry;
Eric Anholt673a3942008-07-30 12:06:12 -07002200
2201 ret = copy_from_user(&reloc, relocs + i, sizeof(reloc));
2202 if (ret != 0) {
2203 i915_gem_object_unpin(obj);
2204 return ret;
2205 }
2206
2207 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
2208 reloc.target_handle);
2209 if (target_obj == NULL) {
2210 i915_gem_object_unpin(obj);
2211 return -EBADF;
2212 }
2213 target_obj_priv = target_obj->driver_private;
2214
2215 /* The target buffer should have appeared before us in the
2216 * exec_object list, so it should have a GTT space bound by now.
2217 */
2218 if (target_obj_priv->gtt_space == NULL) {
2219 DRM_ERROR("No GTT space found for object %d\n",
2220 reloc.target_handle);
2221 drm_gem_object_unreference(target_obj);
2222 i915_gem_object_unpin(obj);
2223 return -EINVAL;
2224 }
2225
2226 if (reloc.offset > obj->size - 4) {
2227 DRM_ERROR("Relocation beyond object bounds: "
2228 "obj %p target %d offset %d size %d.\n",
2229 obj, reloc.target_handle,
2230 (int) reloc.offset, (int) obj->size);
2231 drm_gem_object_unreference(target_obj);
2232 i915_gem_object_unpin(obj);
2233 return -EINVAL;
2234 }
2235 if (reloc.offset & 3) {
2236 DRM_ERROR("Relocation not 4-byte aligned: "
2237 "obj %p target %d offset %d.\n",
2238 obj, reloc.target_handle,
2239 (int) reloc.offset);
2240 drm_gem_object_unreference(target_obj);
2241 i915_gem_object_unpin(obj);
2242 return -EINVAL;
2243 }
2244
Eric Anholte47c68e2008-11-14 13:35:19 -08002245 if (reloc.write_domain & I915_GEM_DOMAIN_CPU ||
2246 reloc.read_domains & I915_GEM_DOMAIN_CPU) {
2247 DRM_ERROR("reloc with read/write CPU domains: "
2248 "obj %p target %d offset %d "
2249 "read %08x write %08x",
2250 obj, reloc.target_handle,
2251 (int) reloc.offset,
2252 reloc.read_domains,
2253 reloc.write_domain);
2254 return -EINVAL;
2255 }
2256
Eric Anholt673a3942008-07-30 12:06:12 -07002257 if (reloc.write_domain && target_obj->pending_write_domain &&
2258 reloc.write_domain != target_obj->pending_write_domain) {
2259 DRM_ERROR("Write domain conflict: "
2260 "obj %p target %d offset %d "
2261 "new %08x old %08x\n",
2262 obj, reloc.target_handle,
2263 (int) reloc.offset,
2264 reloc.write_domain,
2265 target_obj->pending_write_domain);
2266 drm_gem_object_unreference(target_obj);
2267 i915_gem_object_unpin(obj);
2268 return -EINVAL;
2269 }
2270
2271#if WATCH_RELOC
2272 DRM_INFO("%s: obj %p offset %08x target %d "
2273 "read %08x write %08x gtt %08x "
2274 "presumed %08x delta %08x\n",
2275 __func__,
2276 obj,
2277 (int) reloc.offset,
2278 (int) reloc.target_handle,
2279 (int) reloc.read_domains,
2280 (int) reloc.write_domain,
2281 (int) target_obj_priv->gtt_offset,
2282 (int) reloc.presumed_offset,
2283 reloc.delta);
2284#endif
2285
2286 target_obj->pending_read_domains |= reloc.read_domains;
2287 target_obj->pending_write_domain |= reloc.write_domain;
2288
2289 /* If the relocation already has the right value in it, no
2290 * more work needs to be done.
2291 */
2292 if (target_obj_priv->gtt_offset == reloc.presumed_offset) {
2293 drm_gem_object_unreference(target_obj);
2294 continue;
2295 }
2296
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002297 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
2298 if (ret != 0) {
2299 drm_gem_object_unreference(target_obj);
2300 i915_gem_object_unpin(obj);
2301 return -EINVAL;
Eric Anholt673a3942008-07-30 12:06:12 -07002302 }
2303
2304 /* Map the page containing the relocation we're going to
2305 * perform.
2306 */
2307 reloc_offset = obj_priv->gtt_offset + reloc.offset;
Keith Packard0839ccb2008-10-30 19:38:48 -07002308 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
2309 (reloc_offset &
2310 ~(PAGE_SIZE - 1)));
Eric Anholt3043c602008-10-02 12:24:47 -07002311 reloc_entry = (uint32_t __iomem *)(reloc_page +
Keith Packard0839ccb2008-10-30 19:38:48 -07002312 (reloc_offset & (PAGE_SIZE - 1)));
Eric Anholt673a3942008-07-30 12:06:12 -07002313 reloc_val = target_obj_priv->gtt_offset + reloc.delta;
2314
2315#if WATCH_BUF
2316 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
2317 obj, (unsigned int) reloc.offset,
2318 readl(reloc_entry), reloc_val);
2319#endif
2320 writel(reloc_val, reloc_entry);
Keith Packard0839ccb2008-10-30 19:38:48 -07002321 io_mapping_unmap_atomic(reloc_page);
Eric Anholt673a3942008-07-30 12:06:12 -07002322
2323 /* Write the updated presumed offset for this entry back out
2324 * to the user.
2325 */
2326 reloc.presumed_offset = target_obj_priv->gtt_offset;
2327 ret = copy_to_user(relocs + i, &reloc, sizeof(reloc));
2328 if (ret != 0) {
2329 drm_gem_object_unreference(target_obj);
2330 i915_gem_object_unpin(obj);
2331 return ret;
2332 }
2333
2334 drm_gem_object_unreference(target_obj);
2335 }
2336
Eric Anholt673a3942008-07-30 12:06:12 -07002337#if WATCH_BUF
2338 if (0)
2339 i915_gem_dump_object(obj, 128, __func__, ~0);
2340#endif
2341 return 0;
2342}
2343
2344/** Dispatch a batchbuffer to the ring
2345 */
2346static int
2347i915_dispatch_gem_execbuffer(struct drm_device *dev,
2348 struct drm_i915_gem_execbuffer *exec,
2349 uint64_t exec_offset)
2350{
2351 drm_i915_private_t *dev_priv = dev->dev_private;
2352 struct drm_clip_rect __user *boxes = (struct drm_clip_rect __user *)
2353 (uintptr_t) exec->cliprects_ptr;
2354 int nbox = exec->num_cliprects;
2355 int i = 0, count;
2356 uint32_t exec_start, exec_len;
2357 RING_LOCALS;
2358
2359 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
2360 exec_len = (uint32_t) exec->batch_len;
2361
2362 if ((exec_start | exec_len) & 0x7) {
2363 DRM_ERROR("alignment\n");
2364 return -EINVAL;
2365 }
2366
2367 if (!exec_start)
2368 return -EINVAL;
2369
2370 count = nbox ? nbox : 1;
2371
2372 for (i = 0; i < count; i++) {
2373 if (i < nbox) {
2374 int ret = i915_emit_box(dev, boxes, i,
2375 exec->DR1, exec->DR4);
2376 if (ret)
2377 return ret;
2378 }
2379
2380 if (IS_I830(dev) || IS_845G(dev)) {
2381 BEGIN_LP_RING(4);
2382 OUT_RING(MI_BATCH_BUFFER);
2383 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
2384 OUT_RING(exec_start + exec_len - 4);
2385 OUT_RING(0);
2386 ADVANCE_LP_RING();
2387 } else {
2388 BEGIN_LP_RING(2);
2389 if (IS_I965G(dev)) {
2390 OUT_RING(MI_BATCH_BUFFER_START |
2391 (2 << 6) |
2392 MI_BATCH_NON_SECURE_I965);
2393 OUT_RING(exec_start);
2394 } else {
2395 OUT_RING(MI_BATCH_BUFFER_START |
2396 (2 << 6));
2397 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
2398 }
2399 ADVANCE_LP_RING();
2400 }
2401 }
2402
2403 /* XXX breadcrumb */
2404 return 0;
2405}
2406
2407/* Throttle our rendering by waiting until the ring has completed our requests
2408 * emitted over 20 msec ago.
2409 *
2410 * This should get us reasonable parallelism between CPU and GPU but also
2411 * relatively low latency when blocking on a particular request to finish.
2412 */
2413static int
2414i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
2415{
2416 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
2417 int ret = 0;
2418 uint32_t seqno;
2419
2420 mutex_lock(&dev->struct_mutex);
2421 seqno = i915_file_priv->mm.last_gem_throttle_seqno;
2422 i915_file_priv->mm.last_gem_throttle_seqno =
2423 i915_file_priv->mm.last_gem_seqno;
2424 if (seqno)
2425 ret = i915_wait_request(dev, seqno);
2426 mutex_unlock(&dev->struct_mutex);
2427 return ret;
2428}
2429
2430int
2431i915_gem_execbuffer(struct drm_device *dev, void *data,
2432 struct drm_file *file_priv)
2433{
2434 drm_i915_private_t *dev_priv = dev->dev_private;
2435 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
2436 struct drm_i915_gem_execbuffer *args = data;
2437 struct drm_i915_gem_exec_object *exec_list = NULL;
2438 struct drm_gem_object **object_list = NULL;
2439 struct drm_gem_object *batch_obj;
2440 int ret, i, pinned = 0;
2441 uint64_t exec_offset;
2442 uint32_t seqno, flush_domains;
Keith Packardac94a962008-11-20 23:30:27 -08002443 int pin_tries;
Eric Anholt673a3942008-07-30 12:06:12 -07002444
2445#if WATCH_EXEC
2446 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
2447 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
2448#endif
2449
Eric Anholt4f481ed2008-09-10 14:22:49 -07002450 if (args->buffer_count < 1) {
2451 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
2452 return -EINVAL;
2453 }
Eric Anholt673a3942008-07-30 12:06:12 -07002454 /* Copy in the exec list from userland */
2455 exec_list = drm_calloc(sizeof(*exec_list), args->buffer_count,
2456 DRM_MEM_DRIVER);
2457 object_list = drm_calloc(sizeof(*object_list), args->buffer_count,
2458 DRM_MEM_DRIVER);
2459 if (exec_list == NULL || object_list == NULL) {
2460 DRM_ERROR("Failed to allocate exec or object list "
2461 "for %d buffers\n",
2462 args->buffer_count);
2463 ret = -ENOMEM;
2464 goto pre_mutex_err;
2465 }
2466 ret = copy_from_user(exec_list,
2467 (struct drm_i915_relocation_entry __user *)
2468 (uintptr_t) args->buffers_ptr,
2469 sizeof(*exec_list) * args->buffer_count);
2470 if (ret != 0) {
2471 DRM_ERROR("copy %d exec entries failed %d\n",
2472 args->buffer_count, ret);
2473 goto pre_mutex_err;
2474 }
2475
2476 mutex_lock(&dev->struct_mutex);
2477
2478 i915_verify_inactive(dev, __FILE__, __LINE__);
2479
2480 if (dev_priv->mm.wedged) {
2481 DRM_ERROR("Execbuf while wedged\n");
2482 mutex_unlock(&dev->struct_mutex);
Chris Wilsona198bc82009-02-06 16:55:20 +00002483 ret = -EIO;
2484 goto pre_mutex_err;
Eric Anholt673a3942008-07-30 12:06:12 -07002485 }
2486
2487 if (dev_priv->mm.suspended) {
2488 DRM_ERROR("Execbuf while VT-switched.\n");
2489 mutex_unlock(&dev->struct_mutex);
Chris Wilsona198bc82009-02-06 16:55:20 +00002490 ret = -EBUSY;
2491 goto pre_mutex_err;
Eric Anholt673a3942008-07-30 12:06:12 -07002492 }
2493
Keith Packardac94a962008-11-20 23:30:27 -08002494 /* Look up object handles */
Eric Anholt673a3942008-07-30 12:06:12 -07002495 for (i = 0; i < args->buffer_count; i++) {
2496 object_list[i] = drm_gem_object_lookup(dev, file_priv,
2497 exec_list[i].handle);
2498 if (object_list[i] == NULL) {
2499 DRM_ERROR("Invalid object handle %d at index %d\n",
2500 exec_list[i].handle, i);
2501 ret = -EBADF;
2502 goto err;
2503 }
Keith Packardac94a962008-11-20 23:30:27 -08002504 }
Eric Anholt673a3942008-07-30 12:06:12 -07002505
Keith Packardac94a962008-11-20 23:30:27 -08002506 /* Pin and relocate */
2507 for (pin_tries = 0; ; pin_tries++) {
2508 ret = 0;
2509 for (i = 0; i < args->buffer_count; i++) {
2510 object_list[i]->pending_read_domains = 0;
2511 object_list[i]->pending_write_domain = 0;
2512 ret = i915_gem_object_pin_and_relocate(object_list[i],
2513 file_priv,
2514 &exec_list[i]);
2515 if (ret)
2516 break;
2517 pinned = i + 1;
2518 }
2519 /* success */
2520 if (ret == 0)
2521 break;
2522
2523 /* error other than GTT full, or we've already tried again */
2524 if (ret != -ENOMEM || pin_tries >= 1) {
Eric Anholtf1acec92008-12-19 14:47:48 -08002525 if (ret != -ERESTARTSYS)
2526 DRM_ERROR("Failed to pin buffers %d\n", ret);
Eric Anholt673a3942008-07-30 12:06:12 -07002527 goto err;
2528 }
Keith Packardac94a962008-11-20 23:30:27 -08002529
2530 /* unpin all of our buffers */
2531 for (i = 0; i < pinned; i++)
2532 i915_gem_object_unpin(object_list[i]);
Eric Anholtb1177632008-12-10 10:09:41 -08002533 pinned = 0;
Keith Packardac94a962008-11-20 23:30:27 -08002534
2535 /* evict everyone we can from the aperture */
2536 ret = i915_gem_evict_everything(dev);
2537 if (ret)
2538 goto err;
Eric Anholt673a3942008-07-30 12:06:12 -07002539 }
2540
2541 /* Set the pending read domains for the batch buffer to COMMAND */
2542 batch_obj = object_list[args->buffer_count-1];
2543 batch_obj->pending_read_domains = I915_GEM_DOMAIN_COMMAND;
2544 batch_obj->pending_write_domain = 0;
2545
2546 i915_verify_inactive(dev, __FILE__, __LINE__);
2547
Keith Packard646f0f62008-11-20 23:23:03 -08002548 /* Zero the global flush/invalidate flags. These
2549 * will be modified as new domains are computed
2550 * for each object
2551 */
2552 dev->invalidate_domains = 0;
2553 dev->flush_domains = 0;
2554
Eric Anholt673a3942008-07-30 12:06:12 -07002555 for (i = 0; i < args->buffer_count; i++) {
2556 struct drm_gem_object *obj = object_list[i];
Eric Anholt673a3942008-07-30 12:06:12 -07002557
Keith Packard646f0f62008-11-20 23:23:03 -08002558 /* Compute new gpu domains and update invalidate/flush */
Keith Packardc0d90822008-11-20 23:11:08 -08002559 i915_gem_object_set_to_gpu_domain(obj,
2560 obj->pending_read_domains,
2561 obj->pending_write_domain);
Eric Anholt673a3942008-07-30 12:06:12 -07002562 }
2563
2564 i915_verify_inactive(dev, __FILE__, __LINE__);
2565
Keith Packard646f0f62008-11-20 23:23:03 -08002566 if (dev->invalidate_domains | dev->flush_domains) {
2567#if WATCH_EXEC
2568 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
2569 __func__,
2570 dev->invalidate_domains,
2571 dev->flush_domains);
2572#endif
2573 i915_gem_flush(dev,
2574 dev->invalidate_domains,
2575 dev->flush_domains);
2576 if (dev->flush_domains)
2577 (void)i915_add_request(dev, dev->flush_domains);
2578 }
Eric Anholt673a3942008-07-30 12:06:12 -07002579
2580 i915_verify_inactive(dev, __FILE__, __LINE__);
2581
2582#if WATCH_COHERENCY
2583 for (i = 0; i < args->buffer_count; i++) {
2584 i915_gem_object_check_coherency(object_list[i],
2585 exec_list[i].handle);
2586 }
2587#endif
2588
2589 exec_offset = exec_list[args->buffer_count - 1].offset;
2590
2591#if WATCH_EXEC
2592 i915_gem_dump_object(object_list[args->buffer_count - 1],
2593 args->batch_len,
2594 __func__,
2595 ~0);
2596#endif
2597
Eric Anholt673a3942008-07-30 12:06:12 -07002598 /* Exec the batchbuffer */
2599 ret = i915_dispatch_gem_execbuffer(dev, args, exec_offset);
2600 if (ret) {
2601 DRM_ERROR("dispatch failed %d\n", ret);
2602 goto err;
2603 }
2604
2605 /*
2606 * Ensure that the commands in the batch buffer are
2607 * finished before the interrupt fires
2608 */
2609 flush_domains = i915_retire_commands(dev);
2610
2611 i915_verify_inactive(dev, __FILE__, __LINE__);
2612
2613 /*
2614 * Get a seqno representing the execution of the current buffer,
2615 * which we can wait on. We would like to mitigate these interrupts,
2616 * likely by only creating seqnos occasionally (so that we have
2617 * *some* interrupts representing completion of buffers that we can
2618 * wait on when trying to clear up gtt space).
2619 */
2620 seqno = i915_add_request(dev, flush_domains);
2621 BUG_ON(seqno == 0);
2622 i915_file_priv->mm.last_gem_seqno = seqno;
2623 for (i = 0; i < args->buffer_count; i++) {
2624 struct drm_gem_object *obj = object_list[i];
Eric Anholt673a3942008-07-30 12:06:12 -07002625
Eric Anholtce44b0e2008-11-06 16:00:31 -08002626 i915_gem_object_move_to_active(obj, seqno);
Eric Anholt673a3942008-07-30 12:06:12 -07002627#if WATCH_LRU
2628 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
2629#endif
2630 }
2631#if WATCH_LRU
2632 i915_dump_lru(dev, __func__);
2633#endif
2634
2635 i915_verify_inactive(dev, __FILE__, __LINE__);
2636
2637 /* Copy the new buffer offsets back to the user's exec list. */
2638 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
2639 (uintptr_t) args->buffers_ptr,
2640 exec_list,
2641 sizeof(*exec_list) * args->buffer_count);
2642 if (ret)
2643 DRM_ERROR("failed to copy %d exec entries "
2644 "back to user (%d)\n",
2645 args->buffer_count, ret);
2646err:
Julia Lawallaad87df2008-12-21 16:28:47 +01002647 for (i = 0; i < pinned; i++)
2648 i915_gem_object_unpin(object_list[i]);
Eric Anholt673a3942008-07-30 12:06:12 -07002649
Julia Lawallaad87df2008-12-21 16:28:47 +01002650 for (i = 0; i < args->buffer_count; i++)
2651 drm_gem_object_unreference(object_list[i]);
2652
Eric Anholt673a3942008-07-30 12:06:12 -07002653 mutex_unlock(&dev->struct_mutex);
2654
2655pre_mutex_err:
2656 drm_free(object_list, sizeof(*object_list) * args->buffer_count,
2657 DRM_MEM_DRIVER);
2658 drm_free(exec_list, sizeof(*exec_list) * args->buffer_count,
2659 DRM_MEM_DRIVER);
2660
2661 return ret;
2662}
2663
2664int
2665i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
2666{
2667 struct drm_device *dev = obj->dev;
2668 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2669 int ret;
2670
2671 i915_verify_inactive(dev, __FILE__, __LINE__);
2672 if (obj_priv->gtt_space == NULL) {
2673 ret = i915_gem_object_bind_to_gtt(obj, alignment);
2674 if (ret != 0) {
Eric Anholt9bb2d6f2008-12-23 18:42:32 -08002675 if (ret != -EBUSY && ret != -ERESTARTSYS)
Eric Anholtf1acec92008-12-19 14:47:48 -08002676 DRM_ERROR("Failure to bind: %d", ret);
Eric Anholt673a3942008-07-30 12:06:12 -07002677 return ret;
2678 }
Jesse Barnes0f973f22009-01-26 17:10:45 -08002679 /*
2680 * Pre-965 chips need a fence register set up in order to
2681 * properly handle tiled surfaces.
2682 */
2683 if (!IS_I965G(dev) &&
2684 obj_priv->fence_reg == I915_FENCE_REG_NONE &&
2685 obj_priv->tiling_mode != I915_TILING_NONE)
2686 i915_gem_object_get_fence_reg(obj, true);
Eric Anholt673a3942008-07-30 12:06:12 -07002687 }
2688 obj_priv->pin_count++;
2689
2690 /* If the object is not active and not pending a flush,
2691 * remove it from the inactive list
2692 */
2693 if (obj_priv->pin_count == 1) {
2694 atomic_inc(&dev->pin_count);
2695 atomic_add(obj->size, &dev->pin_memory);
2696 if (!obj_priv->active &&
2697 (obj->write_domain & ~(I915_GEM_DOMAIN_CPU |
2698 I915_GEM_DOMAIN_GTT)) == 0 &&
2699 !list_empty(&obj_priv->list))
2700 list_del_init(&obj_priv->list);
2701 }
2702 i915_verify_inactive(dev, __FILE__, __LINE__);
2703
2704 return 0;
2705}
2706
2707void
2708i915_gem_object_unpin(struct drm_gem_object *obj)
2709{
2710 struct drm_device *dev = obj->dev;
2711 drm_i915_private_t *dev_priv = dev->dev_private;
2712 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2713
2714 i915_verify_inactive(dev, __FILE__, __LINE__);
2715 obj_priv->pin_count--;
2716 BUG_ON(obj_priv->pin_count < 0);
2717 BUG_ON(obj_priv->gtt_space == NULL);
2718
2719 /* If the object is no longer pinned, and is
2720 * neither active nor being flushed, then stick it on
2721 * the inactive list
2722 */
2723 if (obj_priv->pin_count == 0) {
2724 if (!obj_priv->active &&
2725 (obj->write_domain & ~(I915_GEM_DOMAIN_CPU |
2726 I915_GEM_DOMAIN_GTT)) == 0)
2727 list_move_tail(&obj_priv->list,
2728 &dev_priv->mm.inactive_list);
2729 atomic_dec(&dev->pin_count);
2730 atomic_sub(obj->size, &dev->pin_memory);
2731 }
2732 i915_verify_inactive(dev, __FILE__, __LINE__);
2733}
2734
2735int
2736i915_gem_pin_ioctl(struct drm_device *dev, void *data,
2737 struct drm_file *file_priv)
2738{
2739 struct drm_i915_gem_pin *args = data;
2740 struct drm_gem_object *obj;
2741 struct drm_i915_gem_object *obj_priv;
2742 int ret;
2743
2744 mutex_lock(&dev->struct_mutex);
2745
2746 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2747 if (obj == NULL) {
2748 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
2749 args->handle);
2750 mutex_unlock(&dev->struct_mutex);
2751 return -EBADF;
2752 }
2753 obj_priv = obj->driver_private;
2754
Jesse Barnes79e53942008-11-07 14:24:08 -08002755 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
2756 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
2757 args->handle);
Eric Anholt673a3942008-07-30 12:06:12 -07002758 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08002759 return -EINVAL;
2760 }
2761
2762 obj_priv->user_pin_count++;
2763 obj_priv->pin_filp = file_priv;
2764 if (obj_priv->user_pin_count == 1) {
2765 ret = i915_gem_object_pin(obj, args->alignment);
2766 if (ret != 0) {
2767 drm_gem_object_unreference(obj);
2768 mutex_unlock(&dev->struct_mutex);
2769 return ret;
2770 }
Eric Anholt673a3942008-07-30 12:06:12 -07002771 }
2772
2773 /* XXX - flush the CPU caches for pinned objects
2774 * as the X server doesn't manage domains yet
2775 */
Eric Anholte47c68e2008-11-14 13:35:19 -08002776 i915_gem_object_flush_cpu_write_domain(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07002777 args->offset = obj_priv->gtt_offset;
2778 drm_gem_object_unreference(obj);
2779 mutex_unlock(&dev->struct_mutex);
2780
2781 return 0;
2782}
2783
2784int
2785i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
2786 struct drm_file *file_priv)
2787{
2788 struct drm_i915_gem_pin *args = data;
2789 struct drm_gem_object *obj;
Jesse Barnes79e53942008-11-07 14:24:08 -08002790 struct drm_i915_gem_object *obj_priv;
Eric Anholt673a3942008-07-30 12:06:12 -07002791
2792 mutex_lock(&dev->struct_mutex);
2793
2794 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2795 if (obj == NULL) {
2796 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
2797 args->handle);
2798 mutex_unlock(&dev->struct_mutex);
2799 return -EBADF;
2800 }
2801
Jesse Barnes79e53942008-11-07 14:24:08 -08002802 obj_priv = obj->driver_private;
2803 if (obj_priv->pin_filp != file_priv) {
2804 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
2805 args->handle);
2806 drm_gem_object_unreference(obj);
2807 mutex_unlock(&dev->struct_mutex);
2808 return -EINVAL;
2809 }
2810 obj_priv->user_pin_count--;
2811 if (obj_priv->user_pin_count == 0) {
2812 obj_priv->pin_filp = NULL;
2813 i915_gem_object_unpin(obj);
2814 }
Eric Anholt673a3942008-07-30 12:06:12 -07002815
2816 drm_gem_object_unreference(obj);
2817 mutex_unlock(&dev->struct_mutex);
2818 return 0;
2819}
2820
2821int
2822i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2823 struct drm_file *file_priv)
2824{
2825 struct drm_i915_gem_busy *args = data;
2826 struct drm_gem_object *obj;
2827 struct drm_i915_gem_object *obj_priv;
2828
2829 mutex_lock(&dev->struct_mutex);
2830 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2831 if (obj == NULL) {
2832 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
2833 args->handle);
2834 mutex_unlock(&dev->struct_mutex);
2835 return -EBADF;
2836 }
2837
2838 obj_priv = obj->driver_private;
Eric Anholtc4de0a52008-12-14 19:05:04 -08002839 /* Don't count being on the flushing list against the object being
2840 * done. Otherwise, a buffer left on the flushing list but not getting
2841 * flushed (because nobody's flushing that domain) won't ever return
2842 * unbusy and get reused by libdrm's bo cache. The other expected
2843 * consumer of this interface, OpenGL's occlusion queries, also specs
2844 * that the objects get unbusy "eventually" without any interference.
2845 */
2846 args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
Eric Anholt673a3942008-07-30 12:06:12 -07002847
2848 drm_gem_object_unreference(obj);
2849 mutex_unlock(&dev->struct_mutex);
2850 return 0;
2851}
2852
2853int
2854i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2855 struct drm_file *file_priv)
2856{
2857 return i915_gem_ring_throttle(dev, file_priv);
2858}
2859
2860int i915_gem_init_object(struct drm_gem_object *obj)
2861{
2862 struct drm_i915_gem_object *obj_priv;
2863
2864 obj_priv = drm_calloc(1, sizeof(*obj_priv), DRM_MEM_DRIVER);
2865 if (obj_priv == NULL)
2866 return -ENOMEM;
2867
2868 /*
2869 * We've just allocated pages from the kernel,
2870 * so they've just been written by the CPU with
2871 * zeros. They'll need to be clflushed before we
2872 * use them with the GPU.
2873 */
2874 obj->write_domain = I915_GEM_DOMAIN_CPU;
2875 obj->read_domains = I915_GEM_DOMAIN_CPU;
2876
Keith Packardba1eb1d2008-10-14 19:55:10 -07002877 obj_priv->agp_type = AGP_USER_MEMORY;
2878
Eric Anholt673a3942008-07-30 12:06:12 -07002879 obj->driver_private = obj_priv;
2880 obj_priv->obj = obj;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002881 obj_priv->fence_reg = I915_FENCE_REG_NONE;
Eric Anholt673a3942008-07-30 12:06:12 -07002882 INIT_LIST_HEAD(&obj_priv->list);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002883
Eric Anholt673a3942008-07-30 12:06:12 -07002884 return 0;
2885}
2886
2887void i915_gem_free_object(struct drm_gem_object *obj)
2888{
Jesse Barnesde151cf2008-11-12 10:03:55 -08002889 struct drm_device *dev = obj->dev;
2890 struct drm_gem_mm *mm = dev->mm_private;
2891 struct drm_map_list *list;
2892 struct drm_map *map;
Eric Anholt673a3942008-07-30 12:06:12 -07002893 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2894
2895 while (obj_priv->pin_count > 0)
2896 i915_gem_object_unpin(obj);
2897
Dave Airlie71acb5e2008-12-30 20:31:46 +10002898 if (obj_priv->phys_obj)
2899 i915_gem_detach_phys_object(dev, obj);
2900
Eric Anholt673a3942008-07-30 12:06:12 -07002901 i915_gem_object_unbind(obj);
2902
Jesse Barnesde151cf2008-11-12 10:03:55 -08002903 list = &obj->map_list;
2904 drm_ht_remove_item(&mm->offset_hash, &list->hash);
2905
2906 if (list->file_offset_node) {
2907 drm_mm_put_block(list->file_offset_node);
2908 list->file_offset_node = NULL;
2909 }
2910
2911 map = list->map;
2912 if (map) {
2913 drm_free(map, sizeof(*map), DRM_MEM_DRIVER);
2914 list->map = NULL;
2915 }
2916
Eric Anholt673a3942008-07-30 12:06:12 -07002917 drm_free(obj_priv->page_cpu_valid, 1, DRM_MEM_DRIVER);
2918 drm_free(obj->driver_private, 1, DRM_MEM_DRIVER);
2919}
2920
Eric Anholt673a3942008-07-30 12:06:12 -07002921/** Unbinds all objects that are on the given buffer list. */
2922static int
2923i915_gem_evict_from_list(struct drm_device *dev, struct list_head *head)
2924{
2925 struct drm_gem_object *obj;
2926 struct drm_i915_gem_object *obj_priv;
2927 int ret;
2928
2929 while (!list_empty(head)) {
2930 obj_priv = list_first_entry(head,
2931 struct drm_i915_gem_object,
2932 list);
2933 obj = obj_priv->obj;
2934
2935 if (obj_priv->pin_count != 0) {
2936 DRM_ERROR("Pinned object in unbind list\n");
2937 mutex_unlock(&dev->struct_mutex);
2938 return -EINVAL;
2939 }
2940
2941 ret = i915_gem_object_unbind(obj);
2942 if (ret != 0) {
2943 DRM_ERROR("Error unbinding object in LeaveVT: %d\n",
2944 ret);
2945 mutex_unlock(&dev->struct_mutex);
2946 return ret;
2947 }
2948 }
2949
2950
2951 return 0;
2952}
2953
2954static int
2955i915_gem_idle(struct drm_device *dev)
2956{
2957 drm_i915_private_t *dev_priv = dev->dev_private;
2958 uint32_t seqno, cur_seqno, last_seqno;
2959 int stuck, ret;
2960
Keith Packard6dbe2772008-10-14 21:41:13 -07002961 mutex_lock(&dev->struct_mutex);
2962
2963 if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
2964 mutex_unlock(&dev->struct_mutex);
Eric Anholt673a3942008-07-30 12:06:12 -07002965 return 0;
Keith Packard6dbe2772008-10-14 21:41:13 -07002966 }
Eric Anholt673a3942008-07-30 12:06:12 -07002967
2968 /* Hack! Don't let anybody do execbuf while we don't control the chip.
2969 * We need to replace this with a semaphore, or something.
2970 */
2971 dev_priv->mm.suspended = 1;
2972
Keith Packard6dbe2772008-10-14 21:41:13 -07002973 /* Cancel the retire work handler, wait for it to finish if running
2974 */
2975 mutex_unlock(&dev->struct_mutex);
2976 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
2977 mutex_lock(&dev->struct_mutex);
2978
Eric Anholt673a3942008-07-30 12:06:12 -07002979 i915_kernel_lost_context(dev);
2980
2981 /* Flush the GPU along with all non-CPU write domains
2982 */
2983 i915_gem_flush(dev, ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT),
2984 ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
Jesse Barnesde151cf2008-11-12 10:03:55 -08002985 seqno = i915_add_request(dev, ~I915_GEM_DOMAIN_CPU);
Eric Anholt673a3942008-07-30 12:06:12 -07002986
2987 if (seqno == 0) {
2988 mutex_unlock(&dev->struct_mutex);
2989 return -ENOMEM;
2990 }
2991
2992 dev_priv->mm.waiting_gem_seqno = seqno;
2993 last_seqno = 0;
2994 stuck = 0;
2995 for (;;) {
2996 cur_seqno = i915_get_gem_seqno(dev);
2997 if (i915_seqno_passed(cur_seqno, seqno))
2998 break;
2999 if (last_seqno == cur_seqno) {
3000 if (stuck++ > 100) {
3001 DRM_ERROR("hardware wedged\n");
3002 dev_priv->mm.wedged = 1;
3003 DRM_WAKEUP(&dev_priv->irq_queue);
3004 break;
3005 }
3006 }
3007 msleep(10);
3008 last_seqno = cur_seqno;
3009 }
3010 dev_priv->mm.waiting_gem_seqno = 0;
3011
3012 i915_gem_retire_requests(dev);
3013
Eric Anholt28dfe522008-11-13 15:00:55 -08003014 if (!dev_priv->mm.wedged) {
3015 /* Active and flushing should now be empty as we've
3016 * waited for a sequence higher than any pending execbuffer
3017 */
3018 WARN_ON(!list_empty(&dev_priv->mm.active_list));
3019 WARN_ON(!list_empty(&dev_priv->mm.flushing_list));
3020 /* Request should now be empty as we've also waited
3021 * for the last request in the list
3022 */
3023 WARN_ON(!list_empty(&dev_priv->mm.request_list));
3024 }
Eric Anholt673a3942008-07-30 12:06:12 -07003025
Eric Anholt28dfe522008-11-13 15:00:55 -08003026 /* Empty the active and flushing lists to inactive. If there's
3027 * anything left at this point, it means that we're wedged and
3028 * nothing good's going to happen by leaving them there. So strip
3029 * the GPU domains and just stuff them onto inactive.
Eric Anholt673a3942008-07-30 12:06:12 -07003030 */
Eric Anholt28dfe522008-11-13 15:00:55 -08003031 while (!list_empty(&dev_priv->mm.active_list)) {
3032 struct drm_i915_gem_object *obj_priv;
Eric Anholt673a3942008-07-30 12:06:12 -07003033
Eric Anholt28dfe522008-11-13 15:00:55 -08003034 obj_priv = list_first_entry(&dev_priv->mm.active_list,
3035 struct drm_i915_gem_object,
3036 list);
3037 obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
3038 i915_gem_object_move_to_inactive(obj_priv->obj);
3039 }
3040
3041 while (!list_empty(&dev_priv->mm.flushing_list)) {
3042 struct drm_i915_gem_object *obj_priv;
3043
Eric Anholt151903d2008-12-01 10:23:21 +10003044 obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
Eric Anholt28dfe522008-11-13 15:00:55 -08003045 struct drm_i915_gem_object,
3046 list);
3047 obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
3048 i915_gem_object_move_to_inactive(obj_priv->obj);
3049 }
3050
3051
3052 /* Move all inactive buffers out of the GTT. */
Eric Anholt673a3942008-07-30 12:06:12 -07003053 ret = i915_gem_evict_from_list(dev, &dev_priv->mm.inactive_list);
Eric Anholt28dfe522008-11-13 15:00:55 -08003054 WARN_ON(!list_empty(&dev_priv->mm.inactive_list));
Keith Packard6dbe2772008-10-14 21:41:13 -07003055 if (ret) {
3056 mutex_unlock(&dev->struct_mutex);
Eric Anholt673a3942008-07-30 12:06:12 -07003057 return ret;
Keith Packard6dbe2772008-10-14 21:41:13 -07003058 }
Eric Anholt673a3942008-07-30 12:06:12 -07003059
Keith Packard6dbe2772008-10-14 21:41:13 -07003060 i915_gem_cleanup_ringbuffer(dev);
3061 mutex_unlock(&dev->struct_mutex);
3062
Eric Anholt673a3942008-07-30 12:06:12 -07003063 return 0;
3064}
3065
3066static int
3067i915_gem_init_hws(struct drm_device *dev)
3068{
3069 drm_i915_private_t *dev_priv = dev->dev_private;
3070 struct drm_gem_object *obj;
3071 struct drm_i915_gem_object *obj_priv;
3072 int ret;
3073
3074 /* If we need a physical address for the status page, it's already
3075 * initialized at driver load time.
3076 */
3077 if (!I915_NEED_GFX_HWS(dev))
3078 return 0;
3079
3080 obj = drm_gem_object_alloc(dev, 4096);
3081 if (obj == NULL) {
3082 DRM_ERROR("Failed to allocate status page\n");
3083 return -ENOMEM;
3084 }
3085 obj_priv = obj->driver_private;
Keith Packardba1eb1d2008-10-14 19:55:10 -07003086 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
Eric Anholt673a3942008-07-30 12:06:12 -07003087
3088 ret = i915_gem_object_pin(obj, 4096);
3089 if (ret != 0) {
3090 drm_gem_object_unreference(obj);
3091 return ret;
3092 }
3093
3094 dev_priv->status_gfx_addr = obj_priv->gtt_offset;
Eric Anholt673a3942008-07-30 12:06:12 -07003095
Keith Packardba1eb1d2008-10-14 19:55:10 -07003096 dev_priv->hw_status_page = kmap(obj_priv->page_list[0]);
3097 if (dev_priv->hw_status_page == NULL) {
Eric Anholt673a3942008-07-30 12:06:12 -07003098 DRM_ERROR("Failed to map status page.\n");
3099 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
3100 drm_gem_object_unreference(obj);
3101 return -EINVAL;
3102 }
3103 dev_priv->hws_obj = obj;
Eric Anholt673a3942008-07-30 12:06:12 -07003104 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
3105 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
Keith Packardba1eb1d2008-10-14 19:55:10 -07003106 I915_READ(HWS_PGA); /* posting read */
Eric Anholt673a3942008-07-30 12:06:12 -07003107 DRM_DEBUG("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
3108
3109 return 0;
3110}
3111
Jesse Barnes79e53942008-11-07 14:24:08 -08003112int
Eric Anholt673a3942008-07-30 12:06:12 -07003113i915_gem_init_ringbuffer(struct drm_device *dev)
3114{
3115 drm_i915_private_t *dev_priv = dev->dev_private;
3116 struct drm_gem_object *obj;
3117 struct drm_i915_gem_object *obj_priv;
Jesse Barnes79e53942008-11-07 14:24:08 -08003118 drm_i915_ring_buffer_t *ring = &dev_priv->ring;
Eric Anholt673a3942008-07-30 12:06:12 -07003119 int ret;
Keith Packard50aa2532008-10-14 17:20:35 -07003120 u32 head;
Eric Anholt673a3942008-07-30 12:06:12 -07003121
3122 ret = i915_gem_init_hws(dev);
3123 if (ret != 0)
3124 return ret;
3125
3126 obj = drm_gem_object_alloc(dev, 128 * 1024);
3127 if (obj == NULL) {
3128 DRM_ERROR("Failed to allocate ringbuffer\n");
3129 return -ENOMEM;
3130 }
3131 obj_priv = obj->driver_private;
3132
3133 ret = i915_gem_object_pin(obj, 4096);
3134 if (ret != 0) {
3135 drm_gem_object_unreference(obj);
3136 return ret;
3137 }
3138
3139 /* Set up the kernel mapping for the ring. */
Jesse Barnes79e53942008-11-07 14:24:08 -08003140 ring->Size = obj->size;
3141 ring->tail_mask = obj->size - 1;
Eric Anholt673a3942008-07-30 12:06:12 -07003142
Jesse Barnes79e53942008-11-07 14:24:08 -08003143 ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
3144 ring->map.size = obj->size;
3145 ring->map.type = 0;
3146 ring->map.flags = 0;
3147 ring->map.mtrr = 0;
Eric Anholt673a3942008-07-30 12:06:12 -07003148
Jesse Barnes79e53942008-11-07 14:24:08 -08003149 drm_core_ioremap_wc(&ring->map, dev);
3150 if (ring->map.handle == NULL) {
Eric Anholt673a3942008-07-30 12:06:12 -07003151 DRM_ERROR("Failed to map ringbuffer.\n");
3152 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
3153 drm_gem_object_unreference(obj);
3154 return -EINVAL;
3155 }
Jesse Barnes79e53942008-11-07 14:24:08 -08003156 ring->ring_obj = obj;
3157 ring->virtual_start = ring->map.handle;
Eric Anholt673a3942008-07-30 12:06:12 -07003158
3159 /* Stop the ring if it's running. */
3160 I915_WRITE(PRB0_CTL, 0);
Eric Anholt673a3942008-07-30 12:06:12 -07003161 I915_WRITE(PRB0_TAIL, 0);
Keith Packard50aa2532008-10-14 17:20:35 -07003162 I915_WRITE(PRB0_HEAD, 0);
Eric Anholt673a3942008-07-30 12:06:12 -07003163
3164 /* Initialize the ring. */
3165 I915_WRITE(PRB0_START, obj_priv->gtt_offset);
Keith Packard50aa2532008-10-14 17:20:35 -07003166 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
3167
3168 /* G45 ring initialization fails to reset head to zero */
3169 if (head != 0) {
3170 DRM_ERROR("Ring head not reset to zero "
3171 "ctl %08x head %08x tail %08x start %08x\n",
3172 I915_READ(PRB0_CTL),
3173 I915_READ(PRB0_HEAD),
3174 I915_READ(PRB0_TAIL),
3175 I915_READ(PRB0_START));
3176 I915_WRITE(PRB0_HEAD, 0);
3177
3178 DRM_ERROR("Ring head forced to zero "
3179 "ctl %08x head %08x tail %08x start %08x\n",
3180 I915_READ(PRB0_CTL),
3181 I915_READ(PRB0_HEAD),
3182 I915_READ(PRB0_TAIL),
3183 I915_READ(PRB0_START));
3184 }
3185
Eric Anholt673a3942008-07-30 12:06:12 -07003186 I915_WRITE(PRB0_CTL,
3187 ((obj->size - 4096) & RING_NR_PAGES) |
3188 RING_NO_REPORT |
3189 RING_VALID);
3190
Keith Packard50aa2532008-10-14 17:20:35 -07003191 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
3192
3193 /* If the head is still not zero, the ring is dead */
3194 if (head != 0) {
3195 DRM_ERROR("Ring initialization failed "
3196 "ctl %08x head %08x tail %08x start %08x\n",
3197 I915_READ(PRB0_CTL),
3198 I915_READ(PRB0_HEAD),
3199 I915_READ(PRB0_TAIL),
3200 I915_READ(PRB0_START));
3201 return -EIO;
3202 }
3203
Eric Anholt673a3942008-07-30 12:06:12 -07003204 /* Update our cache of the ring state */
Jesse Barnes79e53942008-11-07 14:24:08 -08003205 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3206 i915_kernel_lost_context(dev);
3207 else {
3208 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
3209 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
3210 ring->space = ring->head - (ring->tail + 8);
3211 if (ring->space < 0)
3212 ring->space += ring->Size;
3213 }
Eric Anholt673a3942008-07-30 12:06:12 -07003214
3215 return 0;
3216}
3217
Jesse Barnes79e53942008-11-07 14:24:08 -08003218void
Eric Anholt673a3942008-07-30 12:06:12 -07003219i915_gem_cleanup_ringbuffer(struct drm_device *dev)
3220{
3221 drm_i915_private_t *dev_priv = dev->dev_private;
3222
3223 if (dev_priv->ring.ring_obj == NULL)
3224 return;
3225
3226 drm_core_ioremapfree(&dev_priv->ring.map, dev);
3227
3228 i915_gem_object_unpin(dev_priv->ring.ring_obj);
3229 drm_gem_object_unreference(dev_priv->ring.ring_obj);
3230 dev_priv->ring.ring_obj = NULL;
3231 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
3232
3233 if (dev_priv->hws_obj != NULL) {
Keith Packardba1eb1d2008-10-14 19:55:10 -07003234 struct drm_gem_object *obj = dev_priv->hws_obj;
3235 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3236
3237 kunmap(obj_priv->page_list[0]);
3238 i915_gem_object_unpin(obj);
3239 drm_gem_object_unreference(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07003240 dev_priv->hws_obj = NULL;
3241 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
Keith Packardba1eb1d2008-10-14 19:55:10 -07003242 dev_priv->hw_status_page = NULL;
Eric Anholt673a3942008-07-30 12:06:12 -07003243
3244 /* Write high address into HWS_PGA when disabling. */
3245 I915_WRITE(HWS_PGA, 0x1ffff000);
3246 }
3247}
3248
3249int
3250i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
3251 struct drm_file *file_priv)
3252{
3253 drm_i915_private_t *dev_priv = dev->dev_private;
3254 int ret;
3255
Jesse Barnes79e53942008-11-07 14:24:08 -08003256 if (drm_core_check_feature(dev, DRIVER_MODESET))
3257 return 0;
3258
Eric Anholt673a3942008-07-30 12:06:12 -07003259 if (dev_priv->mm.wedged) {
3260 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3261 dev_priv->mm.wedged = 0;
3262 }
3263
Eric Anholt673a3942008-07-30 12:06:12 -07003264 mutex_lock(&dev->struct_mutex);
Eric Anholt9bb2d6f2008-12-23 18:42:32 -08003265 dev_priv->mm.suspended = 0;
3266
3267 ret = i915_gem_init_ringbuffer(dev);
3268 if (ret != 0)
3269 return ret;
3270
Eric Anholt673a3942008-07-30 12:06:12 -07003271 BUG_ON(!list_empty(&dev_priv->mm.active_list));
3272 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
3273 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
3274 BUG_ON(!list_empty(&dev_priv->mm.request_list));
Eric Anholt673a3942008-07-30 12:06:12 -07003275 mutex_unlock(&dev->struct_mutex);
Kristian Høgsbergdbb19d32008-08-20 11:04:27 -04003276
3277 drm_irq_install(dev);
3278
Eric Anholt673a3942008-07-30 12:06:12 -07003279 return 0;
3280}
3281
3282int
3283i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
3284 struct drm_file *file_priv)
3285{
3286 int ret;
3287
Jesse Barnes79e53942008-11-07 14:24:08 -08003288 if (drm_core_check_feature(dev, DRIVER_MODESET))
3289 return 0;
3290
Eric Anholt673a3942008-07-30 12:06:12 -07003291 ret = i915_gem_idle(dev);
Kristian Høgsbergdbb19d32008-08-20 11:04:27 -04003292 drm_irq_uninstall(dev);
3293
Keith Packard6dbe2772008-10-14 21:41:13 -07003294 return ret;
Eric Anholt673a3942008-07-30 12:06:12 -07003295}
3296
3297void
3298i915_gem_lastclose(struct drm_device *dev)
3299{
3300 int ret;
Eric Anholt673a3942008-07-30 12:06:12 -07003301
Eric Anholte806b492009-01-22 09:56:58 -08003302 if (drm_core_check_feature(dev, DRIVER_MODESET))
3303 return;
3304
Keith Packard6dbe2772008-10-14 21:41:13 -07003305 ret = i915_gem_idle(dev);
3306 if (ret)
3307 DRM_ERROR("failed to idle hardware: %d\n", ret);
Eric Anholt673a3942008-07-30 12:06:12 -07003308}
3309
3310void
3311i915_gem_load(struct drm_device *dev)
3312{
3313 drm_i915_private_t *dev_priv = dev->dev_private;
3314
3315 INIT_LIST_HEAD(&dev_priv->mm.active_list);
3316 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
3317 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
3318 INIT_LIST_HEAD(&dev_priv->mm.request_list);
3319 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
3320 i915_gem_retire_work_handler);
Eric Anholt673a3942008-07-30 12:06:12 -07003321 dev_priv->mm.next_gem_seqno = 1;
3322
Jesse Barnesde151cf2008-11-12 10:03:55 -08003323 /* Old X drivers will take 0-2 for front, back, depth buffers */
3324 dev_priv->fence_reg_start = 3;
3325
Jesse Barnes0f973f22009-01-26 17:10:45 -08003326 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
Jesse Barnesde151cf2008-11-12 10:03:55 -08003327 dev_priv->num_fence_regs = 16;
3328 else
3329 dev_priv->num_fence_regs = 8;
3330
Eric Anholt673a3942008-07-30 12:06:12 -07003331 i915_gem_detect_bit_6_swizzle(dev);
3332}
Dave Airlie71acb5e2008-12-30 20:31:46 +10003333
3334/*
3335 * Create a physically contiguous memory object for this object
3336 * e.g. for cursor + overlay regs
3337 */
3338int i915_gem_init_phys_object(struct drm_device *dev,
3339 int id, int size)
3340{
3341 drm_i915_private_t *dev_priv = dev->dev_private;
3342 struct drm_i915_gem_phys_object *phys_obj;
3343 int ret;
3344
3345 if (dev_priv->mm.phys_objs[id - 1] || !size)
3346 return 0;
3347
3348 phys_obj = drm_calloc(1, sizeof(struct drm_i915_gem_phys_object), DRM_MEM_DRIVER);
3349 if (!phys_obj)
3350 return -ENOMEM;
3351
3352 phys_obj->id = id;
3353
3354 phys_obj->handle = drm_pci_alloc(dev, size, 0, 0xffffffff);
3355 if (!phys_obj->handle) {
3356 ret = -ENOMEM;
3357 goto kfree_obj;
3358 }
3359#ifdef CONFIG_X86
3360 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3361#endif
3362
3363 dev_priv->mm.phys_objs[id - 1] = phys_obj;
3364
3365 return 0;
3366kfree_obj:
3367 drm_free(phys_obj, sizeof(struct drm_i915_gem_phys_object), DRM_MEM_DRIVER);
3368 return ret;
3369}
3370
3371void i915_gem_free_phys_object(struct drm_device *dev, int id)
3372{
3373 drm_i915_private_t *dev_priv = dev->dev_private;
3374 struct drm_i915_gem_phys_object *phys_obj;
3375
3376 if (!dev_priv->mm.phys_objs[id - 1])
3377 return;
3378
3379 phys_obj = dev_priv->mm.phys_objs[id - 1];
3380 if (phys_obj->cur_obj) {
3381 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
3382 }
3383
3384#ifdef CONFIG_X86
3385 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3386#endif
3387 drm_pci_free(dev, phys_obj->handle);
3388 kfree(phys_obj);
3389 dev_priv->mm.phys_objs[id - 1] = NULL;
3390}
3391
3392void i915_gem_free_all_phys_object(struct drm_device *dev)
3393{
3394 int i;
3395
Dave Airlie260883c2009-01-22 17:58:49 +10003396 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
Dave Airlie71acb5e2008-12-30 20:31:46 +10003397 i915_gem_free_phys_object(dev, i);
3398}
3399
3400void i915_gem_detach_phys_object(struct drm_device *dev,
3401 struct drm_gem_object *obj)
3402{
3403 struct drm_i915_gem_object *obj_priv;
3404 int i;
3405 int ret;
3406 int page_count;
3407
3408 obj_priv = obj->driver_private;
3409 if (!obj_priv->phys_obj)
3410 return;
3411
3412 ret = i915_gem_object_get_page_list(obj);
3413 if (ret)
3414 goto out;
3415
3416 page_count = obj->size / PAGE_SIZE;
3417
3418 for (i = 0; i < page_count; i++) {
3419 char *dst = kmap_atomic(obj_priv->page_list[i], KM_USER0);
3420 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
3421
3422 memcpy(dst, src, PAGE_SIZE);
3423 kunmap_atomic(dst, KM_USER0);
3424 }
3425 drm_clflush_pages(obj_priv->page_list, page_count);
3426 drm_agp_chipset_flush(dev);
3427out:
3428 obj_priv->phys_obj->cur_obj = NULL;
3429 obj_priv->phys_obj = NULL;
3430}
3431
3432int
3433i915_gem_attach_phys_object(struct drm_device *dev,
3434 struct drm_gem_object *obj, int id)
3435{
3436 drm_i915_private_t *dev_priv = dev->dev_private;
3437 struct drm_i915_gem_object *obj_priv;
3438 int ret = 0;
3439 int page_count;
3440 int i;
3441
3442 if (id > I915_MAX_PHYS_OBJECT)
3443 return -EINVAL;
3444
3445 obj_priv = obj->driver_private;
3446
3447 if (obj_priv->phys_obj) {
3448 if (obj_priv->phys_obj->id == id)
3449 return 0;
3450 i915_gem_detach_phys_object(dev, obj);
3451 }
3452
3453
3454 /* create a new object */
3455 if (!dev_priv->mm.phys_objs[id - 1]) {
3456 ret = i915_gem_init_phys_object(dev, id,
3457 obj->size);
3458 if (ret) {
Linus Torvaldsaeb565d2009-01-26 10:01:53 -08003459 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
Dave Airlie71acb5e2008-12-30 20:31:46 +10003460 goto out;
3461 }
3462 }
3463
3464 /* bind to the object */
3465 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
3466 obj_priv->phys_obj->cur_obj = obj;
3467
3468 ret = i915_gem_object_get_page_list(obj);
3469 if (ret) {
3470 DRM_ERROR("failed to get page list\n");
3471 goto out;
3472 }
3473
3474 page_count = obj->size / PAGE_SIZE;
3475
3476 for (i = 0; i < page_count; i++) {
3477 char *src = kmap_atomic(obj_priv->page_list[i], KM_USER0);
3478 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
3479
3480 memcpy(dst, src, PAGE_SIZE);
3481 kunmap_atomic(src, KM_USER0);
3482 }
3483
3484 return 0;
3485out:
3486 return ret;
3487}
3488
3489static int
3490i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
3491 struct drm_i915_gem_pwrite *args,
3492 struct drm_file *file_priv)
3493{
3494 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3495 void *obj_addr;
3496 int ret;
3497 char __user *user_data;
3498
3499 user_data = (char __user *) (uintptr_t) args->data_ptr;
3500 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
3501
3502 DRM_ERROR("obj_addr %p, %lld\n", obj_addr, args->size);
3503 ret = copy_from_user(obj_addr, user_data, args->size);
3504 if (ret)
3505 return -EFAULT;
3506
3507 drm_agp_chipset_flush(dev);
3508 return 0;
3509}