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gerrit-public.fairphone.software / fp2-dev / kernel / msm / a2205cd2cbfb8fb217e6036f08773a09d1b6d75e / . / arch / arm / plat-s3c / Kconfig
blob: e6e64968a611cc44c4d778255bda0659ed2624d8 [file] [log] [blame]
Ben Dooksd58153d2007-07-22 16:07:09 +0100[diff] [blame]1# arch/arm/plat-s3c/Kconfig
2#
3# Copyright 2007 Simtec Electronics
4#
5# Licensed under GPLv2
6
7config PLAT_S3C
8 bool
Ben Dooksa08ab632008-10-21 14:06:39 +0100[diff] [blame]9 depends on ARCH_S3C2410 || ARCH_S3C24A0 || ARCH_S3C64XX
Ben Dooksbcae8ae2008-10-21 14:06:32 +0100[diff] [blame]10 default y
Ben Dooksd58153d2007-07-22 16:07:09 +0100[diff] [blame]11 select NO_IOPORT
12 help
13 Base platform code for any Samsung S3C device
14
Ben Dooksb2627582007-07-22 16:09:44 +0100[diff] [blame]15# low-level serial option nodes
16
17config CPU_LLSERIAL_S3C2410_ONLY
18 bool
Ben Dooksbcae8ae2008-10-21 14:06:32 +0100[diff] [blame]19 depends on PLAT_S3C
Ben Dooksb2627582007-07-22 16:09:44 +0100[diff] [blame]20 default y if CPU_LLSERIAL_S3C2410 && !CPU_LLSERIAL_S3C2440
21
22config CPU_LLSERIAL_S3C2440_ONLY
23 bool
Ben Dooksbcae8ae2008-10-21 14:06:32 +0100[diff] [blame]24 depends on PLAT_S3C
Ben Dooksb2627582007-07-22 16:09:44 +0100[diff] [blame]25 default y if CPU_LLSERIAL_S3C2440 && !CPU_LLSERIAL_S3C2410
26
27config CPU_LLSERIAL_S3C2410
28 bool
Ben Dooksbcae8ae2008-10-21 14:06:32 +0100[diff] [blame]29 depends on PLAT_S3C
Ben Dooksb2627582007-07-22 16:09:44 +0100[diff] [blame]30 help
31 Selected if there is an S3C2410 (or register compatible) serial
32 low-level implementation needed
33
34config CPU_LLSERIAL_S3C2440
35 bool
Ben Dooksbcae8ae2008-10-21 14:06:32 +0100[diff] [blame]36 depends on PLAT_S3C
Ben Dooksb2627582007-07-22 16:09:44 +0100[diff] [blame]37 help
38 Selected if there is an S3C2440 (or register compatible) serial
39 low-level implementation needed
40
41# boot configurations
42
Ben Dooksd58153d2007-07-22 16:07:09 +0100[diff] [blame]43comment "Boot options"
44
Ben Dooksa45f8262007-07-22 16:16:51 +0100[diff] [blame]45config S3C_BOOT_WATCHDOG
46 bool "S3C Initialisation watchdog"
Ben Dooksd58153d2007-07-22 16:07:09 +0100[diff] [blame]47 depends on PLAT_S3C && S3C2410_WATCHDOG
48 help
49 Say y to enable the watchdog during the kernel decompression
50 stage. If the kernel fails to uncompress, then the watchdog
51 will trigger a reset and the system should restart.
52
Ben Dooksa45f8262007-07-22 16:16:51 +0100[diff] [blame]53config S3C_BOOT_ERROR_RESET
54 bool "S3C Reboot on decompression error"
Ben Dooksd58153d2007-07-22 16:07:09 +0100[diff] [blame]55 depends on PLAT_S3C
56 help
57 Say y here to use the watchdog to reset the system if the
58 kernel decompressor detects an error during decompression.
59
60comment "Power management"
61
62config S3C2410_PM_DEBUG
63 bool "S3C2410 PM Suspend debug"
64 depends on PLAT_S3C && PM
65 help
66 Say Y here if you want verbose debugging from the PM Suspend and
67 Resume code. See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt>
68 for more information.
69
70config S3C2410_PM_CHECK
71 bool "S3C2410 PM Suspend Memory CRC"
72 depends on PLAT_S3C && PM && CRC32
73 help
74 Enable the PM code's memory area checksum over sleep. This option
75 will generate CRCs of all blocks of memory, and store them before
76 going to sleep. The blocks are then checked on resume for any
77 errors.
78
79 Note, this can take several seconds depending on memory size
80 and CPU speed.
81
82 See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt>
83
84config S3C2410_PM_CHECK_CHUNKSIZE
85 int "S3C2410 PM Suspend CRC Chunksize (KiB)"
86 depends on PLAT_S3C && PM && S3C2410_PM_CHECK
87 default 64
88 help
89 Set the chunksize in Kilobytes of the CRC for checking memory
90 corruption over suspend and resume. A smaller value will mean that
91 the CRC data block will take more memory, but wil identify any
92 faults with better precision.
93
94 See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt>
95
Ben Dooksc7657842007-07-22 16:11:20 +0100[diff] [blame]96config S3C_LOWLEVEL_UART_PORT
97 int "S3C UART to use for low-level messages"
Ben Dooksd58153d2007-07-22 16:07:09 +0100[diff] [blame]98 depends on PLAT_S3C
99 default 0
100 help
101 Choice of which UART port to use for the low-level messages,
102 such as the `Uncompressing...` at start time. The value of
103 this configuration should be between zero and two. The port
104 must have been initialised by the boot-loader before use.
Ben Dooks5b323c72008-10-31 16:14:28 +0000[diff] [blame]105
Ben Dooksefd3a8e2008-10-31 16:14:30 +0000[diff] [blame]106# options for gpiolib support
107
108config S3C_GPIO_SPACE
109 int "Space between gpio banks"
110 default 0
111 help
112 Add a number of spare GPIO entries between each bank for debugging
113 purposes. This allows any problems where an counter overflows from
114 one bank to another to be caught, at the expense of using a little
115 more memory.
116
Ben Dooks8a53bdb2008-10-31 16:14:32 +0000[diff] [blame]117config S3C_GPIO_TRACK
118 bool
119 help
120 Internal configuration option to enable the s3c specific gpio
121 chip tracking if the platform requires it.
122
Ben Dooks21b23662008-10-31 16:14:34 +0000[diff] [blame]123config S3C_GPIO_PULL_UPDOWN
124 bool
125 help
126 Internal configuration to enable the correct GPIO pull helper
127
128config S3C_GPIO_PULL_DOWN
129 bool
130 help
131 Internal configuration to enable the correct GPIO pull helper
132
133config S3C_GPIO_PULL_UP
134 bool
135 help
136 Internal configuration to enable the correct GPIO pull helper
137
138config S3C_GPIO_CFG_S3C24XX
139 bool
140 help
141 Internal configuration to enable S3C24XX style GPIO configuration
142 functions.
143
144config S3C_GPIO_CFG_S3C64XX
145 bool
146 help
147 Internal configuration to enable S3C64XX style GPIO configuration
148 functions.
149
Ben Dooks5b323c72008-10-31 16:14:28 +0000[diff] [blame]150# device definitions to compile in
151
152config S3C_DEV_HSMMC
153 bool
154 depends on PLAT_S3C
155 help
156 Compile in platform device definitions for HSMMC code
Ben Dooksa2205cd2008-10-31 16:14:39 +0000[diff] [blame^]157
158config S3C_DEV_HSMMC1
159 bool
160 depends on PLAT_S3C
161 help
162 Compile in platform device definitions for HSMMC channel 1