Ron Rindjunsky | 1053d35 | 2008-05-05 10:22:43 +0800 | [diff] [blame] | 1 | /****************************************************************************** |
| 2 | * |
| 3 | * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved. |
| 4 | * |
| 5 | * Portions of this file are derived from the ipw3945 project, as well |
| 6 | * as portions of the ieee80211 subsystem header files. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify it |
| 9 | * under the terms of version 2 of the GNU General Public License as |
| 10 | * published by the Free Software Foundation. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 15 | * more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License along with |
| 18 | * this program; if not, write to the Free Software Foundation, Inc., |
| 19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA |
| 20 | * |
| 21 | * The full GNU General Public License is included in this distribution in the |
| 22 | * file called LICENSE. |
| 23 | * |
| 24 | * Contact Information: |
| 25 | * James P. Ketrenos <ipw2100-admin@linux.intel.com> |
| 26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 27 | * |
| 28 | *****************************************************************************/ |
| 29 | |
Tomas Winkler | fd4abac | 2008-05-15 13:54:07 +0800 | [diff] [blame] | 30 | #include <linux/etherdevice.h> |
Ron Rindjunsky | 1053d35 | 2008-05-05 10:22:43 +0800 | [diff] [blame] | 31 | #include <net/mac80211.h> |
| 32 | #include "iwl-eeprom.h" |
| 33 | #include "iwl-dev.h" |
| 34 | #include "iwl-core.h" |
| 35 | #include "iwl-sta.h" |
| 36 | #include "iwl-io.h" |
| 37 | #include "iwl-helpers.h" |
| 38 | |
| 39 | /** |
| 40 | * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] |
| 41 | * |
| 42 | * Does NOT advance any TFD circular buffer read/write indexes |
| 43 | * Does NOT free the TFD itself (which is within circular buffer) |
| 44 | */ |
Ron Rindjunsky | 1646690 | 2008-05-05 10:22:50 +0800 | [diff] [blame] | 45 | int iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq) |
Ron Rindjunsky | 1053d35 | 2008-05-05 10:22:43 +0800 | [diff] [blame] | 46 | { |
| 47 | struct iwl_tfd_frame *bd_tmp = (struct iwl_tfd_frame *)&txq->bd[0]; |
| 48 | struct iwl_tfd_frame *bd = &bd_tmp[txq->q.read_ptr]; |
| 49 | struct pci_dev *dev = priv->pci_dev; |
| 50 | int i; |
| 51 | int counter = 0; |
| 52 | int index, is_odd; |
| 53 | |
| 54 | /* Host command buffers stay mapped in memory, nothing to clean */ |
| 55 | if (txq->q.id == IWL_CMD_QUEUE_NUM) |
| 56 | return 0; |
| 57 | |
| 58 | /* Sanity check on number of chunks */ |
| 59 | counter = IWL_GET_BITS(*bd, num_tbs); |
| 60 | if (counter > MAX_NUM_OF_TBS) { |
| 61 | IWL_ERROR("Too many chunks: %i\n", counter); |
| 62 | /* @todo issue fatal error, it is quite serious situation */ |
| 63 | return 0; |
| 64 | } |
| 65 | |
| 66 | /* Unmap chunks, if any. |
| 67 | * TFD info for odd chunks is different format than for even chunks. */ |
| 68 | for (i = 0; i < counter; i++) { |
| 69 | index = i / 2; |
| 70 | is_odd = i & 0x1; |
| 71 | |
| 72 | if (is_odd) |
| 73 | pci_unmap_single( |
| 74 | dev, |
| 75 | IWL_GET_BITS(bd->pa[index], tb2_addr_lo16) | |
| 76 | (IWL_GET_BITS(bd->pa[index], |
| 77 | tb2_addr_hi20) << 16), |
| 78 | IWL_GET_BITS(bd->pa[index], tb2_len), |
| 79 | PCI_DMA_TODEVICE); |
| 80 | |
| 81 | else if (i > 0) |
| 82 | pci_unmap_single(dev, |
| 83 | le32_to_cpu(bd->pa[index].tb1_addr), |
| 84 | IWL_GET_BITS(bd->pa[index], tb1_len), |
| 85 | PCI_DMA_TODEVICE); |
| 86 | |
| 87 | /* Free SKB, if any, for this chunk */ |
| 88 | if (txq->txb[txq->q.read_ptr].skb[i]) { |
| 89 | struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[i]; |
| 90 | |
| 91 | dev_kfree_skb(skb); |
| 92 | txq->txb[txq->q.read_ptr].skb[i] = NULL; |
| 93 | } |
| 94 | } |
| 95 | return 0; |
| 96 | } |
| 97 | EXPORT_SYMBOL(iwl_hw_txq_free_tfd); |
| 98 | |
Tomas Winkler | fd4abac | 2008-05-15 13:54:07 +0800 | [diff] [blame] | 99 | |
| 100 | int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *ptr, |
| 101 | dma_addr_t addr, u16 len) |
| 102 | { |
| 103 | int index, is_odd; |
| 104 | struct iwl_tfd_frame *tfd = ptr; |
| 105 | u32 num_tbs = IWL_GET_BITS(*tfd, num_tbs); |
| 106 | |
| 107 | /* Each TFD can point to a maximum 20 Tx buffers */ |
| 108 | if ((num_tbs >= MAX_NUM_OF_TBS) || (num_tbs < 0)) { |
| 109 | IWL_ERROR("Error can not send more than %d chunks\n", |
| 110 | MAX_NUM_OF_TBS); |
| 111 | return -EINVAL; |
| 112 | } |
| 113 | |
| 114 | index = num_tbs / 2; |
| 115 | is_odd = num_tbs & 0x1; |
| 116 | |
| 117 | if (!is_odd) { |
| 118 | tfd->pa[index].tb1_addr = cpu_to_le32(addr); |
| 119 | IWL_SET_BITS(tfd->pa[index], tb1_addr_hi, |
| 120 | iwl_get_dma_hi_address(addr)); |
| 121 | IWL_SET_BITS(tfd->pa[index], tb1_len, len); |
| 122 | } else { |
| 123 | IWL_SET_BITS(tfd->pa[index], tb2_addr_lo16, |
| 124 | (u32) (addr & 0xffff)); |
| 125 | IWL_SET_BITS(tfd->pa[index], tb2_addr_hi20, addr >> 16); |
| 126 | IWL_SET_BITS(tfd->pa[index], tb2_len, len); |
| 127 | } |
| 128 | |
| 129 | IWL_SET_BITS(*tfd, num_tbs, num_tbs + 1); |
| 130 | |
| 131 | return 0; |
| 132 | } |
| 133 | EXPORT_SYMBOL(iwl_hw_txq_attach_buf_to_tfd); |
| 134 | |
| 135 | /** |
| 136 | * iwl_txq_update_write_ptr - Send new write index to hardware |
| 137 | */ |
| 138 | int iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq) |
| 139 | { |
| 140 | u32 reg = 0; |
| 141 | int ret = 0; |
| 142 | int txq_id = txq->q.id; |
| 143 | |
| 144 | if (txq->need_update == 0) |
| 145 | return ret; |
| 146 | |
| 147 | /* if we're trying to save power */ |
| 148 | if (test_bit(STATUS_POWER_PMI, &priv->status)) { |
| 149 | /* wake up nic if it's powered down ... |
| 150 | * uCode will wake up, and interrupt us again, so next |
| 151 | * time we'll skip this part. */ |
| 152 | reg = iwl_read32(priv, CSR_UCODE_DRV_GP1); |
| 153 | |
| 154 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { |
| 155 | IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg); |
| 156 | iwl_set_bit(priv, CSR_GP_CNTRL, |
| 157 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
| 158 | return ret; |
| 159 | } |
| 160 | |
| 161 | /* restore this queue's parameters in nic hardware. */ |
| 162 | ret = iwl_grab_nic_access(priv); |
| 163 | if (ret) |
| 164 | return ret; |
| 165 | iwl_write_direct32(priv, HBUS_TARG_WRPTR, |
| 166 | txq->q.write_ptr | (txq_id << 8)); |
| 167 | iwl_release_nic_access(priv); |
| 168 | |
| 169 | /* else not in power-save mode, uCode will never sleep when we're |
| 170 | * trying to tx (during RFKILL, we're not trying to tx). */ |
| 171 | } else |
| 172 | iwl_write32(priv, HBUS_TARG_WRPTR, |
| 173 | txq->q.write_ptr | (txq_id << 8)); |
| 174 | |
| 175 | txq->need_update = 0; |
| 176 | |
| 177 | return ret; |
| 178 | } |
| 179 | EXPORT_SYMBOL(iwl_txq_update_write_ptr); |
| 180 | |
| 181 | |
Ron Rindjunsky | 1053d35 | 2008-05-05 10:22:43 +0800 | [diff] [blame] | 182 | /** |
| 183 | * iwl_tx_queue_free - Deallocate DMA queue. |
| 184 | * @txq: Transmit queue to deallocate. |
| 185 | * |
| 186 | * Empty queue by removing and destroying all BD's. |
| 187 | * Free all buffers. |
| 188 | * 0-fill, but do not free "txq" descriptor structure. |
| 189 | */ |
Ron Rindjunsky | 1646690 | 2008-05-05 10:22:50 +0800 | [diff] [blame] | 190 | static void iwl_tx_queue_free(struct iwl_priv *priv, struct iwl_tx_queue *txq) |
Ron Rindjunsky | 1053d35 | 2008-05-05 10:22:43 +0800 | [diff] [blame] | 191 | { |
Tomas Winkler | 443cfd4 | 2008-05-15 13:53:57 +0800 | [diff] [blame] | 192 | struct iwl_queue *q = &txq->q; |
Ron Rindjunsky | 1053d35 | 2008-05-05 10:22:43 +0800 | [diff] [blame] | 193 | struct pci_dev *dev = priv->pci_dev; |
| 194 | int len; |
| 195 | |
| 196 | if (q->n_bd == 0) |
| 197 | return; |
| 198 | |
| 199 | /* first, empty all BD's */ |
| 200 | for (; q->write_ptr != q->read_ptr; |
| 201 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) |
| 202 | iwl_hw_txq_free_tfd(priv, txq); |
| 203 | |
| 204 | len = sizeof(struct iwl_cmd) * q->n_window; |
| 205 | if (q->id == IWL_CMD_QUEUE_NUM) |
| 206 | len += IWL_MAX_SCAN_SIZE; |
| 207 | |
| 208 | /* De-alloc array of command/tx buffers */ |
| 209 | pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd); |
| 210 | |
| 211 | /* De-alloc circular buffer of TFDs */ |
| 212 | if (txq->q.n_bd) |
| 213 | pci_free_consistent(dev, sizeof(struct iwl_tfd_frame) * |
| 214 | txq->q.n_bd, txq->bd, txq->q.dma_addr); |
| 215 | |
| 216 | /* De-alloc array of per-TFD driver data */ |
| 217 | kfree(txq->txb); |
| 218 | txq->txb = NULL; |
| 219 | |
| 220 | /* 0-fill queue descriptor structure */ |
| 221 | memset(txq, 0, sizeof(*txq)); |
| 222 | } |
| 223 | |
Tomas Winkler | fd4abac | 2008-05-15 13:54:07 +0800 | [diff] [blame] | 224 | /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** |
| 225 | * DMA services |
| 226 | * |
| 227 | * Theory of operation |
| 228 | * |
| 229 | * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer |
| 230 | * of buffer descriptors, each of which points to one or more data buffers for |
| 231 | * the device to read from or fill. Driver and device exchange status of each |
| 232 | * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty |
| 233 | * entries in each circular buffer, to protect against confusing empty and full |
| 234 | * queue states. |
| 235 | * |
| 236 | * The device reads or writes the data in the queues via the device's several |
| 237 | * DMA/FIFO channels. Each queue is mapped to a single DMA channel. |
| 238 | * |
| 239 | * For Tx queue, there are low mark and high mark limits. If, after queuing |
| 240 | * the packet for Tx, free space become < low mark, Tx queue stopped. When |
| 241 | * reclaiming packets (on 'tx done IRQ), if free space become > high mark, |
| 242 | * Tx queue resumed. |
| 243 | * |
| 244 | * See more detailed info in iwl-4965-hw.h. |
| 245 | ***************************************************/ |
| 246 | |
| 247 | int iwl_queue_space(const struct iwl_queue *q) |
| 248 | { |
| 249 | int s = q->read_ptr - q->write_ptr; |
| 250 | |
| 251 | if (q->read_ptr > q->write_ptr) |
| 252 | s -= q->n_bd; |
| 253 | |
| 254 | if (s <= 0) |
| 255 | s += q->n_window; |
| 256 | /* keep some reserve to not confuse empty and full situations */ |
| 257 | s -= 2; |
| 258 | if (s < 0) |
| 259 | s = 0; |
| 260 | return s; |
| 261 | } |
| 262 | EXPORT_SYMBOL(iwl_queue_space); |
| 263 | |
| 264 | |
Ron Rindjunsky | 1053d35 | 2008-05-05 10:22:43 +0800 | [diff] [blame] | 265 | /** |
Ron Rindjunsky | 1053d35 | 2008-05-05 10:22:43 +0800 | [diff] [blame] | 266 | * iwl_queue_init - Initialize queue's high/low-water and read/write indexes |
| 267 | */ |
Tomas Winkler | 443cfd4 | 2008-05-15 13:53:57 +0800 | [diff] [blame] | 268 | static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q, |
Ron Rindjunsky | 1053d35 | 2008-05-05 10:22:43 +0800 | [diff] [blame] | 269 | int count, int slots_num, u32 id) |
| 270 | { |
| 271 | q->n_bd = count; |
| 272 | q->n_window = slots_num; |
| 273 | q->id = id; |
| 274 | |
| 275 | /* count must be power-of-two size, otherwise iwl_queue_inc_wrap |
| 276 | * and iwl_queue_dec_wrap are broken. */ |
| 277 | BUG_ON(!is_power_of_2(count)); |
| 278 | |
| 279 | /* slots_num must be power-of-two size, otherwise |
| 280 | * get_cmd_index is broken. */ |
| 281 | BUG_ON(!is_power_of_2(slots_num)); |
| 282 | |
| 283 | q->low_mark = q->n_window / 4; |
| 284 | if (q->low_mark < 4) |
| 285 | q->low_mark = 4; |
| 286 | |
| 287 | q->high_mark = q->n_window / 8; |
| 288 | if (q->high_mark < 2) |
| 289 | q->high_mark = 2; |
| 290 | |
| 291 | q->write_ptr = q->read_ptr = 0; |
| 292 | |
| 293 | return 0; |
| 294 | } |
| 295 | |
| 296 | /** |
| 297 | * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue |
| 298 | */ |
| 299 | static int iwl_tx_queue_alloc(struct iwl_priv *priv, |
Ron Rindjunsky | 1646690 | 2008-05-05 10:22:50 +0800 | [diff] [blame] | 300 | struct iwl_tx_queue *txq, u32 id) |
Ron Rindjunsky | 1053d35 | 2008-05-05 10:22:43 +0800 | [diff] [blame] | 301 | { |
| 302 | struct pci_dev *dev = priv->pci_dev; |
| 303 | |
| 304 | /* Driver private data, only for Tx (not command) queues, |
| 305 | * not shared with device. */ |
| 306 | if (id != IWL_CMD_QUEUE_NUM) { |
| 307 | txq->txb = kmalloc(sizeof(txq->txb[0]) * |
| 308 | TFD_QUEUE_SIZE_MAX, GFP_KERNEL); |
| 309 | if (!txq->txb) { |
| 310 | IWL_ERROR("kmalloc for auxiliary BD " |
| 311 | "structures failed\n"); |
| 312 | goto error; |
| 313 | } |
| 314 | } else |
| 315 | txq->txb = NULL; |
| 316 | |
| 317 | /* Circular buffer of transmit frame descriptors (TFDs), |
| 318 | * shared with device */ |
| 319 | txq->bd = pci_alloc_consistent(dev, |
| 320 | sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX, |
| 321 | &txq->q.dma_addr); |
| 322 | |
| 323 | if (!txq->bd) { |
| 324 | IWL_ERROR("pci_alloc_consistent(%zd) failed\n", |
| 325 | sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX); |
| 326 | goto error; |
| 327 | } |
| 328 | txq->q.id = id; |
| 329 | |
| 330 | return 0; |
| 331 | |
| 332 | error: |
| 333 | kfree(txq->txb); |
| 334 | txq->txb = NULL; |
| 335 | |
| 336 | return -ENOMEM; |
| 337 | } |
| 338 | |
| 339 | /* |
| 340 | * Tell nic where to find circular buffer of Tx Frame Descriptors for |
| 341 | * given Tx queue, and enable the DMA channel used for that queue. |
| 342 | * |
| 343 | * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA |
| 344 | * channels supported in hardware. |
| 345 | */ |
| 346 | static int iwl_hw_tx_queue_init(struct iwl_priv *priv, |
Ron Rindjunsky | 1646690 | 2008-05-05 10:22:50 +0800 | [diff] [blame] | 347 | struct iwl_tx_queue *txq) |
Ron Rindjunsky | 1053d35 | 2008-05-05 10:22:43 +0800 | [diff] [blame] | 348 | { |
| 349 | int rc; |
| 350 | unsigned long flags; |
| 351 | int txq_id = txq->q.id; |
| 352 | |
| 353 | spin_lock_irqsave(&priv->lock, flags); |
| 354 | rc = iwl_grab_nic_access(priv); |
| 355 | if (rc) { |
| 356 | spin_unlock_irqrestore(&priv->lock, flags); |
| 357 | return rc; |
| 358 | } |
| 359 | |
| 360 | /* Circular buffer (TFD queue in DRAM) physical base address */ |
| 361 | iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id), |
| 362 | txq->q.dma_addr >> 8); |
| 363 | |
| 364 | /* Enable DMA channel, using same id as for TFD queue */ |
| 365 | iwl_write_direct32( |
| 366 | priv, FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), |
| 367 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | |
| 368 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL); |
| 369 | iwl_release_nic_access(priv); |
| 370 | spin_unlock_irqrestore(&priv->lock, flags); |
| 371 | |
| 372 | return 0; |
| 373 | } |
| 374 | |
| 375 | /** |
| 376 | * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue |
| 377 | */ |
| 378 | static int iwl_tx_queue_init(struct iwl_priv *priv, |
Ron Rindjunsky | 1646690 | 2008-05-05 10:22:50 +0800 | [diff] [blame] | 379 | struct iwl_tx_queue *txq, |
Ron Rindjunsky | 1053d35 | 2008-05-05 10:22:43 +0800 | [diff] [blame] | 380 | int slots_num, u32 txq_id) |
| 381 | { |
| 382 | struct pci_dev *dev = priv->pci_dev; |
| 383 | int len; |
| 384 | int rc = 0; |
| 385 | |
| 386 | /* |
| 387 | * Alloc buffer array for commands (Tx or other types of commands). |
| 388 | * For the command queue (#4), allocate command space + one big |
| 389 | * command for scan, since scan command is very huge; the system will |
| 390 | * not have two scans at the same time, so only one is needed. |
| 391 | * For normal Tx queues (all other queues), no super-size command |
| 392 | * space is needed. |
| 393 | */ |
| 394 | len = sizeof(struct iwl_cmd) * slots_num; |
| 395 | if (txq_id == IWL_CMD_QUEUE_NUM) |
| 396 | len += IWL_MAX_SCAN_SIZE; |
| 397 | txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd); |
| 398 | if (!txq->cmd) |
| 399 | return -ENOMEM; |
| 400 | |
| 401 | /* Alloc driver data array and TFD circular buffer */ |
| 402 | rc = iwl_tx_queue_alloc(priv, txq, txq_id); |
| 403 | if (rc) { |
| 404 | pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd); |
| 405 | |
| 406 | return -ENOMEM; |
| 407 | } |
| 408 | txq->need_update = 0; |
| 409 | |
| 410 | /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise |
| 411 | * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ |
| 412 | BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); |
| 413 | |
| 414 | /* Initialize queue's high/low-water marks, and head/tail indexes */ |
| 415 | iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id); |
| 416 | |
| 417 | /* Tell device where to find queue */ |
| 418 | iwl_hw_tx_queue_init(priv, txq); |
| 419 | |
| 420 | return 0; |
| 421 | } |
Tomas Winkler | da1bc45 | 2008-05-29 16:35:00 +0800 | [diff] [blame] | 422 | /** |
| 423 | * iwl_hw_txq_ctx_free - Free TXQ Context |
| 424 | * |
| 425 | * Destroy all TX DMA queues and structures |
| 426 | */ |
| 427 | void iwl_hw_txq_ctx_free(struct iwl_priv *priv) |
| 428 | { |
| 429 | int txq_id; |
| 430 | |
| 431 | /* Tx queues */ |
| 432 | for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) |
| 433 | iwl_tx_queue_free(priv, &priv->txq[txq_id]); |
| 434 | |
| 435 | /* Keep-warm buffer */ |
| 436 | iwl_kw_free(priv); |
| 437 | } |
| 438 | EXPORT_SYMBOL(iwl_hw_txq_ctx_free); |
| 439 | |
Ron Rindjunsky | 1053d35 | 2008-05-05 10:22:43 +0800 | [diff] [blame] | 440 | |
| 441 | /** |
| 442 | * iwl_txq_ctx_reset - Reset TX queue context |
| 443 | * Destroys all DMA structures and initialise them again |
| 444 | * |
| 445 | * @param priv |
| 446 | * @return error code |
| 447 | */ |
| 448 | int iwl_txq_ctx_reset(struct iwl_priv *priv) |
| 449 | { |
| 450 | int ret = 0; |
| 451 | int txq_id, slots_num; |
Tomas Winkler | da1bc45 | 2008-05-29 16:35:00 +0800 | [diff] [blame] | 452 | unsigned long flags; |
Ron Rindjunsky | 1053d35 | 2008-05-05 10:22:43 +0800 | [diff] [blame] | 453 | |
| 454 | iwl_kw_free(priv); |
| 455 | |
| 456 | /* Free all tx/cmd queues and keep-warm buffer */ |
| 457 | iwl_hw_txq_ctx_free(priv); |
| 458 | |
| 459 | /* Alloc keep-warm buffer */ |
| 460 | ret = iwl_kw_alloc(priv); |
| 461 | if (ret) { |
| 462 | IWL_ERROR("Keep Warm allocation failed"); |
| 463 | goto error_kw; |
| 464 | } |
Tomas Winkler | da1bc45 | 2008-05-29 16:35:00 +0800 | [diff] [blame] | 465 | spin_lock_irqsave(&priv->lock, flags); |
| 466 | ret = iwl_grab_nic_access(priv); |
| 467 | if (unlikely(ret)) { |
| 468 | spin_unlock_irqrestore(&priv->lock, flags); |
| 469 | goto error_reset; |
| 470 | } |
Ron Rindjunsky | 1053d35 | 2008-05-05 10:22:43 +0800 | [diff] [blame] | 471 | |
| 472 | /* Turn off all Tx DMA fifos */ |
Tomas Winkler | da1bc45 | 2008-05-29 16:35:00 +0800 | [diff] [blame] | 473 | priv->cfg->ops->lib->txq_set_sched(priv, 0); |
| 474 | |
| 475 | iwl_release_nic_access(priv); |
| 476 | spin_unlock_irqrestore(&priv->lock, flags); |
| 477 | |
Ron Rindjunsky | 1053d35 | 2008-05-05 10:22:43 +0800 | [diff] [blame] | 478 | |
| 479 | /* Tell nic where to find the keep-warm buffer */ |
| 480 | ret = iwl_kw_init(priv); |
| 481 | if (ret) { |
| 482 | IWL_ERROR("kw_init failed\n"); |
| 483 | goto error_reset; |
| 484 | } |
| 485 | |
Tomas Winkler | da1bc45 | 2008-05-29 16:35:00 +0800 | [diff] [blame] | 486 | /* Alloc and init all Tx queues, including the command queue (#4) */ |
Ron Rindjunsky | 1053d35 | 2008-05-05 10:22:43 +0800 | [diff] [blame] | 487 | for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) { |
| 488 | slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ? |
| 489 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; |
| 490 | ret = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num, |
| 491 | txq_id); |
| 492 | if (ret) { |
| 493 | IWL_ERROR("Tx %d queue init failed\n", txq_id); |
| 494 | goto error; |
| 495 | } |
| 496 | } |
| 497 | |
| 498 | return ret; |
| 499 | |
| 500 | error: |
| 501 | iwl_hw_txq_ctx_free(priv); |
| 502 | error_reset: |
| 503 | iwl_kw_free(priv); |
| 504 | error_kw: |
| 505 | return ret; |
| 506 | } |
Tomas Winkler | da1bc45 | 2008-05-29 16:35:00 +0800 | [diff] [blame] | 507 | /** |
| 508 | * iwl_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory |
| 509 | */ |
| 510 | void iwl_txq_ctx_stop(struct iwl_priv *priv) |
| 511 | { |
| 512 | |
| 513 | int txq_id; |
| 514 | unsigned long flags; |
| 515 | |
| 516 | |
| 517 | /* Turn off all Tx DMA fifos */ |
| 518 | spin_lock_irqsave(&priv->lock, flags); |
| 519 | if (iwl_grab_nic_access(priv)) { |
| 520 | spin_unlock_irqrestore(&priv->lock, flags); |
| 521 | return; |
| 522 | } |
| 523 | |
| 524 | priv->cfg->ops->lib->txq_set_sched(priv, 0); |
| 525 | |
| 526 | /* Stop each Tx DMA channel, and wait for it to be idle */ |
| 527 | for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) { |
| 528 | iwl_write_direct32(priv, |
| 529 | FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), 0x0); |
| 530 | iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG, |
| 531 | FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE |
| 532 | (txq_id), 200); |
| 533 | } |
| 534 | iwl_release_nic_access(priv); |
| 535 | spin_unlock_irqrestore(&priv->lock, flags); |
| 536 | |
| 537 | /* Deallocate memory for all Tx queues */ |
| 538 | iwl_hw_txq_ctx_free(priv); |
| 539 | } |
| 540 | EXPORT_SYMBOL(iwl_txq_ctx_stop); |
Tomas Winkler | fd4abac | 2008-05-15 13:54:07 +0800 | [diff] [blame] | 541 | |
| 542 | /* |
| 543 | * handle build REPLY_TX command notification. |
| 544 | */ |
| 545 | static void iwl_tx_cmd_build_basic(struct iwl_priv *priv, |
| 546 | struct iwl_tx_cmd *tx_cmd, |
Johannes Berg | e039fa4 | 2008-05-15 12:55:29 +0200 | [diff] [blame] | 547 | struct ieee80211_tx_info *info, |
Tomas Winkler | fd4abac | 2008-05-15 13:54:07 +0800 | [diff] [blame] | 548 | struct ieee80211_hdr *hdr, |
| 549 | int is_unicast, u8 std_id) |
| 550 | { |
| 551 | u16 fc = le16_to_cpu(hdr->frame_control); |
| 552 | __le32 tx_flags = tx_cmd->tx_flags; |
| 553 | |
| 554 | tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; |
Johannes Berg | e039fa4 | 2008-05-15 12:55:29 +0200 | [diff] [blame] | 555 | if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { |
Tomas Winkler | fd4abac | 2008-05-15 13:54:07 +0800 | [diff] [blame] | 556 | tx_flags |= TX_CMD_FLG_ACK_MSK; |
| 557 | if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) |
| 558 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; |
| 559 | if (ieee80211_is_probe_response(fc) && |
| 560 | !(le16_to_cpu(hdr->seq_ctrl) & 0xf)) |
| 561 | tx_flags |= TX_CMD_FLG_TSF_MSK; |
| 562 | } else { |
| 563 | tx_flags &= (~TX_CMD_FLG_ACK_MSK); |
| 564 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; |
| 565 | } |
| 566 | |
| 567 | if (ieee80211_is_back_request(fc)) |
| 568 | tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK; |
| 569 | |
| 570 | |
| 571 | tx_cmd->sta_id = std_id; |
| 572 | if (ieee80211_get_morefrag(hdr)) |
| 573 | tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK; |
| 574 | |
| 575 | if (ieee80211_is_qos_data(fc)) { |
| 576 | u8 *qc = ieee80211_get_qos_ctrl(hdr, ieee80211_get_hdrlen(fc)); |
| 577 | tx_cmd->tid_tspec = qc[0] & 0xf; |
| 578 | tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK; |
| 579 | } else { |
| 580 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; |
| 581 | } |
| 582 | |
Johannes Berg | e039fa4 | 2008-05-15 12:55:29 +0200 | [diff] [blame] | 583 | if (info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) { |
Tomas Winkler | fd4abac | 2008-05-15 13:54:07 +0800 | [diff] [blame] | 584 | tx_flags |= TX_CMD_FLG_RTS_MSK; |
| 585 | tx_flags &= ~TX_CMD_FLG_CTS_MSK; |
Johannes Berg | e039fa4 | 2008-05-15 12:55:29 +0200 | [diff] [blame] | 586 | } else if (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT) { |
Tomas Winkler | fd4abac | 2008-05-15 13:54:07 +0800 | [diff] [blame] | 587 | tx_flags &= ~TX_CMD_FLG_RTS_MSK; |
| 588 | tx_flags |= TX_CMD_FLG_CTS_MSK; |
| 589 | } |
| 590 | |
| 591 | if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK)) |
| 592 | tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK; |
| 593 | |
| 594 | tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK); |
| 595 | if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) { |
| 596 | if ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_ASSOC_REQ || |
| 597 | (fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_REASSOC_REQ) |
| 598 | tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3); |
| 599 | else |
| 600 | tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2); |
| 601 | } else { |
| 602 | tx_cmd->timeout.pm_frame_timeout = 0; |
| 603 | } |
| 604 | |
| 605 | tx_cmd->driver_txop = 0; |
| 606 | tx_cmd->tx_flags = tx_flags; |
| 607 | tx_cmd->next_frame_len = 0; |
| 608 | } |
| 609 | |
| 610 | #define RTS_HCCA_RETRY_LIMIT 3 |
| 611 | #define RTS_DFAULT_RETRY_LIMIT 60 |
| 612 | |
| 613 | static void iwl_tx_cmd_build_rate(struct iwl_priv *priv, |
| 614 | struct iwl_tx_cmd *tx_cmd, |
Johannes Berg | e039fa4 | 2008-05-15 12:55:29 +0200 | [diff] [blame] | 615 | struct ieee80211_tx_info *info, |
Tomas Winkler | fd4abac | 2008-05-15 13:54:07 +0800 | [diff] [blame] | 616 | u16 fc, int sta_id, |
| 617 | int is_hcca) |
| 618 | { |
| 619 | u8 rts_retry_limit = 0; |
| 620 | u8 data_retry_limit = 0; |
| 621 | u8 rate_plcp; |
| 622 | u16 rate_flags = 0; |
Johannes Berg | 2e92e6f | 2008-05-15 12:55:27 +0200 | [diff] [blame] | 623 | int rate_idx; |
| 624 | |
Johannes Berg | e039fa4 | 2008-05-15 12:55:29 +0200 | [diff] [blame] | 625 | rate_idx = min(ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xffff, |
Johannes Berg | 2e92e6f | 2008-05-15 12:55:27 +0200 | [diff] [blame] | 626 | IWL_RATE_COUNT - 1); |
Tomas Winkler | fd4abac | 2008-05-15 13:54:07 +0800 | [diff] [blame] | 627 | |
| 628 | rate_plcp = iwl_rates[rate_idx].plcp; |
| 629 | |
| 630 | rts_retry_limit = (is_hcca) ? |
| 631 | RTS_HCCA_RETRY_LIMIT : RTS_DFAULT_RETRY_LIMIT; |
| 632 | |
| 633 | if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE)) |
| 634 | rate_flags |= RATE_MCS_CCK_MSK; |
| 635 | |
| 636 | |
| 637 | if (ieee80211_is_probe_response(fc)) { |
| 638 | data_retry_limit = 3; |
| 639 | if (data_retry_limit < rts_retry_limit) |
| 640 | rts_retry_limit = data_retry_limit; |
| 641 | } else |
| 642 | data_retry_limit = IWL_DEFAULT_TX_RETRY; |
| 643 | |
| 644 | if (priv->data_retry_limit != -1) |
| 645 | data_retry_limit = priv->data_retry_limit; |
| 646 | |
| 647 | |
| 648 | if (ieee80211_is_data(fc)) { |
| 649 | tx_cmd->initial_rate_index = 0; |
| 650 | tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK; |
| 651 | } else { |
| 652 | switch (fc & IEEE80211_FCTL_STYPE) { |
| 653 | case IEEE80211_STYPE_AUTH: |
| 654 | case IEEE80211_STYPE_DEAUTH: |
| 655 | case IEEE80211_STYPE_ASSOC_REQ: |
| 656 | case IEEE80211_STYPE_REASSOC_REQ: |
| 657 | if (tx_cmd->tx_flags & TX_CMD_FLG_RTS_MSK) { |
| 658 | tx_cmd->tx_flags &= ~TX_CMD_FLG_RTS_MSK; |
| 659 | tx_cmd->tx_flags |= TX_CMD_FLG_CTS_MSK; |
| 660 | } |
| 661 | break; |
| 662 | default: |
| 663 | break; |
| 664 | } |
| 665 | |
| 666 | /* Alternate between antenna A and B for successive frames */ |
| 667 | if (priv->use_ant_b_for_management_frame) { |
| 668 | priv->use_ant_b_for_management_frame = 0; |
| 669 | rate_flags |= RATE_MCS_ANT_B_MSK; |
| 670 | } else { |
| 671 | priv->use_ant_b_for_management_frame = 1; |
| 672 | rate_flags |= RATE_MCS_ANT_A_MSK; |
| 673 | } |
| 674 | } |
| 675 | |
| 676 | tx_cmd->rts_retry_limit = rts_retry_limit; |
| 677 | tx_cmd->data_retry_limit = data_retry_limit; |
| 678 | tx_cmd->rate_n_flags = iwl4965_hw_set_rate_n_flags(rate_plcp, rate_flags); |
| 679 | } |
| 680 | |
| 681 | static void iwl_tx_cmd_build_hwcrypto(struct iwl_priv *priv, |
Johannes Berg | e039fa4 | 2008-05-15 12:55:29 +0200 | [diff] [blame] | 682 | struct ieee80211_tx_info *info, |
Tomas Winkler | fd4abac | 2008-05-15 13:54:07 +0800 | [diff] [blame] | 683 | struct iwl_tx_cmd *tx_cmd, |
| 684 | struct sk_buff *skb_frag, |
| 685 | int sta_id) |
| 686 | { |
Johannes Berg | e039fa4 | 2008-05-15 12:55:29 +0200 | [diff] [blame] | 687 | struct ieee80211_key_conf *keyconf = info->control.hw_key; |
Tomas Winkler | fd4abac | 2008-05-15 13:54:07 +0800 | [diff] [blame] | 688 | |
Emmanuel Grumbach | ccc038a | 2008-05-15 13:54:09 +0800 | [diff] [blame] | 689 | switch (keyconf->alg) { |
Tomas Winkler | fd4abac | 2008-05-15 13:54:07 +0800 | [diff] [blame] | 690 | case ALG_CCMP: |
| 691 | tx_cmd->sec_ctl = TX_CMD_SEC_CCM; |
Emmanuel Grumbach | ccc038a | 2008-05-15 13:54:09 +0800 | [diff] [blame] | 692 | memcpy(tx_cmd->key, keyconf->key, keyconf->keylen); |
Johannes Berg | e039fa4 | 2008-05-15 12:55:29 +0200 | [diff] [blame] | 693 | if (info->flags & IEEE80211_TX_CTL_AMPDU) |
Tomas Winkler | fd4abac | 2008-05-15 13:54:07 +0800 | [diff] [blame] | 694 | tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK; |
| 695 | IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n"); |
| 696 | break; |
| 697 | |
| 698 | case ALG_TKIP: |
| 699 | tx_cmd->sec_ctl = TX_CMD_SEC_TKIP; |
Emmanuel Grumbach | ccc038a | 2008-05-15 13:54:09 +0800 | [diff] [blame] | 700 | ieee80211_get_tkip_key(keyconf, skb_frag, |
Tomas Winkler | fd4abac | 2008-05-15 13:54:07 +0800 | [diff] [blame] | 701 | IEEE80211_TKIP_P2_KEY, tx_cmd->key); |
| 702 | IWL_DEBUG_TX("tx_cmd with tkip hwcrypto\n"); |
| 703 | break; |
| 704 | |
| 705 | case ALG_WEP: |
Tomas Winkler | fd4abac | 2008-05-15 13:54:07 +0800 | [diff] [blame] | 706 | tx_cmd->sec_ctl |= (TX_CMD_SEC_WEP | |
Emmanuel Grumbach | ccc038a | 2008-05-15 13:54:09 +0800 | [diff] [blame] | 707 | (keyconf->keyidx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT); |
| 708 | |
| 709 | if (keyconf->keylen == WEP_KEY_LEN_128) |
| 710 | tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128; |
| 711 | |
| 712 | memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen); |
Tomas Winkler | fd4abac | 2008-05-15 13:54:07 +0800 | [diff] [blame] | 713 | |
| 714 | IWL_DEBUG_TX("Configuring packet for WEP encryption " |
Emmanuel Grumbach | ccc038a | 2008-05-15 13:54:09 +0800 | [diff] [blame] | 715 | "with key %d\n", keyconf->keyidx); |
Tomas Winkler | fd4abac | 2008-05-15 13:54:07 +0800 | [diff] [blame] | 716 | break; |
| 717 | |
| 718 | default: |
Emmanuel Grumbach | ccc038a | 2008-05-15 13:54:09 +0800 | [diff] [blame] | 719 | printk(KERN_ERR "Unknown encode alg %d\n", keyconf->alg); |
Tomas Winkler | fd4abac | 2008-05-15 13:54:07 +0800 | [diff] [blame] | 720 | break; |
| 721 | } |
| 722 | } |
| 723 | |
| 724 | static void iwl_update_tx_stats(struct iwl_priv *priv, u16 fc, u16 len) |
| 725 | { |
| 726 | /* 0 - mgmt, 1 - cnt, 2 - data */ |
| 727 | int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2; |
| 728 | priv->tx_stats[idx].cnt++; |
| 729 | priv->tx_stats[idx].bytes += len; |
| 730 | } |
| 731 | |
| 732 | /* |
| 733 | * start REPLY_TX command process |
| 734 | */ |
Johannes Berg | e039fa4 | 2008-05-15 12:55:29 +0200 | [diff] [blame] | 735 | int iwl_tx_skb(struct iwl_priv *priv, struct sk_buff *skb) |
Tomas Winkler | fd4abac | 2008-05-15 13:54:07 +0800 | [diff] [blame] | 736 | { |
| 737 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
Johannes Berg | e039fa4 | 2008-05-15 12:55:29 +0200 | [diff] [blame] | 738 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
Tomas Winkler | fd4abac | 2008-05-15 13:54:07 +0800 | [diff] [blame] | 739 | struct iwl_tfd_frame *tfd; |
| 740 | u32 *control_flags; |
Johannes Berg | e253008 | 2008-05-17 00:57:14 +0200 | [diff] [blame] | 741 | int txq_id = skb_get_queue_mapping(skb); |
Tomas Winkler | fd4abac | 2008-05-15 13:54:07 +0800 | [diff] [blame] | 742 | struct iwl_tx_queue *txq = NULL; |
| 743 | struct iwl_queue *q = NULL; |
| 744 | dma_addr_t phys_addr; |
| 745 | dma_addr_t txcmd_phys; |
| 746 | dma_addr_t scratch_phys; |
| 747 | struct iwl_cmd *out_cmd = NULL; |
| 748 | struct iwl_tx_cmd *tx_cmd; |
| 749 | u16 len, idx, len_org; |
| 750 | u16 seq_number = 0; |
| 751 | u8 id, hdr_len, unicast; |
| 752 | u8 sta_id; |
| 753 | u16 fc; |
| 754 | u8 wait_write_ptr = 0; |
| 755 | u8 tid = 0; |
| 756 | u8 *qc = NULL; |
| 757 | unsigned long flags; |
| 758 | int ret; |
| 759 | |
| 760 | spin_lock_irqsave(&priv->lock, flags); |
| 761 | if (iwl_is_rfkill(priv)) { |
| 762 | IWL_DEBUG_DROP("Dropping - RF KILL\n"); |
| 763 | goto drop_unlock; |
| 764 | } |
| 765 | |
| 766 | if (!priv->vif) { |
| 767 | IWL_DEBUG_DROP("Dropping - !priv->vif\n"); |
| 768 | goto drop_unlock; |
| 769 | } |
| 770 | |
Johannes Berg | e039fa4 | 2008-05-15 12:55:29 +0200 | [diff] [blame] | 771 | if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == |
Johannes Berg | 2e92e6f | 2008-05-15 12:55:27 +0200 | [diff] [blame] | 772 | IWL_INVALID_RATE) { |
Tomas Winkler | fd4abac | 2008-05-15 13:54:07 +0800 | [diff] [blame] | 773 | IWL_ERROR("ERROR: No TX rate available.\n"); |
| 774 | goto drop_unlock; |
| 775 | } |
| 776 | |
| 777 | unicast = !is_multicast_ether_addr(hdr->addr1); |
| 778 | id = 0; |
| 779 | |
| 780 | fc = le16_to_cpu(hdr->frame_control); |
| 781 | |
| 782 | #ifdef CONFIG_IWLWIFI_DEBUG |
| 783 | if (ieee80211_is_auth(fc)) |
| 784 | IWL_DEBUG_TX("Sending AUTH frame\n"); |
| 785 | else if (ieee80211_is_assoc_request(fc)) |
| 786 | IWL_DEBUG_TX("Sending ASSOC frame\n"); |
| 787 | else if (ieee80211_is_reassoc_request(fc)) |
| 788 | IWL_DEBUG_TX("Sending REASSOC frame\n"); |
| 789 | #endif |
| 790 | |
| 791 | /* drop all data frame if we are not associated */ |
| 792 | if (((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_DATA) && |
| 793 | (!iwl_is_associated(priv) || |
| 794 | ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && !priv->assoc_id) || |
| 795 | !priv->assoc_station_added)) { |
| 796 | IWL_DEBUG_DROP("Dropping - !iwl_is_associated\n"); |
| 797 | goto drop_unlock; |
| 798 | } |
| 799 | |
| 800 | spin_unlock_irqrestore(&priv->lock, flags); |
| 801 | |
| 802 | hdr_len = ieee80211_get_hdrlen(fc); |
| 803 | |
| 804 | /* Find (or create) index into station table for destination station */ |
| 805 | sta_id = iwl_get_sta_id(priv, hdr); |
| 806 | if (sta_id == IWL_INVALID_STATION) { |
| 807 | DECLARE_MAC_BUF(mac); |
| 808 | |
| 809 | IWL_DEBUG_DROP("Dropping - INVALID STATION: %s\n", |
| 810 | print_mac(mac, hdr->addr1)); |
| 811 | goto drop; |
| 812 | } |
| 813 | |
| 814 | IWL_DEBUG_TX("station Id %d\n", sta_id); |
| 815 | |
| 816 | if (ieee80211_is_qos_data(fc)) { |
| 817 | qc = ieee80211_get_qos_ctrl(hdr, hdr_len); |
| 818 | tid = qc[0] & 0xf; |
| 819 | seq_number = priv->stations[sta_id].tid[tid].seq_number & |
| 820 | IEEE80211_SCTL_SEQ; |
| 821 | hdr->seq_ctrl = cpu_to_le16(seq_number) | |
| 822 | (hdr->seq_ctrl & |
| 823 | __constant_cpu_to_le16(IEEE80211_SCTL_FRAG)); |
| 824 | seq_number += 0x10; |
| 825 | #ifdef CONFIG_IWL4965_HT |
| 826 | /* aggregation is on for this <sta,tid> */ |
Johannes Berg | e039fa4 | 2008-05-15 12:55:29 +0200 | [diff] [blame] | 827 | if (info->flags & IEEE80211_TX_CTL_AMPDU) |
Tomas Winkler | fd4abac | 2008-05-15 13:54:07 +0800 | [diff] [blame] | 828 | txq_id = priv->stations[sta_id].tid[tid].agg.txq_id; |
| 829 | priv->stations[sta_id].tid[tid].tfds_in_queue++; |
| 830 | #endif /* CONFIG_IWL4965_HT */ |
| 831 | } |
| 832 | |
| 833 | /* Descriptor for chosen Tx queue */ |
| 834 | txq = &priv->txq[txq_id]; |
| 835 | q = &txq->q; |
| 836 | |
| 837 | spin_lock_irqsave(&priv->lock, flags); |
| 838 | |
| 839 | /* Set up first empty TFD within this queue's circular TFD buffer */ |
| 840 | tfd = &txq->bd[q->write_ptr]; |
| 841 | memset(tfd, 0, sizeof(*tfd)); |
| 842 | control_flags = (u32 *) tfd; |
| 843 | idx = get_cmd_index(q, q->write_ptr, 0); |
| 844 | |
| 845 | /* Set up driver data for this TFD */ |
| 846 | memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info)); |
| 847 | txq->txb[q->write_ptr].skb[0] = skb; |
Tomas Winkler | fd4abac | 2008-05-15 13:54:07 +0800 | [diff] [blame] | 848 | |
| 849 | /* Set up first empty entry in queue's array of Tx/cmd buffers */ |
| 850 | out_cmd = &txq->cmd[idx]; |
| 851 | tx_cmd = &out_cmd->cmd.tx; |
| 852 | memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr)); |
| 853 | memset(tx_cmd, 0, sizeof(struct iwl_tx_cmd)); |
| 854 | |
| 855 | /* |
| 856 | * Set up the Tx-command (not MAC!) header. |
| 857 | * Store the chosen Tx queue and TFD index within the sequence field; |
| 858 | * after Tx, uCode's Tx response will return this value so driver can |
| 859 | * locate the frame within the tx queue and do post-tx processing. |
| 860 | */ |
| 861 | out_cmd->hdr.cmd = REPLY_TX; |
| 862 | out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | |
| 863 | INDEX_TO_SEQ(q->write_ptr))); |
| 864 | |
| 865 | /* Copy MAC header from skb into command buffer */ |
| 866 | memcpy(tx_cmd->hdr, hdr, hdr_len); |
| 867 | |
| 868 | /* |
| 869 | * Use the first empty entry in this queue's command buffer array |
| 870 | * to contain the Tx command and MAC header concatenated together |
| 871 | * (payload data will be in another buffer). |
| 872 | * Size of this varies, due to varying MAC header length. |
| 873 | * If end is not dword aligned, we'll have 2 extra bytes at the end |
| 874 | * of the MAC header (device reads on dword boundaries). |
| 875 | * We'll tell device about this padding later. |
| 876 | */ |
| 877 | len = sizeof(struct iwl_tx_cmd) + |
| 878 | sizeof(struct iwl_cmd_header) + hdr_len; |
| 879 | |
| 880 | len_org = len; |
| 881 | len = (len + 3) & ~3; |
| 882 | |
| 883 | if (len_org != len) |
| 884 | len_org = 1; |
| 885 | else |
| 886 | len_org = 0; |
| 887 | |
| 888 | /* Physical address of this Tx command's header (not MAC header!), |
| 889 | * within command buffer array. */ |
| 890 | txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl_cmd) * idx + |
| 891 | offsetof(struct iwl_cmd, hdr); |
| 892 | |
| 893 | /* Add buffer containing Tx command and MAC(!) header to TFD's |
| 894 | * first entry */ |
| 895 | iwl_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len); |
| 896 | |
Johannes Berg | e039fa4 | 2008-05-15 12:55:29 +0200 | [diff] [blame] | 897 | if (!(info->flags & IEEE80211_TX_CTL_DO_NOT_ENCRYPT)) |
| 898 | iwl_tx_cmd_build_hwcrypto(priv, info, tx_cmd, skb, sta_id); |
Tomas Winkler | fd4abac | 2008-05-15 13:54:07 +0800 | [diff] [blame] | 899 | |
| 900 | /* Set up TFD's 2nd entry to point directly to remainder of skb, |
| 901 | * if any (802.11 null frames have no payload). */ |
| 902 | len = skb->len - hdr_len; |
| 903 | if (len) { |
| 904 | phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len, |
| 905 | len, PCI_DMA_TODEVICE); |
| 906 | iwl_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len); |
| 907 | } |
| 908 | |
| 909 | /* Tell NIC about any 2-byte padding after MAC header */ |
| 910 | if (len_org) |
| 911 | tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK; |
| 912 | |
| 913 | /* Total # bytes to be transmitted */ |
| 914 | len = (u16)skb->len; |
| 915 | tx_cmd->len = cpu_to_le16(len); |
| 916 | /* TODO need this for burst mode later on */ |
Johannes Berg | e039fa4 | 2008-05-15 12:55:29 +0200 | [diff] [blame] | 917 | iwl_tx_cmd_build_basic(priv, tx_cmd, info, hdr, unicast, sta_id); |
Tomas Winkler | fd4abac | 2008-05-15 13:54:07 +0800 | [diff] [blame] | 918 | |
| 919 | /* set is_hcca to 0; it probably will never be implemented */ |
Johannes Berg | e039fa4 | 2008-05-15 12:55:29 +0200 | [diff] [blame] | 920 | iwl_tx_cmd_build_rate(priv, tx_cmd, info, fc, sta_id, 0); |
Tomas Winkler | fd4abac | 2008-05-15 13:54:07 +0800 | [diff] [blame] | 921 | |
| 922 | iwl_update_tx_stats(priv, fc, len); |
| 923 | |
| 924 | scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) + |
| 925 | offsetof(struct iwl_tx_cmd, scratch); |
| 926 | tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); |
| 927 | tx_cmd->dram_msb_ptr = iwl_get_dma_hi_address(scratch_phys); |
| 928 | |
| 929 | if (!ieee80211_get_morefrag(hdr)) { |
| 930 | txq->need_update = 1; |
| 931 | if (qc) |
| 932 | priv->stations[sta_id].tid[tid].seq_number = seq_number; |
| 933 | } else { |
| 934 | wait_write_ptr = 1; |
| 935 | txq->need_update = 0; |
| 936 | } |
| 937 | |
| 938 | iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd)); |
| 939 | |
| 940 | iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len); |
| 941 | |
| 942 | /* Set up entry for this TFD in Tx byte-count array */ |
| 943 | priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, len); |
| 944 | |
| 945 | /* Tell device the write index *just past* this latest filled TFD */ |
| 946 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); |
| 947 | ret = iwl_txq_update_write_ptr(priv, txq); |
| 948 | spin_unlock_irqrestore(&priv->lock, flags); |
| 949 | |
| 950 | if (ret) |
| 951 | return ret; |
| 952 | |
| 953 | if ((iwl_queue_space(q) < q->high_mark) |
| 954 | && priv->mac80211_registered) { |
| 955 | if (wait_write_ptr) { |
| 956 | spin_lock_irqsave(&priv->lock, flags); |
| 957 | txq->need_update = 1; |
| 958 | iwl_txq_update_write_ptr(priv, txq); |
| 959 | spin_unlock_irqrestore(&priv->lock, flags); |
| 960 | } |
| 961 | |
Johannes Berg | e253008 | 2008-05-17 00:57:14 +0200 | [diff] [blame] | 962 | ieee80211_stop_queue(priv->hw, skb_get_queue_mapping(skb)); |
Tomas Winkler | fd4abac | 2008-05-15 13:54:07 +0800 | [diff] [blame] | 963 | } |
| 964 | |
| 965 | return 0; |
| 966 | |
| 967 | drop_unlock: |
| 968 | spin_unlock_irqrestore(&priv->lock, flags); |
| 969 | drop: |
| 970 | return -1; |
| 971 | } |
| 972 | EXPORT_SYMBOL(iwl_tx_skb); |
| 973 | |
| 974 | /*************** HOST COMMAND QUEUE FUNCTIONS *****/ |
| 975 | |
| 976 | /** |
| 977 | * iwl_enqueue_hcmd - enqueue a uCode command |
| 978 | * @priv: device private data point |
| 979 | * @cmd: a point to the ucode command structure |
| 980 | * |
| 981 | * The function returns < 0 values to indicate the operation is |
| 982 | * failed. On success, it turns the index (> 0) of command in the |
| 983 | * command queue. |
| 984 | */ |
| 985 | int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd) |
| 986 | { |
| 987 | struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM]; |
| 988 | struct iwl_queue *q = &txq->q; |
| 989 | struct iwl_tfd_frame *tfd; |
| 990 | u32 *control_flags; |
| 991 | struct iwl_cmd *out_cmd; |
| 992 | u32 idx; |
| 993 | u16 fix_size; |
| 994 | dma_addr_t phys_addr; |
| 995 | int ret; |
| 996 | unsigned long flags; |
| 997 | |
| 998 | cmd->len = priv->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len); |
| 999 | fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr)); |
| 1000 | |
| 1001 | /* If any of the command structures end up being larger than |
| 1002 | * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then |
| 1003 | * we will need to increase the size of the TFD entries */ |
| 1004 | BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) && |
| 1005 | !(cmd->meta.flags & CMD_SIZE_HUGE)); |
| 1006 | |
| 1007 | if (iwl_is_rfkill(priv)) { |
| 1008 | IWL_DEBUG_INFO("Not sending command - RF KILL"); |
| 1009 | return -EIO; |
| 1010 | } |
| 1011 | |
| 1012 | if (iwl_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) { |
| 1013 | IWL_ERROR("No space for Tx\n"); |
| 1014 | return -ENOSPC; |
| 1015 | } |
| 1016 | |
| 1017 | spin_lock_irqsave(&priv->hcmd_lock, flags); |
| 1018 | |
| 1019 | tfd = &txq->bd[q->write_ptr]; |
| 1020 | memset(tfd, 0, sizeof(*tfd)); |
| 1021 | |
| 1022 | control_flags = (u32 *) tfd; |
| 1023 | |
| 1024 | idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE); |
| 1025 | out_cmd = &txq->cmd[idx]; |
| 1026 | |
| 1027 | out_cmd->hdr.cmd = cmd->id; |
| 1028 | memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta)); |
| 1029 | memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len); |
| 1030 | |
| 1031 | /* At this point, the out_cmd now has all of the incoming cmd |
| 1032 | * information */ |
| 1033 | |
| 1034 | out_cmd->hdr.flags = 0; |
| 1035 | out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) | |
| 1036 | INDEX_TO_SEQ(q->write_ptr)); |
| 1037 | if (out_cmd->meta.flags & CMD_SIZE_HUGE) |
| 1038 | out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME); |
| 1039 | |
| 1040 | phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx + |
| 1041 | offsetof(struct iwl_cmd, hdr); |
| 1042 | iwl_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size); |
| 1043 | |
| 1044 | IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, " |
| 1045 | "%d bytes at %d[%d]:%d\n", |
| 1046 | get_cmd_string(out_cmd->hdr.cmd), |
| 1047 | out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence), |
| 1048 | fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM); |
| 1049 | |
| 1050 | txq->need_update = 1; |
| 1051 | |
| 1052 | /* Set up entry in queue's byte count circular buffer */ |
| 1053 | priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0); |
| 1054 | |
| 1055 | /* Increment and update queue's write index */ |
| 1056 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); |
| 1057 | ret = iwl_txq_update_write_ptr(priv, txq); |
| 1058 | |
| 1059 | spin_unlock_irqrestore(&priv->hcmd_lock, flags); |
| 1060 | return ret ? ret : idx; |
| 1061 | } |
| 1062 | |
Tomas Winkler | a332f8d | 2008-05-29 16:35:08 +0800 | [diff] [blame^] | 1063 | #ifdef CONFIG_IWLWIF_DEBUG |
| 1064 | #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x |
| 1065 | |
| 1066 | const char *iwl_get_tx_fail_reason(u32 status) |
| 1067 | { |
| 1068 | switch (status & TX_STATUS_MSK) { |
| 1069 | case TX_STATUS_SUCCESS: |
| 1070 | return "SUCCESS"; |
| 1071 | TX_STATUS_ENTRY(SHORT_LIMIT); |
| 1072 | TX_STATUS_ENTRY(LONG_LIMIT); |
| 1073 | TX_STATUS_ENTRY(FIFO_UNDERRUN); |
| 1074 | TX_STATUS_ENTRY(MGMNT_ABORT); |
| 1075 | TX_STATUS_ENTRY(NEXT_FRAG); |
| 1076 | TX_STATUS_ENTRY(LIFE_EXPIRE); |
| 1077 | TX_STATUS_ENTRY(DEST_PS); |
| 1078 | TX_STATUS_ENTRY(ABORTED); |
| 1079 | TX_STATUS_ENTRY(BT_RETRY); |
| 1080 | TX_STATUS_ENTRY(STA_INVALID); |
| 1081 | TX_STATUS_ENTRY(FRAG_DROPPED); |
| 1082 | TX_STATUS_ENTRY(TID_DISABLE); |
| 1083 | TX_STATUS_ENTRY(FRAME_FLUSHED); |
| 1084 | TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL); |
| 1085 | TX_STATUS_ENTRY(TX_LOCKED); |
| 1086 | TX_STATUS_ENTRY(NO_BEACON_ON_RADAR); |
| 1087 | } |
| 1088 | |
| 1089 | return "UNKNOWN"; |
| 1090 | } |
| 1091 | EXPORT_SYMBOL(iwl_get_tx_fail_reason); |
| 1092 | #endif /* CONFIG_IWLWIFI_DEBUG */ |