Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1 | /* |
Pierre Ossman | 70f1048 | 2007-07-11 20:04:50 +0200 | [diff] [blame] | 2 | * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3 | * |
Pierre Ossman | b69c905 | 2008-03-08 23:44:25 +0100 | [diff] [blame] | 4 | * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
Pierre Ossman | 643f720 | 2006-09-30 23:27:52 -0700 | [diff] [blame] | 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or (at |
| 9 | * your option) any later version. |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 10 | */ |
| 11 | |
Andrew Morton | 0c7ad10 | 2008-07-25 19:44:35 -0700 | [diff] [blame] | 12 | #include <linux/scatterlist.h> |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 13 | #include <linux/compiler.h> |
| 14 | #include <linux/types.h> |
| 15 | #include <linux/io.h> |
Andrew Morton | 0c7ad10 | 2008-07-25 19:44:35 -0700 | [diff] [blame] | 16 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 17 | /* |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 18 | * Controller registers |
| 19 | */ |
| 20 | |
| 21 | #define SDHCI_DMA_ADDRESS 0x00 |
| 22 | |
| 23 | #define SDHCI_BLOCK_SIZE 0x04 |
Pierre Ossman | bab7696 | 2006-07-02 16:51:35 +0100 | [diff] [blame] | 24 | #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 25 | |
| 26 | #define SDHCI_BLOCK_COUNT 0x06 |
| 27 | |
| 28 | #define SDHCI_ARGUMENT 0x08 |
| 29 | |
| 30 | #define SDHCI_TRANSFER_MODE 0x0C |
| 31 | #define SDHCI_TRNS_DMA 0x01 |
| 32 | #define SDHCI_TRNS_BLK_CNT_EN 0x02 |
| 33 | #define SDHCI_TRNS_ACMD12 0x04 |
| 34 | #define SDHCI_TRNS_READ 0x10 |
| 35 | #define SDHCI_TRNS_MULTI 0x20 |
| 36 | |
| 37 | #define SDHCI_COMMAND 0x0E |
| 38 | #define SDHCI_CMD_RESP_MASK 0x03 |
| 39 | #define SDHCI_CMD_CRC 0x08 |
| 40 | #define SDHCI_CMD_INDEX 0x10 |
| 41 | #define SDHCI_CMD_DATA 0x20 |
| 42 | |
| 43 | #define SDHCI_CMD_RESP_NONE 0x00 |
| 44 | #define SDHCI_CMD_RESP_LONG 0x01 |
| 45 | #define SDHCI_CMD_RESP_SHORT 0x02 |
| 46 | #define SDHCI_CMD_RESP_SHORT_BUSY 0x03 |
| 47 | |
| 48 | #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) |
| 49 | |
| 50 | #define SDHCI_RESPONSE 0x10 |
| 51 | |
| 52 | #define SDHCI_BUFFER 0x20 |
| 53 | |
| 54 | #define SDHCI_PRESENT_STATE 0x24 |
| 55 | #define SDHCI_CMD_INHIBIT 0x00000001 |
| 56 | #define SDHCI_DATA_INHIBIT 0x00000002 |
| 57 | #define SDHCI_DOING_WRITE 0x00000100 |
| 58 | #define SDHCI_DOING_READ 0x00000200 |
| 59 | #define SDHCI_SPACE_AVAILABLE 0x00000400 |
| 60 | #define SDHCI_DATA_AVAILABLE 0x00000800 |
| 61 | #define SDHCI_CARD_PRESENT 0x00010000 |
| 62 | #define SDHCI_WRITE_PROTECT 0x00080000 |
| 63 | |
| 64 | #define SDHCI_HOST_CONTROL 0x28 |
| 65 | #define SDHCI_CTRL_LED 0x01 |
| 66 | #define SDHCI_CTRL_4BITBUS 0x02 |
Pierre Ossman | 077df88 | 2006-11-08 23:06:35 +0100 | [diff] [blame] | 67 | #define SDHCI_CTRL_HISPD 0x04 |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 68 | #define SDHCI_CTRL_DMA_MASK 0x18 |
| 69 | #define SDHCI_CTRL_SDMA 0x00 |
| 70 | #define SDHCI_CTRL_ADMA1 0x08 |
| 71 | #define SDHCI_CTRL_ADMA32 0x10 |
| 72 | #define SDHCI_CTRL_ADMA64 0x18 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 73 | |
| 74 | #define SDHCI_POWER_CONTROL 0x29 |
Pierre Ossman | 146ad66 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 75 | #define SDHCI_POWER_ON 0x01 |
| 76 | #define SDHCI_POWER_180 0x0A |
| 77 | #define SDHCI_POWER_300 0x0C |
| 78 | #define SDHCI_POWER_330 0x0E |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 79 | |
| 80 | #define SDHCI_BLOCK_GAP_CONTROL 0x2A |
| 81 | |
Nicolas Pitre | 2df3b71 | 2007-09-29 10:46:20 -0400 | [diff] [blame] | 82 | #define SDHCI_WAKE_UP_CONTROL 0x2B |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 83 | |
| 84 | #define SDHCI_CLOCK_CONTROL 0x2C |
| 85 | #define SDHCI_DIVIDER_SHIFT 8 |
| 86 | #define SDHCI_CLOCK_CARD_EN 0x0004 |
| 87 | #define SDHCI_CLOCK_INT_STABLE 0x0002 |
| 88 | #define SDHCI_CLOCK_INT_EN 0x0001 |
| 89 | |
| 90 | #define SDHCI_TIMEOUT_CONTROL 0x2E |
| 91 | |
| 92 | #define SDHCI_SOFTWARE_RESET 0x2F |
| 93 | #define SDHCI_RESET_ALL 0x01 |
| 94 | #define SDHCI_RESET_CMD 0x02 |
| 95 | #define SDHCI_RESET_DATA 0x04 |
| 96 | |
| 97 | #define SDHCI_INT_STATUS 0x30 |
| 98 | #define SDHCI_INT_ENABLE 0x34 |
| 99 | #define SDHCI_SIGNAL_ENABLE 0x38 |
| 100 | #define SDHCI_INT_RESPONSE 0x00000001 |
| 101 | #define SDHCI_INT_DATA_END 0x00000002 |
| 102 | #define SDHCI_INT_DMA_END 0x00000008 |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 103 | #define SDHCI_INT_SPACE_AVAIL 0x00000010 |
| 104 | #define SDHCI_INT_DATA_AVAIL 0x00000020 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 105 | #define SDHCI_INT_CARD_INSERT 0x00000040 |
| 106 | #define SDHCI_INT_CARD_REMOVE 0x00000080 |
| 107 | #define SDHCI_INT_CARD_INT 0x00000100 |
Pierre Ossman | 964f9ce | 2007-07-20 18:20:36 +0200 | [diff] [blame] | 108 | #define SDHCI_INT_ERROR 0x00008000 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 109 | #define SDHCI_INT_TIMEOUT 0x00010000 |
| 110 | #define SDHCI_INT_CRC 0x00020000 |
| 111 | #define SDHCI_INT_END_BIT 0x00040000 |
| 112 | #define SDHCI_INT_INDEX 0x00080000 |
| 113 | #define SDHCI_INT_DATA_TIMEOUT 0x00100000 |
| 114 | #define SDHCI_INT_DATA_CRC 0x00200000 |
| 115 | #define SDHCI_INT_DATA_END_BIT 0x00400000 |
| 116 | #define SDHCI_INT_BUS_POWER 0x00800000 |
| 117 | #define SDHCI_INT_ACMD12ERR 0x01000000 |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 118 | #define SDHCI_INT_ADMA_ERROR 0x02000000 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 119 | |
| 120 | #define SDHCI_INT_NORMAL_MASK 0x00007FFF |
| 121 | #define SDHCI_INT_ERROR_MASK 0xFFFF8000 |
| 122 | |
| 123 | #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ |
| 124 | SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX) |
| 125 | #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 126 | SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 127 | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ |
Pierre Ossman | 4accfe2 | 2009-04-10 23:55:42 +0200 | [diff] [blame] | 128 | SDHCI_INT_DATA_END_BIT | SDHCI_ADMA_ERROR) |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 129 | #define SDHCI_INT_ALL_MASK ((unsigned int)-1) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 130 | |
| 131 | #define SDHCI_ACMD12_ERR 0x3C |
| 132 | |
| 133 | /* 3E-3F reserved */ |
| 134 | |
| 135 | #define SDHCI_CAPABILITIES 0x40 |
Pierre Ossman | 1c8cde9 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 136 | #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F |
| 137 | #define SDHCI_TIMEOUT_CLK_SHIFT 0 |
| 138 | #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 139 | #define SDHCI_CLOCK_BASE_MASK 0x00003F00 |
| 140 | #define SDHCI_CLOCK_BASE_SHIFT 8 |
Pierre Ossman | 1d676e0 | 2006-07-02 16:52:10 +0100 | [diff] [blame] | 141 | #define SDHCI_MAX_BLOCK_MASK 0x00030000 |
| 142 | #define SDHCI_MAX_BLOCK_SHIFT 16 |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 143 | #define SDHCI_CAN_DO_ADMA2 0x00080000 |
| 144 | #define SDHCI_CAN_DO_ADMA1 0x00100000 |
Pierre Ossman | 077df88 | 2006-11-08 23:06:35 +0100 | [diff] [blame] | 145 | #define SDHCI_CAN_DO_HISPD 0x00200000 |
Pierre Ossman | 146ad66 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 146 | #define SDHCI_CAN_DO_DMA 0x00400000 |
| 147 | #define SDHCI_CAN_VDD_330 0x01000000 |
| 148 | #define SDHCI_CAN_VDD_300 0x02000000 |
| 149 | #define SDHCI_CAN_VDD_180 0x04000000 |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 150 | #define SDHCI_CAN_64BIT 0x10000000 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 151 | |
| 152 | /* 44-47 reserved for more caps */ |
| 153 | |
| 154 | #define SDHCI_MAX_CURRENT 0x48 |
| 155 | |
| 156 | /* 4C-4F reserved for more max current */ |
| 157 | |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 158 | #define SDHCI_SET_ACMD12_ERROR 0x50 |
| 159 | #define SDHCI_SET_INT_ERROR 0x52 |
| 160 | |
| 161 | #define SDHCI_ADMA_ERROR 0x54 |
| 162 | |
| 163 | /* 55-57 reserved */ |
| 164 | |
| 165 | #define SDHCI_ADMA_ADDRESS 0x58 |
| 166 | |
| 167 | /* 60-FB reserved */ |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 168 | |
| 169 | #define SDHCI_SLOT_INT_STATUS 0xFC |
| 170 | |
| 171 | #define SDHCI_HOST_VERSION 0xFE |
Pierre Ossman | 4a96550 | 2006-06-30 02:22:29 -0700 | [diff] [blame] | 172 | #define SDHCI_VENDOR_VER_MASK 0xFF00 |
| 173 | #define SDHCI_VENDOR_VER_SHIFT 8 |
| 174 | #define SDHCI_SPEC_VER_MASK 0x00FF |
| 175 | #define SDHCI_SPEC_VER_SHIFT 0 |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 176 | #define SDHCI_SPEC_100 0 |
| 177 | #define SDHCI_SPEC_200 1 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 178 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 179 | struct sdhci_ops; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 180 | |
| 181 | struct sdhci_host { |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 182 | /* Data set by hardware interface driver */ |
| 183 | const char *hw_name; /* Hardware bus name */ |
| 184 | |
| 185 | unsigned int quirks; /* Deviations from spec. */ |
| 186 | |
| 187 | /* Controller doesn't honor resets unless we touch the clock register */ |
| 188 | #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0) |
| 189 | /* Controller has bad caps bits, but really supports DMA */ |
| 190 | #define SDHCI_QUIRK_FORCE_DMA (1<<1) |
| 191 | /* Controller doesn't like to be reset when there is no card inserted. */ |
| 192 | #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2) |
| 193 | /* Controller doesn't like clearing the power reg before a change */ |
| 194 | #define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3) |
| 195 | /* Controller has flaky internal state so reset it on each ios change */ |
| 196 | #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4) |
| 197 | /* Controller has an unusable DMA engine */ |
| 198 | #define SDHCI_QUIRK_BROKEN_DMA (1<<5) |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 199 | /* Controller has an unusable ADMA engine */ |
| 200 | #define SDHCI_QUIRK_BROKEN_ADMA (1<<6) |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 201 | /* Controller can only DMA from 32-bit aligned addresses */ |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 202 | #define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7) |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 203 | /* Controller can only DMA chunk sizes that are a multiple of 32 bits */ |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 204 | #define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8) |
| 205 | /* Controller can only ADMA chunks that are a multiple of 32 bits */ |
| 206 | #define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9) |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 207 | /* Controller needs to be reset after each request to stay stable */ |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 208 | #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10) |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 209 | /* Controller needs voltage and power writes to happen separately */ |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 210 | #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11) |
Pierre Ossman | ee53ab5 | 2008-07-05 00:25:15 +0200 | [diff] [blame] | 211 | /* Controller provides an incorrect timeout value for transfers */ |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 212 | #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12) |
Pierre Ossman | 4a3cba3 | 2008-07-29 00:11:16 +0200 | [diff] [blame] | 213 | /* Controller has an issue with buffer bits for small transfers */ |
| 214 | #define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13) |
Ben Dooks | f945405 | 2009-02-20 20:33:08 +0300 | [diff] [blame] | 215 | /* Controller does not provide transfer-complete interrupt when not busy */ |
| 216 | #define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14) |
Anton Vorontsov | 68d1fb7 | 2009-03-17 00:13:52 +0300 | [diff] [blame] | 217 | /* Controller has unreliable card detection */ |
| 218 | #define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15) |
Anton Vorontsov | c5075a1 | 2009-03-17 00:13:54 +0300 | [diff] [blame] | 219 | /* Controller reports inverted write-protect state */ |
| 220 | #define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16) |
Anton Vorontsov | 8114634 | 2009-03-17 00:13:59 +0300 | [diff] [blame] | 221 | /* Controller has nonstandard clock management */ |
| 222 | #define SDHCI_QUIRK_NONSTANDARD_CLOCK (1<<17) |
Anton Vorontsov | 3e3bf20 | 2009-03-17 00:14:00 +0300 | [diff] [blame] | 223 | /* Controller does not like fast PIO transfers */ |
| 224 | #define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18) |
Anton Vorontsov | 063a9db | 2009-03-17 00:14:02 +0300 | [diff] [blame] | 225 | /* Controller losing signal/interrupt enable states after reset */ |
| 226 | #define SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET (1<<19) |
Anton Vorontsov | 0633f65 | 2009-03-17 00:14:03 +0300 | [diff] [blame] | 227 | /* Controller has to be forced to use block size of 2048 bytes */ |
| 228 | #define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20) |
Ben Dooks | 1388eef | 2009-06-14 12:40:53 +0100 | [diff] [blame] | 229 | /* Controller cannot do multi-block transfers */ |
| 230 | #define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21) |
Anton Vorontsov | 5fe23c7 | 2009-06-18 00:14:08 +0400 | [diff] [blame] | 231 | /* Controller can only handle 1-bit data transfers */ |
| 232 | #define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22) |
Harald Welte | 557b069 | 2009-06-18 16:53:38 +0200 | [diff] [blame] | 233 | /* Controller needs 10ms delay between applying power and clock */ |
| 234 | #define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23) |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 235 | |
| 236 | int irq; /* Device IRQ */ |
| 237 | void __iomem * ioaddr; /* Mapped address */ |
| 238 | |
| 239 | const struct sdhci_ops *ops; /* Low level hw interface */ |
| 240 | |
| 241 | /* Internal data */ |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 242 | struct mmc_host *mmc; /* MMC structure */ |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 243 | u64 dma_mask; /* custom DMA mask */ |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 244 | |
Éric Piel | 35ff855 | 2008-11-22 19:29:29 +0100 | [diff] [blame] | 245 | #if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE) |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 246 | struct led_classdev led; /* LED control */ |
Helmut Schaa | 5dbace0 | 2009-02-14 16:22:39 +0100 | [diff] [blame] | 247 | char led_name[32]; |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 248 | #endif |
| 249 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 250 | spinlock_t lock; /* Mutex */ |
| 251 | |
| 252 | int flags; /* Host attributes */ |
Pierre Ossman | c9fddbc | 2007-12-02 19:52:11 +0100 | [diff] [blame] | 253 | #define SDHCI_USE_DMA (1<<0) /* Host is DMA capable */ |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 254 | #define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */ |
| 255 | #define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */ |
| 256 | #define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */ |
| 257 | |
| 258 | unsigned int version; /* SDHCI spec. version */ |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 259 | |
| 260 | unsigned int max_clk; /* Max possible freq (MHz) */ |
Pierre Ossman | 1c8cde9 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 261 | unsigned int timeout_clk; /* Timeout freq (KHz) */ |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 262 | |
| 263 | unsigned int clock; /* Current clock (MHz) */ |
Pierre Ossman | ae62890 | 2009-05-03 20:45:03 +0200 | [diff] [blame] | 264 | u8 pwr; /* Current voltage */ |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 265 | |
| 266 | struct mmc_request *mrq; /* Current request */ |
| 267 | struct mmc_command *cmd; /* Current command */ |
| 268 | struct mmc_data *data; /* Current data request */ |
Harvey Harrison | 55654be | 2008-05-12 14:02:08 -0700 | [diff] [blame] | 269 | unsigned int data_early:1; /* Data finished before cmd */ |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 270 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 271 | struct sg_mapping_iter sg_miter; /* SG state for PIO */ |
| 272 | unsigned int blocks; /* remaining PIO blocks */ |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 273 | |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 274 | int sg_count; /* Mapped sg entries */ |
| 275 | |
| 276 | u8 *adma_desc; /* ADMA descriptor table */ |
| 277 | u8 *align_buffer; /* Bounce buffer */ |
| 278 | |
| 279 | dma_addr_t adma_addr; /* Mapped ADMA descr. table */ |
| 280 | dma_addr_t align_addr; /* Mapped bounce buffer */ |
| 281 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 282 | struct tasklet_struct card_tasklet; /* Tasklet structures */ |
| 283 | struct tasklet_struct finish_tasklet; |
| 284 | |
| 285 | struct timer_list timer; /* Timer for timeouts */ |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 286 | |
| 287 | unsigned long private[0] ____cacheline_aligned; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 288 | }; |
| 289 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 290 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 291 | struct sdhci_ops { |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 292 | #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS |
| 293 | u32 (*readl)(struct sdhci_host *host, int reg); |
| 294 | u16 (*readw)(struct sdhci_host *host, int reg); |
| 295 | u8 (*readb)(struct sdhci_host *host, int reg); |
| 296 | void (*writel)(struct sdhci_host *host, u32 val, int reg); |
| 297 | void (*writew)(struct sdhci_host *host, u16 val, int reg); |
| 298 | void (*writeb)(struct sdhci_host *host, u8 val, int reg); |
| 299 | #endif |
| 300 | |
Anton Vorontsov | 8114634 | 2009-03-17 00:13:59 +0300 | [diff] [blame] | 301 | void (*set_clock)(struct sdhci_host *host, unsigned int clock); |
| 302 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 303 | int (*enable_dma)(struct sdhci_host *host); |
Ben Dooks | 4240ff0 | 2009-03-17 00:13:57 +0300 | [diff] [blame] | 304 | unsigned int (*get_max_clock)(struct sdhci_host *host); |
Anton Vorontsov | a9e58f2 | 2009-07-29 15:04:16 -0700 | [diff] [blame] | 305 | unsigned int (*get_min_clock)(struct sdhci_host *host); |
Ben Dooks | 4240ff0 | 2009-03-17 00:13:57 +0300 | [diff] [blame] | 306 | unsigned int (*get_timeout_clock)(struct sdhci_host *host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 307 | }; |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 308 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 309 | #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS |
| 310 | |
| 311 | static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) |
| 312 | { |
| 313 | if (unlikely(host->ops->writel)) |
| 314 | host->ops->writel(host, val, reg); |
| 315 | else |
| 316 | writel(val, host->ioaddr + reg); |
| 317 | } |
| 318 | |
| 319 | static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) |
| 320 | { |
| 321 | if (unlikely(host->ops->writew)) |
| 322 | host->ops->writew(host, val, reg); |
| 323 | else |
| 324 | writew(val, host->ioaddr + reg); |
| 325 | } |
| 326 | |
| 327 | static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) |
| 328 | { |
| 329 | if (unlikely(host->ops->writeb)) |
| 330 | host->ops->writeb(host, val, reg); |
| 331 | else |
| 332 | writeb(val, host->ioaddr + reg); |
| 333 | } |
| 334 | |
| 335 | static inline u32 sdhci_readl(struct sdhci_host *host, int reg) |
| 336 | { |
| 337 | if (unlikely(host->ops->readl)) |
| 338 | return host->ops->readl(host, reg); |
| 339 | else |
| 340 | return readl(host->ioaddr + reg); |
| 341 | } |
| 342 | |
| 343 | static inline u16 sdhci_readw(struct sdhci_host *host, int reg) |
| 344 | { |
| 345 | if (unlikely(host->ops->readw)) |
| 346 | return host->ops->readw(host, reg); |
| 347 | else |
| 348 | return readw(host->ioaddr + reg); |
| 349 | } |
| 350 | |
| 351 | static inline u8 sdhci_readb(struct sdhci_host *host, int reg) |
| 352 | { |
| 353 | if (unlikely(host->ops->readb)) |
| 354 | return host->ops->readb(host, reg); |
| 355 | else |
| 356 | return readb(host->ioaddr + reg); |
| 357 | } |
| 358 | |
| 359 | #else |
| 360 | |
| 361 | static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) |
| 362 | { |
| 363 | writel(val, host->ioaddr + reg); |
| 364 | } |
| 365 | |
| 366 | static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) |
| 367 | { |
| 368 | writew(val, host->ioaddr + reg); |
| 369 | } |
| 370 | |
| 371 | static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) |
| 372 | { |
| 373 | writeb(val, host->ioaddr + reg); |
| 374 | } |
| 375 | |
| 376 | static inline u32 sdhci_readl(struct sdhci_host *host, int reg) |
| 377 | { |
| 378 | return readl(host->ioaddr + reg); |
| 379 | } |
| 380 | |
| 381 | static inline u16 sdhci_readw(struct sdhci_host *host, int reg) |
| 382 | { |
| 383 | return readw(host->ioaddr + reg); |
| 384 | } |
| 385 | |
| 386 | static inline u8 sdhci_readb(struct sdhci_host *host, int reg) |
| 387 | { |
| 388 | return readb(host->ioaddr + reg); |
| 389 | } |
| 390 | |
| 391 | #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */ |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 392 | |
| 393 | extern struct sdhci_host *sdhci_alloc_host(struct device *dev, |
| 394 | size_t priv_size); |
| 395 | extern void sdhci_free_host(struct sdhci_host *host); |
| 396 | |
| 397 | static inline void *sdhci_priv(struct sdhci_host *host) |
| 398 | { |
| 399 | return (void *)host->private; |
| 400 | } |
| 401 | |
| 402 | extern int sdhci_add_host(struct sdhci_host *host); |
Pierre Ossman | 1e72859 | 2008-04-16 19:13:13 +0200 | [diff] [blame] | 403 | extern void sdhci_remove_host(struct sdhci_host *host, int dead); |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 404 | |
| 405 | #ifdef CONFIG_PM |
| 406 | extern int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state); |
| 407 | extern int sdhci_resume_host(struct sdhci_host *host); |
| 408 | #endif |