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gerrit-public.fairphone.software / fp2-dev / kernel / msm / ac86a9785384843e8359c45a042cc4f87953d4c8 / . / arch / blackfin / mach-bf561 / dma.c
blob: 9863ae4fb8a4dd9d21fcc089b8f3f091310d3352 [file] [log] [blame]
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]1/*
2 * File: arch/blackfin/mach-bf561/dma.c
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: This file contains the simple DMA Implementation for Blackfin
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
Bernd Schmidtac86a972008-04-24 05:23:31 +0800[diff] [blame^]29#include <linux/module.h>
30
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]31#include <asm/blackfin.h>
32#include <asm/dma.h>
33
34struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
35 (struct dma_register *) DMA1_0_NEXT_DESC_PTR,
36 (struct dma_register *) DMA1_1_NEXT_DESC_PTR,
37 (struct dma_register *) DMA1_2_NEXT_DESC_PTR,
38 (struct dma_register *) DMA1_3_NEXT_DESC_PTR,
39 (struct dma_register *) DMA1_4_NEXT_DESC_PTR,
40 (struct dma_register *) DMA1_5_NEXT_DESC_PTR,
41 (struct dma_register *) DMA1_6_NEXT_DESC_PTR,
42 (struct dma_register *) DMA1_7_NEXT_DESC_PTR,
43 (struct dma_register *) DMA1_8_NEXT_DESC_PTR,
44 (struct dma_register *) DMA1_9_NEXT_DESC_PTR,
45 (struct dma_register *) DMA1_10_NEXT_DESC_PTR,
46 (struct dma_register *) DMA1_11_NEXT_DESC_PTR,
47 (struct dma_register *) DMA2_0_NEXT_DESC_PTR,
48 (struct dma_register *) DMA2_1_NEXT_DESC_PTR,
49 (struct dma_register *) DMA2_2_NEXT_DESC_PTR,
50 (struct dma_register *) DMA2_3_NEXT_DESC_PTR,
51 (struct dma_register *) DMA2_4_NEXT_DESC_PTR,
52 (struct dma_register *) DMA2_5_NEXT_DESC_PTR,
53 (struct dma_register *) DMA2_6_NEXT_DESC_PTR,
54 (struct dma_register *) DMA2_7_NEXT_DESC_PTR,
55 (struct dma_register *) DMA2_8_NEXT_DESC_PTR,
56 (struct dma_register *) DMA2_9_NEXT_DESC_PTR,
57 (struct dma_register *) DMA2_10_NEXT_DESC_PTR,
58 (struct dma_register *) DMA2_11_NEXT_DESC_PTR,
59 (struct dma_register *) MDMA1_D0_NEXT_DESC_PTR,
60 (struct dma_register *) MDMA1_S0_NEXT_DESC_PTR,
61 (struct dma_register *) MDMA1_D1_NEXT_DESC_PTR,
62 (struct dma_register *) MDMA1_S1_NEXT_DESC_PTR,
63 (struct dma_register *) MDMA2_D0_NEXT_DESC_PTR,
64 (struct dma_register *) MDMA2_S0_NEXT_DESC_PTR,
65 (struct dma_register *) MDMA2_D1_NEXT_DESC_PTR,
66 (struct dma_register *) MDMA2_S1_NEXT_DESC_PTR,
67 (struct dma_register *) IMDMA_D0_NEXT_DESC_PTR,
68 (struct dma_register *) IMDMA_S0_NEXT_DESC_PTR,
69 (struct dma_register *) IMDMA_D1_NEXT_DESC_PTR,
70 (struct dma_register *) IMDMA_S1_NEXT_DESC_PTR,
71};
Bernd Schmidtac86a972008-04-24 05:23:31 +0800[diff] [blame^]72EXPORT_SYMBOL(base_addr);
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]73
74int channel2irq(unsigned int channel)
75{
76 int ret_irq = -1;
77
78 switch (channel) {
79 case CH_PPI0:
80 ret_irq = IRQ_PPI0;
81 break;
82 case CH_PPI1:
83 ret_irq = IRQ_PPI1;
84 break;
85 case CH_SPORT0_RX:
86 ret_irq = IRQ_SPORT0_RX;
87 break;
88 case CH_SPORT0_TX:
89 ret_irq = IRQ_SPORT0_TX;
90 break;
91 case CH_SPORT1_RX:
92 ret_irq = IRQ_SPORT1_RX;
93 break;
94 case CH_SPORT1_TX:
95 ret_irq = IRQ_SPORT1_TX;
96 break;
97 case CH_SPI:
98 ret_irq = IRQ_SPI;
99 break;
100 case CH_UART_RX:
101 ret_irq = IRQ_UART_RX;
102 break;
103 case CH_UART_TX:
104 ret_irq = IRQ_UART_TX;
105 break;
106
107 case CH_MEM_STREAM0_SRC:
108 case CH_MEM_STREAM0_DEST:
109 ret_irq = IRQ_MEM_DMA0;
110 break;
111 case CH_MEM_STREAM1_SRC:
112 case CH_MEM_STREAM1_DEST:
113 ret_irq = IRQ_MEM_DMA1;
114 break;
115 case CH_MEM_STREAM2_SRC:
116 case CH_MEM_STREAM2_DEST:
117 ret_irq = IRQ_MEM_DMA2;
118 break;
119 case CH_MEM_STREAM3_SRC:
120 case CH_MEM_STREAM3_DEST:
121 ret_irq = IRQ_MEM_DMA3;
122 break;
123
124 case CH_IMEM_STREAM0_SRC:
125 case CH_IMEM_STREAM0_DEST:
126 ret_irq = IRQ_IMEM_DMA0;
127 break;
128 case CH_IMEM_STREAM1_SRC:
129 case CH_IMEM_STREAM1_DEST:
130 ret_irq = IRQ_IMEM_DMA1;
131 break;
132 }
133 return ret_irq;
134}