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gerrit-public.fairphone.software / fp2-dev / kernel / msm / b1524e29e318e79b2d04bcbd651a7af8dff32bb3 / . / arch / blackfin / mach-bf533 / include / mach / defBF532.h
blob: 8e8099b567f7c641fd1e4da3334925aa2f57b98f [file] [log] [blame]
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]1/*
Robin Getz96f10502009-09-24 14:11:24 +0000[diff] [blame]2 * System & MMR bit and Address definitions for ADSP-BF532
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]3 *
Robin Getz96f10502009-09-24 14:11:24 +0000[diff] [blame]4 * Copyright 2005-2008 Analog Devices Inc.
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]5 *
Robin Getz96f10502009-09-24 14:11:24 +0000[diff] [blame]6 * Licensed under the ADI BSD license or the GPL-2 (or later)
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]7 */
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]8
9#ifndef _DEF_BF532_H
10#define _DEF_BF532_H
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]11
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]12/* include all Core registers and bit definitions */
Bryan Wu639f6572008-08-27 10:51:02 +0800[diff] [blame]13#include <asm/def_LPBlackfin.h>
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]14
15/*********************************************************************************** */
16/* System MMR Register Map */
17/*********************************************************************************** */
18/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
19
20#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */
21#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */
22#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
23#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
24#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
25#define CHIPID 0xFFC00014 /* Chip ID Register */
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]26
27/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]28#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
29#define SYSCR 0xFFC00104 /* System Configuration registe */
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]30#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
31#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */
32#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
33#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
34#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
35#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */
36#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */
37
38/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
39#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
40#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
41#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
42
43/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
44#define RTC_STAT 0xFFC00300 /* RTC Status Register */
45#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
46#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
47#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
48#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
49#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
50#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */
51
52/* UART Controller (0xFFC00400 - 0xFFC004FF) */
Graf Yang6ed83942008-04-24 04:43:14 +0800[diff] [blame]53
54/*
55 * Because include/linux/serial_reg.h have defined UART_*,
56 * So we define blackfin uart regs to BFIN_UART_*.
57 */
58#define BFIN_UART_THR 0xFFC00400 /* Transmit Holding register */
59#define BFIN_UART_RBR 0xFFC00400 /* Receive Buffer register */
60#define BFIN_UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
61#define BFIN_UART_IER 0xFFC00404 /* Interrupt Enable Register */
62#define BFIN_UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
63#define BFIN_UART_IIR 0xFFC00408 /* Interrupt Identification Register */
64#define BFIN_UART_LCR 0xFFC0040C /* Line Control Register */
65#define BFIN_UART_MCR 0xFFC00410 /* Modem Control Register */
66#define BFIN_UART_LSR 0xFFC00414 /* Line Status Register */
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]67#if 0
Graf Yang6ed83942008-04-24 04:43:14 +0800[diff] [blame]68#define BFIN_UART_MSR 0xFFC00418 /* Modem Status Register (UNUSED in ADSP-BF532) */
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]69#endif
Graf Yang6ed83942008-04-24 04:43:14 +0800[diff] [blame]70#define BFIN_UART_SCR 0xFFC0041C /* SCR Scratch Register */
71#define BFIN_UART_GCTL 0xFFC00424 /* Global Control Register */
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]72
73/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
Bryan Wu1d487f42007-10-11 00:30:56 +0800[diff] [blame]74#define SPI0_REGBASE 0xFFC00500
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]75#define SPI_CTL 0xFFC00500 /* SPI Control Register */
76#define SPI_FLG 0xFFC00504 /* SPI Flag register */
77#define SPI_STAT 0xFFC00508 /* SPI Status register */
78#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
79#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
80#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
81#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
82
83/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */
84
85#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
86#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
87#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
88#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
89
90#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
91#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
92#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
93#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
94
95#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
96#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
97#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
98#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
99
100#define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */
101#define TIMER_DISABLE 0xFFC00644 /* Timer Disable Register */
102#define TIMER_STATUS 0xFFC00648 /* Timer Status Register */
103
104/* General Purpose IO (0xFFC00700 - 0xFFC007FF) */
105
106#define FIO_FLAG_D 0xFFC00700 /* Flag Mask to directly specify state of pins */
107#define FIO_FLAG_C 0xFFC00704 /* Peripheral Interrupt Flag Register (clear) */
108#define FIO_FLAG_S 0xFFC00708 /* Peripheral Interrupt Flag Register (set) */
109#define FIO_FLAG_T 0xFFC0070C /* Flag Mask to directly toggle state of pins */
110#define FIO_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Register (set directly) */
111#define FIO_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Register (clear) */
112#define FIO_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Register (set) */
113#define FIO_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Register (toggle) */
114#define FIO_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Register (set directly) */
115#define FIO_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Register (clear) */
116#define FIO_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Register (set) */
117#define FIO_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Register (toggle) */
118#define FIO_DIR 0xFFC00730 /* Peripheral Flag Direction Register */
119#define FIO_POLAR 0xFFC00734 /* Flag Source Polarity Register */
120#define FIO_EDGE 0xFFC00738 /* Flag Source Sensitivity Register */
121#define FIO_BOTH 0xFFC0073C /* Flag Set on BOTH Edges Register */
122#define FIO_INEN 0xFFC00740 /* Flag Input Enable Register */
123
124/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
125#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
126#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
127#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
128#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
129#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
130#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
131#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
132#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
133#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
134#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
135#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
136#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
137#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
138#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
139#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
140#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
141#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
142#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
143#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
144#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
145#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
146#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
147
148/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
149#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
150#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
151#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
152#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
153#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
154#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
155#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
156#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
157#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
158#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
159#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
160#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
161#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
162#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
163#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
164#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
165#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
166#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
167#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
168#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
169#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
170#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
171
172/* Asynchronous Memory Controller - External Bus Interface Unit */
173#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
174#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
175#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
176
177/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
178
179#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
180#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
181#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
182#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
183
184/* DMA Traffic controls */
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]185#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
186#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
187
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]188/* Alternate deprecated register names (below) provided for backwards code compatibility */
189#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
190#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
191
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]192/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
193#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
194#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
195#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
196#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
197#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
198#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
199#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
200#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
201#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
202#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
203#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
204#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
205#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
206
207#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
208#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
209#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
210#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
211#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
212#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
213#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
214#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
215#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
216#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
217#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
218#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
219#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
220
221#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
222#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
223#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
224#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
225#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
226#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
227#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
228#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
229#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
230#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
231#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
232#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
233#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
234
235#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
236#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
237#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
238#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
239#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
240#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
241#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
242#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
243#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
244#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
245#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
246#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
247#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
248
249#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
250#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
251#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
252#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
253#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
254#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
255#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
256#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
257#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
258#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
259#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
260#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
261#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
262
263#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
264#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
265#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
266#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
267#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
268#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
269#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
270#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
271#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
272#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
273#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
274#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
275#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
276
277#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
278#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
279#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
280#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
281#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
282#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
283#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
284#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
285#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
286#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
287#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
288#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
289#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
290
291#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
292#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
293#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
294#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
295#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
296#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
297#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
298#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
299#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
300#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
301#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
302#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
303#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
304
305#define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA Stream 1 Destination Configuration Register */
306#define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
307#define MDMA_D1_START_ADDR 0xFFC00E84 /* MemDMA Stream 1 Destination Start Address Register */
308#define MDMA_D1_X_COUNT 0xFFC00E90 /* MemDMA Stream 1 Destination X Count Register */
309#define MDMA_D1_Y_COUNT 0xFFC00E98 /* MemDMA Stream 1 Destination Y Count Register */
310#define MDMA_D1_X_MODIFY 0xFFC00E94 /* MemDMA Stream 1 Destination X Modify Register */
311#define MDMA_D1_Y_MODIFY 0xFFC00E9C /* MemDMA Stream 1 Destination Y Modify Register */
312#define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
313#define MDMA_D1_CURR_ADDR 0xFFC00EA4 /* MemDMA Stream 1 Destination Current Address Register */
314#define MDMA_D1_CURR_X_COUNT 0xFFC00EB0 /* MemDMA Stream 1 Destination Current X Count Register */
315#define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8 /* MemDMA Stream 1 Destination Current Y Count Register */
316#define MDMA_D1_IRQ_STATUS 0xFFC00EA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
317#define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC /* MemDMA Stream 1 Destination Peripheral Map Register */
318
319#define MDMA_S1_CONFIG 0xFFC00EC8 /* MemDMA Stream 1 Source Configuration Register */
320#define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
321#define MDMA_S1_START_ADDR 0xFFC00EC4 /* MemDMA Stream 1 Source Start Address Register */
322#define MDMA_S1_X_COUNT 0xFFC00ED0 /* MemDMA Stream 1 Source X Count Register */
323#define MDMA_S1_Y_COUNT 0xFFC00ED8 /* MemDMA Stream 1 Source Y Count Register */
324#define MDMA_S1_X_MODIFY 0xFFC00ED4 /* MemDMA Stream 1 Source X Modify Register */
325#define MDMA_S1_Y_MODIFY 0xFFC00EDC /* MemDMA Stream 1 Source Y Modify Register */
326#define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
327#define MDMA_S1_CURR_ADDR 0xFFC00EE4 /* MemDMA Stream 1 Source Current Address Register */
328#define MDMA_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA Stream 1 Source Current X Count Register */
329#define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA Stream 1 Source Current Y Count Register */
330#define MDMA_S1_IRQ_STATUS 0xFFC00EE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
331#define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC /* MemDMA Stream 1 Source Peripheral Map Register */
332
333#define MDMA_D0_CONFIG 0xFFC00E08 /* MemDMA Stream 0 Destination Configuration Register */
334#define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
335#define MDMA_D0_START_ADDR 0xFFC00E04 /* MemDMA Stream 0 Destination Start Address Register */
336#define MDMA_D0_X_COUNT 0xFFC00E10 /* MemDMA Stream 0 Destination X Count Register */
337#define MDMA_D0_Y_COUNT 0xFFC00E18 /* MemDMA Stream 0 Destination Y Count Register */
338#define MDMA_D0_X_MODIFY 0xFFC00E14 /* MemDMA Stream 0 Destination X Modify Register */
339#define MDMA_D0_Y_MODIFY 0xFFC00E1C /* MemDMA Stream 0 Destination Y Modify Register */
340#define MDMA_D0_CURR_DESC_PTR 0xFFC00E20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
341#define MDMA_D0_CURR_ADDR 0xFFC00E24 /* MemDMA Stream 0 Destination Current Address Register */
342#define MDMA_D0_CURR_X_COUNT 0xFFC00E30 /* MemDMA Stream 0 Destination Current X Count Register */
343#define MDMA_D0_CURR_Y_COUNT 0xFFC00E38 /* MemDMA Stream 0 Destination Current Y Count Register */
344#define MDMA_D0_IRQ_STATUS 0xFFC00E28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
345#define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C /* MemDMA Stream 0 Destination Peripheral Map Register */
346
347#define MDMA_S0_CONFIG 0xFFC00E48 /* MemDMA Stream 0 Source Configuration Register */
348#define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
349#define MDMA_S0_START_ADDR 0xFFC00E44 /* MemDMA Stream 0 Source Start Address Register */
350#define MDMA_S0_X_COUNT 0xFFC00E50 /* MemDMA Stream 0 Source X Count Register */
351#define MDMA_S0_Y_COUNT 0xFFC00E58 /* MemDMA Stream 0 Source Y Count Register */
352#define MDMA_S0_X_MODIFY 0xFFC00E54 /* MemDMA Stream 0 Source X Modify Register */
353#define MDMA_S0_Y_MODIFY 0xFFC00E5C /* MemDMA Stream 0 Source Y Modify Register */
354#define MDMA_S0_CURR_DESC_PTR 0xFFC00E60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
355#define MDMA_S0_CURR_ADDR 0xFFC00E64 /* MemDMA Stream 0 Source Current Address Register */
356#define MDMA_S0_CURR_X_COUNT 0xFFC00E70 /* MemDMA Stream 0 Source Current X Count Register */
357#define MDMA_S0_CURR_Y_COUNT 0xFFC00E78 /* MemDMA Stream 0 Source Current Y Count Register */
358#define MDMA_S0_IRQ_STATUS 0xFFC00E68 /* MemDMA Stream 0 Source Interrupt/Status Register */
359#define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C /* MemDMA Stream 0 Source Peripheral Map Register */
360
361/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */
362
363#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
364#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
365#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
366#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
367#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
368
369/*********************************************************************************** */
370/* System MMR Register Bits */
371/******************************************************************************* */
372
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]373/* CHIPID Masks */
374#define CHIPID_VERSION 0xF0000000
375#define CHIPID_FAMILY 0x0FFFF000
376#define CHIPID_MANUFACTURE 0x00000FFE
377
378/* SWRST Mask */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]379#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
380#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
381#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
382#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
383#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
384
385/* SYSCR Masks */
386#define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */
387#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]388
389/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
390
391 /* SIC_IAR0 Masks */
392
393#define P0_IVG(x) ((x)-7) /* Peripheral #0 assigned IVG #x */
394#define P1_IVG(x) ((x)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
395#define P2_IVG(x) ((x)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
396#define P3_IVG(x) ((x)-7) << 0xC /* Peripheral #3 assigned IVG #x */
397#define P4_IVG(x) ((x)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
398#define P5_IVG(x) ((x)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
399#define P6_IVG(x) ((x)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
400#define P7_IVG(x) ((x)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
401
402/* SIC_IAR1 Masks */
403
404#define P8_IVG(x) ((x)-7) /* Peripheral #8 assigned IVG #x */
405#define P9_IVG(x) ((x)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
406#define P10_IVG(x) ((x)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
407#define P11_IVG(x) ((x)-7) << 0xC /* Peripheral #11 assigned IVG #x */
408#define P12_IVG(x) ((x)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
409#define P13_IVG(x) ((x)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
410#define P14_IVG(x) ((x)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
411#define P15_IVG(x) ((x)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
412
413/* SIC_IAR2 Masks */
414#define P16_IVG(x) ((x)-7) /* Peripheral #16 assigned IVG #x */
415#define P17_IVG(x) ((x)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
416#define P18_IVG(x) ((x)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
417#define P19_IVG(x) ((x)-7) << 0xC /* Peripheral #19 assigned IVG #x */
418#define P20_IVG(x) ((x)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
419#define P21_IVG(x) ((x)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
420#define P22_IVG(x) ((x)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
421#define P23_IVG(x) ((x)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
422
423/* SIC_IMASK Masks */
424#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
425#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
426#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */
427#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
428
429/* SIC_IWR Masks */
430#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
431#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
432#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
433#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
434
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]435/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
436
437/* PPI_CONTROL Masks */
438#define PORT_EN 0x00000001 /* PPI Port Enable */
439#define PORT_DIR 0x00000002 /* PPI Port Direction */
440#define XFR_TYPE 0x0000000C /* PPI Transfer Type */
441#define PORT_CFG 0x00000030 /* PPI Port Configuration */
442#define FLD_SEL 0x00000040 /* PPI Active Field Select */
443#define PACK_EN 0x00000080 /* PPI Packing Mode */
444#define DMA32 0x00000100 /* PPI 32-bit DMA Enable */
445#define SKIP_EN 0x00000200 /* PPI Skip Element Enable */
446#define SKIP_EO 0x00000400 /* PPI Skip Even/Odd Elements */
447#define DLENGTH 0x00003800 /* PPI Data Length */
448#define DLEN_8 0x0000 /* Data Length = 8 Bits */
449#define DLEN_10 0x0800 /* Data Length = 10 Bits */
450#define DLEN_11 0x1000 /* Data Length = 11 Bits */
451#define DLEN_12 0x1800 /* Data Length = 12 Bits */
452#define DLEN_13 0x2000 /* Data Length = 13 Bits */
453#define DLEN_14 0x2800 /* Data Length = 14 Bits */
454#define DLEN_15 0x3000 /* Data Length = 15 Bits */
455#define DLEN_16 0x3800 /* Data Length = 16 Bits */
456#define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */
457#define POL 0x0000C000 /* PPI Signal Polarities */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]458#define POLC 0x4000 /* PPI Clock Polarity */
459#define POLS 0x8000 /* PPI Frame Sync Polarity */
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]460
461/* PPI_STATUS Masks */
462#define FLD 0x00000400 /* Field Indicator */
463#define FT_ERR 0x00000800 /* Frame Track Error */
464#define OVR 0x00001000 /* FIFO Overflow Error */
465#define UNDR 0x00002000 /* FIFO Underrun Error */
466#define ERR_DET 0x00004000 /* Error Detected Indicator */
467#define ERR_NCOR 0x00008000 /* Error Not Corrected Indicator */
468
469/* ********** DMA CONTROLLER MASKS *********************8 */
470
Mike Frysinger00d24602009-10-20 17:20:21 +0000[diff] [blame]471/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]472
473#define CTYPE 0x00000040 /* DMA Channel Type Indicator */
474#define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */
475#define PCAP8 0x00000080 /* DMA 8-bit Operation Indicator */
476#define PCAP16 0x00000100 /* DMA 16-bit Operation Indicator */
477#define PCAP32 0x00000200 /* DMA 32-bit Operation Indicator */
478#define PCAPWR 0x00000400 /* DMA Write Operation Indicator */
479#define PCAPRD 0x00000800 /* DMA Read Operation Indicator */
480#define PMAP 0x00007000 /* DMA Peripheral Map Field */
481
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]482#define PMAP_PPI 0x0000 /* PMAP PPI Port DMA */
483#define PMAP_SPORT0RX 0x1000 /* PMAP SPORT0 Receive DMA */
484#define PMAP_SPORT0TX 0x2000 /* PMAP SPORT0 Transmit DMA */
485#define PMAP_SPORT1RX 0x3000 /* PMAP SPORT1 Receive DMA */
486#define PMAP_SPORT1TX 0x4000 /* PMAP SPORT1 Transmit DMA */
487#define PMAP_SPI 0x5000 /* PMAP SPI DMA */
488#define PMAP_UARTRX 0x6000 /* PMAP UART Receive DMA */
489#define PMAP_UARTTX 0x7000 /* PMAP UART Transmit DMA */
490
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]491/* ************* GENERAL PURPOSE TIMER MASKS ******************** */
492
493/* PWM Timer bit definitions */
494
495/* TIMER_ENABLE Register */
496#define TIMEN0 0x0001
497#define TIMEN1 0x0002
498#define TIMEN2 0x0004
499
500#define TIMEN0_P 0x00
501#define TIMEN1_P 0x01
502#define TIMEN2_P 0x02
503
504/* TIMER_DISABLE Register */
505#define TIMDIS0 0x0001
506#define TIMDIS1 0x0002
507#define TIMDIS2 0x0004
508
509#define TIMDIS0_P 0x00
510#define TIMDIS1_P 0x01
511#define TIMDIS2_P 0x02
512
513/* TIMER_STATUS Register */
514#define TIMIL0 0x0001
515#define TIMIL1 0x0002
516#define TIMIL2 0x0004
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]517#define TOVF_ERR0 0x0010 /* Timer 0 Counter Overflow */
518#define TOVF_ERR1 0x0020 /* Timer 1 Counter Overflow */
519#define TOVF_ERR2 0x0040 /* Timer 2 Counter Overflow */
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]520#define TRUN0 0x1000
521#define TRUN1 0x2000
522#define TRUN2 0x4000
523
524#define TIMIL0_P 0x00
525#define TIMIL1_P 0x01
526#define TIMIL2_P 0x02
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]527#define TOVF_ERR0_P 0x04
528#define TOVF_ERR1_P 0x05
529#define TOVF_ERR2_P 0x06
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]530#define TRUN0_P 0x0C
531#define TRUN1_P 0x0D
532#define TRUN2_P 0x0E
533
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]534/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
535#define TOVL_ERR0 TOVF_ERR0
536#define TOVL_ERR1 TOVF_ERR1
537#define TOVL_ERR2 TOVF_ERR2
538#define TOVL_ERR0_P TOVF_ERR0_P
539#define TOVL_ERR1_P TOVF_ERR1_P
540#define TOVL_ERR2_P TOVF_ERR2_P
541
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]542/* TIMERx_CONFIG Registers */
543#define PWM_OUT 0x0001
544#define WDTH_CAP 0x0002
545#define EXT_CLK 0x0003
546#define PULSE_HI 0x0004
547#define PERIOD_CNT 0x0008
548#define IRQ_ENA 0x0010
549#define TIN_SEL 0x0020
550#define OUT_DIS 0x0040
551#define CLK_SEL 0x0080
552#define TOGGLE_HI 0x0100
553#define EMU_RUN 0x0200
554#define ERR_TYP(x) ((x & 0x03) << 14)
555
556#define TMODE_P0 0x00
557#define TMODE_P1 0x01
558#define PULSE_HI_P 0x02
559#define PERIOD_CNT_P 0x03
560#define IRQ_ENA_P 0x04
561#define TIN_SEL_P 0x05
562#define OUT_DIS_P 0x06
563#define CLK_SEL_P 0x07
564#define TOGGLE_HI_P 0x08
565#define EMU_RUN_P 0x09
566#define ERR_TYP_P0 0x0E
567#define ERR_TYP_P1 0x0F
568
569/*/ ****************** PROGRAMMABLE FLAG MASKS ********************* */
570
571/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */
572#define PF0 0x0001
573#define PF1 0x0002
574#define PF2 0x0004
575#define PF3 0x0008
576#define PF4 0x0010
577#define PF5 0x0020
578#define PF6 0x0040
579#define PF7 0x0080
580#define PF8 0x0100
581#define PF9 0x0200
582#define PF10 0x0400
583#define PF11 0x0800
584#define PF12 0x1000
585#define PF13 0x2000
586#define PF14 0x4000
587#define PF15 0x8000
588
589/* General Purpose IO (0xFFC00700 - 0xFFC007FF) BIT POSITIONS */
590#define PF0_P 0
591#define PF1_P 1
592#define PF2_P 2
593#define PF3_P 3
594#define PF4_P 4
595#define PF5_P 5
596#define PF6_P 6
597#define PF7_P 7
598#define PF8_P 8
599#define PF9_P 9
600#define PF10_P 10
601#define PF11_P 11
602#define PF12_P 12
603#define PF13_P 13
604#define PF14_P 14
605#define PF15_P 15
606
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]607/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
608
609/* AMGCTL Masks */
610#define AMCKEN 0x00000001 /* Enable CLKOUT */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]611#define AMBEN_NONE 0x00000000 /* All Banks Disabled */
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]612#define AMBEN_B0 0x00000002 /* Enable Asynchronous Memory Bank 0 only */
613#define AMBEN_B0_B1 0x00000004 /* Enable Asynchronous Memory Banks 0 & 1 only */
614#define AMBEN_B0_B1_B2 0x00000006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */
615#define AMBEN_ALL 0x00000008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
616
617/* AMGCTL Bit Positions */
618#define AMCKEN_P 0x00000000 /* Enable CLKOUT */
619#define AMBEN_P0 0x00000001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
620#define AMBEN_P1 0x00000002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */
621#define AMBEN_P2 0x00000003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
622
623/* AMBCTL0 Masks */
624#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */
625#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */
626#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */
627#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */
628#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */
629#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */
630#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
631#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
632#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
633#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
634#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
635#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
636#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
637#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
638#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */
639#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */
640#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */
641#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */
642#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */
643#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */
644#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */
645#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */
646#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */
647#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */
648#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */
649#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */
650#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */
651#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */
652#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */
653#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */
654#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */
655#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */
656#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */
657#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */
658#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */
659#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */
660#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */
661#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */
662#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */
663#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */
664#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */
665#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */
666#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */
667#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */
668#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */
669#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */
670#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */
671#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */
672#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */
673#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */
674#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
675#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
676#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
677#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
678#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
679#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
680#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
681#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
682#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */
683#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */
684#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */
685#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */
686#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */
687#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */
688#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */
689#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */
690#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */
691#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */
692#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */
693#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */
694#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */
695#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */
696#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */
697#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */
698#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */
699#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */
700#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */
701#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */
702#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */
703#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */
704#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */
705#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */
706#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */
707#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */
708#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */
709#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */
710#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */
711#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */
712
713/* AMBCTL1 Masks */
714#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */
715#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */
716#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */
717#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */
718#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */
719#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */
720#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
721#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
722#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
723#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
724#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
725#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
726#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
727#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
728#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */
729#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */
730#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */
731#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */
732#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */
733#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */
734#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */
735#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */
736#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */
737#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */
738#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */
739#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */
740#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */
741#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */
742#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */
743#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */
744#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */
745#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */
746#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */
747#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */
748#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */
749#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */
750#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */
751#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */
752#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */
753#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */
754#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */
755#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */
756#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */
757#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */
758#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */
759#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */
760#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */
761#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */
762#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */
763#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */
764#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
765#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
766#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
767#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
768#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
769#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
770#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
771#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
772#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */
773#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */
774#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */
775#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */
776#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */
777#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */
778#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */
779#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */
780#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */
781#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */
782#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */
783#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */
784#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */
785#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */
786#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */
787#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */
788#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */
789#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */
790#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */
791#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */
792#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */
793#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */
794#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */
795#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */
796#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */
797#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */
798#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */
799#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */
800#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */
801#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */
802
803/* ********************** SDRAM CONTROLLER MASKS *************************** */
804
805/* SDGCTL Masks */
806#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
807#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */
808#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */
809#define PFE 0x00000010 /* Enable SDRAM prefetch */
810#define PFP 0x00000020 /* Prefetch has priority over AMC requests */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]811#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
812#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
813#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]814#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
815#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
816#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
817#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
818#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
819#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
820#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
821#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
822#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
823#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
824#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
825#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
826#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
827#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
828#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
829#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
830#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
831#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
832#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
833#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
834#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
835#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
836#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
837#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
838#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
839#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
840#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
841#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
842#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
843#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
844#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
845#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
846#define PUPSD 0x00200000 /*Power-up start delay */
847#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
848#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
849#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */
850#define EBUFE 0x02000000 /* Enable external buffering timing */
851#define FBBRW 0x04000000 /* Fast back-to-back read write enable */
852#define EMREN 0x10000000 /* Extended mode register enable */
853#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */
854#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */
855
856/* EBIU_SDBCTL Masks */
857#define EBE 0x00000001 /* Enable SDRAM external bank */
858#define EBSZ_16 0x00000000 /* SDRAM external bank size = 16MB */
859#define EBSZ_32 0x00000002 /* SDRAM external bank size = 32MB */
860#define EBSZ_64 0x00000004 /* SDRAM external bank size = 64MB */
861#define EBSZ_128 0x00000006 /* SDRAM external bank size = 128MB */
862#define EBCAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
863#define EBCAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */
864#define EBCAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */
865#define EBCAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */
866
867/* EBIU_SDSTAT Masks */
868#define SDCI 0x00000001 /* SDRAM controller is idle */
869#define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */
870#define SDPUA 0x00000004 /* SDRAM power up active */
871#define SDRS 0x00000008 /* SDRAM is in reset state */
872#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */
873#define BGSTAT 0x00000020 /* Bus granted */
874
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]875
876#endif /* _DEF_BF532_H */