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Michael Hennerich5610db62007-07-12 12:32:52 +08001#ifndef _MACH_PORTMUX_H_
2#define _MACH_PORTMUX_H_
3
Michael Hennerichfac3cf42007-12-24 20:07:03 +08004#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
5
Michael Hennerich5610db62007-07-12 12:32:52 +08006#define P_PPI0_CLK (P_DONTCARE)
7#define P_PPI0_FS1 (P_DONTCARE)
8#define P_PPI0_FS2 (P_DONTCARE)
9#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF3))
10#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF4))
11#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF5))
12#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF6))
13#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF7))
14#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF8))
15#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF9))
16#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF10))
17#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF11))
18#define P_PPI0_D0 (P_DONTCARE)
19#define P_PPI0_D1 (P_DONTCARE)
20#define P_PPI0_D2 (P_DONTCARE)
21#define P_PPI0_D3 (P_DONTCARE)
22#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF15))
23#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF14))
24#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF13))
25#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF12))
26
27#define P_SPORT1_TSCLK (P_DONTCARE)
28#define P_SPORT1_RSCLK (P_DONTCARE)
29#define P_SPORT0_TSCLK (P_DONTCARE)
30#define P_SPORT0_RSCLK (P_DONTCARE)
31#define P_UART0_RX (P_DONTCARE)
32#define P_UART0_TX (P_DONTCARE)
33#define P_SPORT1_DRSEC (P_DONTCARE)
34#define P_SPORT1_RFS (P_DONTCARE)
35#define P_SPORT1_DTPRI (P_DONTCARE)
36#define P_SPORT1_DTSEC (P_DONTCARE)
37#define P_SPORT1_TFS (P_DONTCARE)
38#define P_SPORT1_DRPRI (P_DONTCARE)
39#define P_SPORT0_DRSEC (P_DONTCARE)
40#define P_SPORT0_RFS (P_DONTCARE)
41#define P_SPORT0_DTPRI (P_DONTCARE)
42#define P_SPORT0_DTSEC (P_DONTCARE)
43#define P_SPORT0_TFS (P_DONTCARE)
44#define P_SPORT0_DRPRI (P_DONTCARE)
45
46#define P_SPI0_MOSI (P_DONTCARE)
Michael Hennerichcc2f81a2007-12-04 23:45:13 -080047#define P_SPI0_MISO (P_DONTCARE)
Michael Hennerich5610db62007-07-12 12:32:52 +080048#define P_SPI0_SCK (P_DONTCARE)
49#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7))
50#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6))
51#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5))
52#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4))
53#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3))
54#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
55#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
56#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
Sonic Zhangb52dae32009-02-04 16:49:45 +080057#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
Michael Hennerich5610db62007-07-12 12:32:52 +080058
59#define P_TMR2 (P_DONTCARE)
60#define P_TMR1 (P_DONTCARE)
61#define P_TMR0 (P_DONTCARE)
62#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF1))
63
Michael Hennerich5610db62007-07-12 12:32:52 +080064#endif /* _MACH_PORTMUX_H_ */