blob: c2b813f51846dd2b6d2834ec21ec902f2c523ec7 [file] [log] [blame]
Kalle Valo2f01a1f2009-04-29 23:33:31 +03001/*
Kalle Valo80301cd2009-06-12 14:17:39 +03002 * This file is part of wl1251
Kalle Valo2f01a1f2009-04-29 23:33:31 +03003 *
4 * Copyright (C) 2008 Nokia Corporation
5 *
6 * Contact: Kalle Valo <kalle.valo@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 */
23
24#include <linux/module.h>
25#include <linux/crc7.h>
26#include <linux/spi/spi.h>
27
Kalle Valo13674112009-06-12 14:17:25 +030028#include "wl1251.h"
Kalle Valo2f01a1f2009-04-29 23:33:31 +030029#include "reg.h"
Kalle Valoef2f8d42009-06-12 14:17:19 +030030#include "wl1251_spi.h"
Kalle Valo2f01a1f2009-04-29 23:33:31 +030031
Kalle Valo80301cd2009-06-12 14:17:39 +030032static int wl1251_translate_reg_addr(struct wl1251 *wl, int addr)
Kalle Valo2f01a1f2009-04-29 23:33:31 +030033{
34 /* If the address is lower than REGISTERS_BASE, it means that this is
35 * a chip-specific register address, so look it up in the registers
36 * table */
37 if (addr < REGISTERS_BASE) {
38 /* Make sure we don't go over the table */
39 if (addr >= ACX_REG_TABLE_LEN) {
Kalle Valo80301cd2009-06-12 14:17:39 +030040 wl1251_error("address out of range (%d)", addr);
Kalle Valo2f01a1f2009-04-29 23:33:31 +030041 return -EINVAL;
42 }
43 addr = wl->chip.acx_reg_table[addr];
44 }
45
46 return addr - wl->physical_reg_addr + wl->virtual_reg_addr;
47}
48
Kalle Valo80301cd2009-06-12 14:17:39 +030049static int wl1251_translate_mem_addr(struct wl1251 *wl, int addr)
Kalle Valo2f01a1f2009-04-29 23:33:31 +030050{
51 return addr - wl->physical_mem_addr + wl->virtual_mem_addr;
52}
53
54
Kalle Valo80301cd2009-06-12 14:17:39 +030055void wl1251_spi_reset(struct wl1251 *wl)
Kalle Valo2f01a1f2009-04-29 23:33:31 +030056{
57 u8 *cmd;
58 struct spi_transfer t;
59 struct spi_message m;
60
61 cmd = kzalloc(WSPI_INIT_CMD_LEN, GFP_KERNEL);
62 if (!cmd) {
Kalle Valo80301cd2009-06-12 14:17:39 +030063 wl1251_error("could not allocate cmd for spi reset");
Kalle Valo2f01a1f2009-04-29 23:33:31 +030064 return;
65 }
66
67 memset(&t, 0, sizeof(t));
68 spi_message_init(&m);
69
70 memset(cmd, 0xff, WSPI_INIT_CMD_LEN);
71
72 t.tx_buf = cmd;
73 t.len = WSPI_INIT_CMD_LEN;
74 spi_message_add_tail(&t, &m);
75
76 spi_sync(wl->spi, &m);
77
Kalle Valo80301cd2009-06-12 14:17:39 +030078 wl1251_dump(DEBUG_SPI, "spi reset -> ", cmd, WSPI_INIT_CMD_LEN);
Kalle Valo2f01a1f2009-04-29 23:33:31 +030079}
80
Kalle Valo80301cd2009-06-12 14:17:39 +030081void wl1251_spi_init(struct wl1251 *wl)
Kalle Valo2f01a1f2009-04-29 23:33:31 +030082{
83 u8 crc[WSPI_INIT_CMD_CRC_LEN], *cmd;
84 struct spi_transfer t;
85 struct spi_message m;
86
87 cmd = kzalloc(WSPI_INIT_CMD_LEN, GFP_KERNEL);
88 if (!cmd) {
Kalle Valo80301cd2009-06-12 14:17:39 +030089 wl1251_error("could not allocate cmd for spi init");
Kalle Valo2f01a1f2009-04-29 23:33:31 +030090 return;
91 }
92
93 memset(crc, 0, sizeof(crc));
94 memset(&t, 0, sizeof(t));
95 spi_message_init(&m);
96
97 /*
98 * Set WSPI_INIT_COMMAND
99 * the data is being send from the MSB to LSB
100 */
101 cmd[2] = 0xff;
102 cmd[3] = 0xff;
103 cmd[1] = WSPI_INIT_CMD_START | WSPI_INIT_CMD_TX;
104 cmd[0] = 0;
105 cmd[7] = 0;
106 cmd[6] |= HW_ACCESS_WSPI_INIT_CMD_MASK << 3;
107 cmd[6] |= HW_ACCESS_WSPI_FIXED_BUSY_LEN & WSPI_INIT_CMD_FIXEDBUSY_LEN;
108
109 if (HW_ACCESS_WSPI_FIXED_BUSY_LEN == 0)
110 cmd[5] |= WSPI_INIT_CMD_DIS_FIXEDBUSY;
111 else
112 cmd[5] |= WSPI_INIT_CMD_EN_FIXEDBUSY;
113
114 cmd[5] |= WSPI_INIT_CMD_IOD | WSPI_INIT_CMD_IP | WSPI_INIT_CMD_CS
115 | WSPI_INIT_CMD_WSPI | WSPI_INIT_CMD_WS;
116
117 crc[0] = cmd[1];
118 crc[1] = cmd[0];
119 crc[2] = cmd[7];
120 crc[3] = cmd[6];
121 crc[4] = cmd[5];
122
123 cmd[4] |= crc7(0, crc, WSPI_INIT_CMD_CRC_LEN) << 1;
124 cmd[4] |= WSPI_INIT_CMD_END;
125
126 t.tx_buf = cmd;
127 t.len = WSPI_INIT_CMD_LEN;
128 spi_message_add_tail(&t, &m);
129
130 spi_sync(wl->spi, &m);
131
Kalle Valo80301cd2009-06-12 14:17:39 +0300132 wl1251_dump(DEBUG_SPI, "spi init -> ", cmd, WSPI_INIT_CMD_LEN);
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300133}
134
135/* Set the SPI partitions to access the chip addresses
136 *
137 * There are two VIRTUAL (SPI) partitions (the memory partition and the
138 * registers partition), which are mapped to two different areas of the
139 * PHYSICAL (hardware) memory. This function also makes other checks to
140 * ensure that the partitions are not overlapping. In the diagram below, the
141 * memory partition comes before the register partition, but the opposite is
142 * also supported.
143 *
144 * PHYSICAL address
145 * space
146 *
147 * | |
148 * ...+----+--> mem_start
149 * VIRTUAL address ... | |
150 * space ... | | [PART_0]
151 * ... | |
152 * 0x00000000 <--+----+... ...+----+--> mem_start + mem_size
153 * | | ... | |
154 * |MEM | ... | |
155 * | | ... | |
156 * part_size <--+----+... | | {unused area)
157 * | | ... | |
158 * |REG | ... | |
159 * part_size | | ... | |
160 * + <--+----+... ...+----+--> reg_start
161 * reg_size ... | |
162 * ... | | [PART_1]
163 * ... | |
164 * ...+----+--> reg_start + reg_size
165 * | |
166 *
167 */
Kalle Valo80301cd2009-06-12 14:17:39 +0300168int wl1251_set_partition(struct wl1251 *wl,
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300169 u32 mem_start, u32 mem_size,
170 u32 reg_start, u32 reg_size)
171{
Kalle Valo80301cd2009-06-12 14:17:39 +0300172 struct wl1251_partition *partition;
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300173 struct spi_transfer t;
174 struct spi_message m;
Kalle Valo8d47cdb2009-06-12 14:14:41 +0300175 size_t len, cmd_len;
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300176 u32 *cmd;
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300177 int addr;
178
Kalle Valo80301cd2009-06-12 14:17:39 +0300179 cmd_len = sizeof(u32) + 2 * sizeof(struct wl1251_partition);
Kalle Valo8d47cdb2009-06-12 14:14:41 +0300180 cmd = kzalloc(cmd_len, GFP_KERNEL);
181 if (!cmd)
182 return -ENOMEM;
183
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300184 spi_message_init(&m);
185 memset(&t, 0, sizeof(t));
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300186
Kalle Valo80301cd2009-06-12 14:17:39 +0300187 partition = (struct wl1251_partition *) (cmd + 1);
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300188 addr = HW_ACCESS_PART0_SIZE_ADDR;
Kalle Valo80301cd2009-06-12 14:17:39 +0300189 len = 2 * sizeof(struct wl1251_partition);
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300190
191 *cmd |= WSPI_CMD_WRITE;
192 *cmd |= (len << WSPI_CMD_BYTE_LENGTH_OFFSET) & WSPI_CMD_BYTE_LENGTH;
193 *cmd |= addr & WSPI_CMD_BYTE_ADDR;
194
Kalle Valo80301cd2009-06-12 14:17:39 +0300195 wl1251_debug(DEBUG_SPI, "mem_start %08X mem_size %08X",
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300196 mem_start, mem_size);
Kalle Valo80301cd2009-06-12 14:17:39 +0300197 wl1251_debug(DEBUG_SPI, "reg_start %08X reg_size %08X",
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300198 reg_start, reg_size);
199
200 /* Make sure that the two partitions together don't exceed the
201 * address range */
202 if ((mem_size + reg_size) > HW_ACCESS_MEMORY_MAX_RANGE) {
Kalle Valo80301cd2009-06-12 14:17:39 +0300203 wl1251_debug(DEBUG_SPI, "Total size exceeds maximum virtual"
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300204 " address range. Truncating partition[0].");
205 mem_size = HW_ACCESS_MEMORY_MAX_RANGE - reg_size;
Kalle Valo80301cd2009-06-12 14:17:39 +0300206 wl1251_debug(DEBUG_SPI, "mem_start %08X mem_size %08X",
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300207 mem_start, mem_size);
Kalle Valo80301cd2009-06-12 14:17:39 +0300208 wl1251_debug(DEBUG_SPI, "reg_start %08X reg_size %08X",
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300209 reg_start, reg_size);
210 }
211
212 if ((mem_start < reg_start) &&
213 ((mem_start + mem_size) > reg_start)) {
214 /* Guarantee that the memory partition doesn't overlap the
215 * registers partition */
Kalle Valo80301cd2009-06-12 14:17:39 +0300216 wl1251_debug(DEBUG_SPI, "End of partition[0] is "
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300217 "overlapping partition[1]. Adjusted.");
218 mem_size = reg_start - mem_start;
Kalle Valo80301cd2009-06-12 14:17:39 +0300219 wl1251_debug(DEBUG_SPI, "mem_start %08X mem_size %08X",
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300220 mem_start, mem_size);
Kalle Valo80301cd2009-06-12 14:17:39 +0300221 wl1251_debug(DEBUG_SPI, "reg_start %08X reg_size %08X",
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300222 reg_start, reg_size);
223 } else if ((reg_start < mem_start) &&
224 ((reg_start + reg_size) > mem_start)) {
225 /* Guarantee that the register partition doesn't overlap the
226 * memory partition */
Kalle Valo80301cd2009-06-12 14:17:39 +0300227 wl1251_debug(DEBUG_SPI, "End of partition[1] is"
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300228 " overlapping partition[0]. Adjusted.");
229 reg_size = mem_start - reg_start;
Kalle Valo80301cd2009-06-12 14:17:39 +0300230 wl1251_debug(DEBUG_SPI, "mem_start %08X mem_size %08X",
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300231 mem_start, mem_size);
Kalle Valo80301cd2009-06-12 14:17:39 +0300232 wl1251_debug(DEBUG_SPI, "reg_start %08X reg_size %08X",
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300233 reg_start, reg_size);
234 }
235
236 partition[0].start = mem_start;
237 partition[0].size = mem_size;
238 partition[1].start = reg_start;
239 partition[1].size = reg_size;
240
241 wl->physical_mem_addr = mem_start;
242 wl->physical_reg_addr = reg_start;
243
244 wl->virtual_mem_addr = 0;
245 wl->virtual_reg_addr = mem_size;
246
Kalle Valo8d47cdb2009-06-12 14:14:41 +0300247 t.tx_buf = cmd;
248 t.len = cmd_len;
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300249 spi_message_add_tail(&t, &m);
250
251 spi_sync(wl->spi, &m);
Kalle Valo8d47cdb2009-06-12 14:14:41 +0300252
253 kfree(cmd);
254
255 return 0;
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300256}
257
Kalle Valob8010792009-08-07 13:32:48 +0300258void wl1251_spi_read(struct wl1251 *wl, int addr, void *buf, size_t len)
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300259{
260 struct spi_transfer t[3];
261 struct spi_message m;
Kalle Valo5262c122009-06-12 14:14:55 +0300262 u8 *busy_buf;
Kalle Valo56343a32009-06-12 14:14:47 +0300263 u32 *cmd;
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300264
Kalle Valo56343a32009-06-12 14:14:47 +0300265 cmd = &wl->buffer_cmd;
Kalle Valo5262c122009-06-12 14:14:55 +0300266 busy_buf = wl->buffer_busyword;
Kalle Valo56343a32009-06-12 14:14:47 +0300267
268 *cmd = 0;
269 *cmd |= WSPI_CMD_READ;
270 *cmd |= (len << WSPI_CMD_BYTE_LENGTH_OFFSET) & WSPI_CMD_BYTE_LENGTH;
271 *cmd |= addr & WSPI_CMD_BYTE_ADDR;
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300272
273 spi_message_init(&m);
274 memset(t, 0, sizeof(t));
275
Kalle Valo56343a32009-06-12 14:14:47 +0300276 t[0].tx_buf = cmd;
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300277 t[0].len = 4;
278 spi_message_add_tail(&t[0], &m);
279
280 /* Busy and non busy words read */
281 t[1].rx_buf = busy_buf;
Kalle Valo80301cd2009-06-12 14:17:39 +0300282 t[1].len = WL1251_BUSY_WORD_LEN;
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300283 spi_message_add_tail(&t[1], &m);
284
285 t[2].rx_buf = buf;
286 t[2].len = len;
287 spi_message_add_tail(&t[2], &m);
288
289 spi_sync(wl->spi, &m);
290
291 /* FIXME: check busy words */
292
Kalle Valo80301cd2009-06-12 14:17:39 +0300293 wl1251_dump(DEBUG_SPI, "spi_read cmd -> ", cmd, sizeof(*cmd));
294 wl1251_dump(DEBUG_SPI, "spi_read buf <- ", buf, len);
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300295}
296
Kalle Valob8010792009-08-07 13:32:48 +0300297void wl1251_spi_write(struct wl1251 *wl, int addr, void *buf, size_t len)
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300298{
299 struct spi_transfer t[2];
300 struct spi_message m;
Kalle Valo56343a32009-06-12 14:14:47 +0300301 u32 *cmd;
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300302
Kalle Valo56343a32009-06-12 14:14:47 +0300303 cmd = &wl->buffer_cmd;
304
305 *cmd = 0;
306 *cmd |= WSPI_CMD_WRITE;
307 *cmd |= (len << WSPI_CMD_BYTE_LENGTH_OFFSET) & WSPI_CMD_BYTE_LENGTH;
308 *cmd |= addr & WSPI_CMD_BYTE_ADDR;
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300309
310 spi_message_init(&m);
311 memset(t, 0, sizeof(t));
312
Kalle Valo56343a32009-06-12 14:14:47 +0300313 t[0].tx_buf = cmd;
314 t[0].len = sizeof(*cmd);
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300315 spi_message_add_tail(&t[0], &m);
316
317 t[1].tx_buf = buf;
318 t[1].len = len;
319 spi_message_add_tail(&t[1], &m);
320
321 spi_sync(wl->spi, &m);
322
Kalle Valo80301cd2009-06-12 14:17:39 +0300323 wl1251_dump(DEBUG_SPI, "spi_write cmd -> ", cmd, sizeof(*cmd));
324 wl1251_dump(DEBUG_SPI, "spi_write buf -> ", buf, len);
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300325}
326
Kalle Valo80301cd2009-06-12 14:17:39 +0300327void wl1251_spi_mem_read(struct wl1251 *wl, int addr, void *buf,
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300328 size_t len)
329{
330 int physical;
331
Kalle Valo80301cd2009-06-12 14:17:39 +0300332 physical = wl1251_translate_mem_addr(wl, addr);
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300333
Kalle Valob8010792009-08-07 13:32:48 +0300334 wl1251_spi_read(wl, physical, buf, len);
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300335}
336
Kalle Valo80301cd2009-06-12 14:17:39 +0300337void wl1251_spi_mem_write(struct wl1251 *wl, int addr, void *buf,
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300338 size_t len)
339{
340 int physical;
341
Kalle Valo80301cd2009-06-12 14:17:39 +0300342 physical = wl1251_translate_mem_addr(wl, addr);
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300343
Kalle Valob8010792009-08-07 13:32:48 +0300344 wl1251_spi_write(wl, physical, buf, len);
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300345}
346
Kalle Valob8010792009-08-07 13:32:48 +0300347void wl1251_spi_reg_read(struct wl1251 *wl, int addr, void *buf, size_t len)
Luciano Coelhoa336e262009-06-12 14:15:22 +0300348{
349 int physical;
350
Kalle Valo80301cd2009-06-12 14:17:39 +0300351 physical = wl1251_translate_reg_addr(wl, addr);
Luciano Coelhoa336e262009-06-12 14:15:22 +0300352
Kalle Valob8010792009-08-07 13:32:48 +0300353 wl1251_spi_read(wl, physical, buf, len);
Luciano Coelhoa336e262009-06-12 14:15:22 +0300354}
355
Kalle Valob8010792009-08-07 13:32:48 +0300356void wl1251_spi_reg_write(struct wl1251 *wl, int addr, void *buf, size_t len)
Luciano Coelhoa336e262009-06-12 14:15:22 +0300357{
358 int physical;
359
Kalle Valo80301cd2009-06-12 14:17:39 +0300360 physical = wl1251_translate_reg_addr(wl, addr);
Luciano Coelhoa336e262009-06-12 14:15:22 +0300361
Kalle Valob8010792009-08-07 13:32:48 +0300362 wl1251_spi_write(wl, physical, buf, len);
Luciano Coelhoa336e262009-06-12 14:15:22 +0300363}
364
Kalle Valo80301cd2009-06-12 14:17:39 +0300365u32 wl1251_mem_read32(struct wl1251 *wl, int addr)
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300366{
Kalle Valo80301cd2009-06-12 14:17:39 +0300367 return wl1251_read32(wl, wl1251_translate_mem_addr(wl, addr));
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300368}
369
Kalle Valo80301cd2009-06-12 14:17:39 +0300370void wl1251_mem_write32(struct wl1251 *wl, int addr, u32 val)
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300371{
Kalle Valo80301cd2009-06-12 14:17:39 +0300372 wl1251_write32(wl, wl1251_translate_mem_addr(wl, addr), val);
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300373}
374
Kalle Valo80301cd2009-06-12 14:17:39 +0300375u32 wl1251_reg_read32(struct wl1251 *wl, int addr)
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300376{
Kalle Valo80301cd2009-06-12 14:17:39 +0300377 return wl1251_read32(wl, wl1251_translate_reg_addr(wl, addr));
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300378}
379
Kalle Valo80301cd2009-06-12 14:17:39 +0300380void wl1251_reg_write32(struct wl1251 *wl, int addr, u32 val)
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300381{
Kalle Valo80301cd2009-06-12 14:17:39 +0300382 wl1251_write32(wl, wl1251_translate_reg_addr(wl, addr), val);
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300383}