Linus Walleij | 61f135b | 2009-11-19 19:49:17 +0100 | [diff] [blame] | 1 | /* |
| 2 | * driver/dma/coh901318.c |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 ST-Ericsson |
| 5 | * License terms: GNU General Public License (GPL) version 2 |
| 6 | * DMA driver for COH 901 318 |
| 7 | * Author: Per Friden <per.friden@stericsson.com> |
| 8 | */ |
| 9 | |
| 10 | #include <linux/init.h> |
| 11 | #include <linux/module.h> |
| 12 | #include <linux/kernel.h> /* printk() */ |
| 13 | #include <linux/fs.h> /* everything... */ |
| 14 | #include <linux/slab.h> /* kmalloc() */ |
| 15 | #include <linux/dmaengine.h> |
| 16 | #include <linux/platform_device.h> |
| 17 | #include <linux/device.h> |
| 18 | #include <linux/irqreturn.h> |
| 19 | #include <linux/interrupt.h> |
| 20 | #include <linux/io.h> |
| 21 | #include <linux/uaccess.h> |
| 22 | #include <linux/debugfs.h> |
| 23 | #include <mach/coh901318.h> |
| 24 | |
| 25 | #include "coh901318_lli.h" |
| 26 | |
| 27 | #define COHC_2_DEV(cohc) (&cohc->chan.dev->device) |
| 28 | |
| 29 | #ifdef VERBOSE_DEBUG |
| 30 | #define COH_DBG(x) ({ if (1) x; 0; }) |
| 31 | #else |
| 32 | #define COH_DBG(x) ({ if (0) x; 0; }) |
| 33 | #endif |
| 34 | |
| 35 | struct coh901318_desc { |
| 36 | struct dma_async_tx_descriptor desc; |
| 37 | struct list_head node; |
| 38 | struct scatterlist *sg; |
| 39 | unsigned int sg_len; |
| 40 | struct coh901318_lli *data; |
| 41 | enum dma_data_direction dir; |
| 42 | int pending_irqs; |
| 43 | unsigned long flags; |
| 44 | }; |
| 45 | |
| 46 | struct coh901318_base { |
| 47 | struct device *dev; |
| 48 | void __iomem *virtbase; |
| 49 | struct coh901318_pool pool; |
| 50 | struct powersave pm; |
| 51 | struct dma_device dma_slave; |
| 52 | struct dma_device dma_memcpy; |
| 53 | struct coh901318_chan *chans; |
| 54 | struct coh901318_platform *platform; |
| 55 | }; |
| 56 | |
| 57 | struct coh901318_chan { |
| 58 | spinlock_t lock; |
| 59 | int allocated; |
| 60 | int completed; |
| 61 | int id; |
| 62 | int stopped; |
| 63 | |
| 64 | struct work_struct free_work; |
| 65 | struct dma_chan chan; |
| 66 | |
| 67 | struct tasklet_struct tasklet; |
| 68 | |
| 69 | struct list_head active; |
| 70 | struct list_head queue; |
| 71 | struct list_head free; |
| 72 | |
| 73 | unsigned long nbr_active_done; |
| 74 | unsigned long busy; |
| 75 | int pending_irqs; |
| 76 | |
| 77 | struct coh901318_base *base; |
| 78 | }; |
| 79 | |
| 80 | static void coh901318_list_print(struct coh901318_chan *cohc, |
| 81 | struct coh901318_lli *lli) |
| 82 | { |
Linus Walleij | 848ad12 | 2010-03-02 14:17:15 -0700 | [diff] [blame] | 83 | struct coh901318_lli *l = lli; |
Linus Walleij | 61f135b | 2009-11-19 19:49:17 +0100 | [diff] [blame] | 84 | int i = 0; |
| 85 | |
Linus Walleij | 848ad12 | 2010-03-02 14:17:15 -0700 | [diff] [blame] | 86 | while (l) { |
Linus Walleij | 61f135b | 2009-11-19 19:49:17 +0100 | [diff] [blame] | 87 | dev_vdbg(COHC_2_DEV(cohc), "i %d, lli %p, ctrl 0x%x, src 0x%x" |
Linus Walleij | 848ad12 | 2010-03-02 14:17:15 -0700 | [diff] [blame] | 88 | ", dst 0x%x, link 0x%x virt_link_addr 0x%p\n", |
Linus Walleij | 61f135b | 2009-11-19 19:49:17 +0100 | [diff] [blame] | 89 | i, l, l->control, l->src_addr, l->dst_addr, |
Linus Walleij | 848ad12 | 2010-03-02 14:17:15 -0700 | [diff] [blame] | 90 | l->link_addr, l->virt_link_addr); |
Linus Walleij | 61f135b | 2009-11-19 19:49:17 +0100 | [diff] [blame] | 91 | i++; |
Linus Walleij | 848ad12 | 2010-03-02 14:17:15 -0700 | [diff] [blame] | 92 | l = l->virt_link_addr; |
Linus Walleij | 61f135b | 2009-11-19 19:49:17 +0100 | [diff] [blame] | 93 | } |
| 94 | } |
| 95 | |
| 96 | #ifdef CONFIG_DEBUG_FS |
| 97 | |
| 98 | #define COH901318_DEBUGFS_ASSIGN(x, y) (x = y) |
| 99 | |
| 100 | static struct coh901318_base *debugfs_dma_base; |
| 101 | static struct dentry *dma_dentry; |
| 102 | |
| 103 | static int coh901318_debugfs_open(struct inode *inode, struct file *file) |
| 104 | { |
| 105 | |
| 106 | file->private_data = inode->i_private; |
| 107 | return 0; |
| 108 | } |
| 109 | |
| 110 | static int coh901318_debugfs_read(struct file *file, char __user *buf, |
| 111 | size_t count, loff_t *f_pos) |
| 112 | { |
| 113 | u64 started_channels = debugfs_dma_base->pm.started_channels; |
| 114 | int pool_count = debugfs_dma_base->pool.debugfs_pool_counter; |
| 115 | int i; |
| 116 | int ret = 0; |
| 117 | char *dev_buf; |
| 118 | char *tmp; |
| 119 | int dev_size; |
| 120 | |
| 121 | dev_buf = kmalloc(4*1024, GFP_KERNEL); |
| 122 | if (dev_buf == NULL) |
| 123 | goto err_kmalloc; |
| 124 | tmp = dev_buf; |
| 125 | |
Linus Walleij | 848ad12 | 2010-03-02 14:17:15 -0700 | [diff] [blame] | 126 | tmp += sprintf(tmp, "DMA -- enabled dma channels\n"); |
Linus Walleij | 61f135b | 2009-11-19 19:49:17 +0100 | [diff] [blame] | 127 | |
| 128 | for (i = 0; i < debugfs_dma_base->platform->max_channels; i++) |
| 129 | if (started_channels & (1 << i)) |
| 130 | tmp += sprintf(tmp, "channel %d\n", i); |
| 131 | |
| 132 | tmp += sprintf(tmp, "Pool alloc nbr %d\n", pool_count); |
| 133 | dev_size = tmp - dev_buf; |
| 134 | |
| 135 | /* No more to read if offset != 0 */ |
| 136 | if (*f_pos > dev_size) |
| 137 | goto out; |
| 138 | |
| 139 | if (count > dev_size - *f_pos) |
| 140 | count = dev_size - *f_pos; |
| 141 | |
| 142 | if (copy_to_user(buf, dev_buf + *f_pos, count)) |
| 143 | ret = -EINVAL; |
| 144 | ret = count; |
| 145 | *f_pos += count; |
| 146 | |
| 147 | out: |
| 148 | kfree(dev_buf); |
| 149 | return ret; |
| 150 | |
| 151 | err_kmalloc: |
| 152 | return 0; |
| 153 | } |
| 154 | |
| 155 | static const struct file_operations coh901318_debugfs_status_operations = { |
| 156 | .owner = THIS_MODULE, |
| 157 | .open = coh901318_debugfs_open, |
| 158 | .read = coh901318_debugfs_read, |
| 159 | }; |
| 160 | |
| 161 | |
| 162 | static int __init init_coh901318_debugfs(void) |
| 163 | { |
| 164 | |
| 165 | dma_dentry = debugfs_create_dir("dma", NULL); |
| 166 | |
| 167 | (void) debugfs_create_file("status", |
| 168 | S_IFREG | S_IRUGO, |
| 169 | dma_dentry, NULL, |
| 170 | &coh901318_debugfs_status_operations); |
| 171 | return 0; |
| 172 | } |
| 173 | |
| 174 | static void __exit exit_coh901318_debugfs(void) |
| 175 | { |
| 176 | debugfs_remove_recursive(dma_dentry); |
| 177 | } |
| 178 | |
| 179 | module_init(init_coh901318_debugfs); |
| 180 | module_exit(exit_coh901318_debugfs); |
| 181 | #else |
| 182 | |
| 183 | #define COH901318_DEBUGFS_ASSIGN(x, y) |
| 184 | |
| 185 | #endif /* CONFIG_DEBUG_FS */ |
| 186 | |
| 187 | static inline struct coh901318_chan *to_coh901318_chan(struct dma_chan *chan) |
| 188 | { |
| 189 | return container_of(chan, struct coh901318_chan, chan); |
| 190 | } |
| 191 | |
| 192 | static inline dma_addr_t |
| 193 | cohc_dev_addr(struct coh901318_chan *cohc) |
| 194 | { |
| 195 | return cohc->base->platform->chan_conf[cohc->id].dev_addr; |
| 196 | } |
| 197 | |
| 198 | static inline const struct coh901318_params * |
| 199 | cohc_chan_param(struct coh901318_chan *cohc) |
| 200 | { |
| 201 | return &cohc->base->platform->chan_conf[cohc->id].param; |
| 202 | } |
| 203 | |
| 204 | static inline const struct coh_dma_channel * |
| 205 | cohc_chan_conf(struct coh901318_chan *cohc) |
| 206 | { |
| 207 | return &cohc->base->platform->chan_conf[cohc->id]; |
| 208 | } |
| 209 | |
| 210 | static void enable_powersave(struct coh901318_chan *cohc) |
| 211 | { |
| 212 | unsigned long flags; |
| 213 | struct powersave *pm = &cohc->base->pm; |
| 214 | |
| 215 | spin_lock_irqsave(&pm->lock, flags); |
| 216 | |
| 217 | pm->started_channels &= ~(1ULL << cohc->id); |
| 218 | |
| 219 | if (!pm->started_channels) { |
| 220 | /* DMA no longer intends to access memory */ |
| 221 | cohc->base->platform->access_memory_state(cohc->base->dev, |
| 222 | false); |
| 223 | } |
| 224 | |
| 225 | spin_unlock_irqrestore(&pm->lock, flags); |
| 226 | } |
| 227 | static void disable_powersave(struct coh901318_chan *cohc) |
| 228 | { |
| 229 | unsigned long flags; |
| 230 | struct powersave *pm = &cohc->base->pm; |
| 231 | |
| 232 | spin_lock_irqsave(&pm->lock, flags); |
| 233 | |
| 234 | if (!pm->started_channels) { |
| 235 | /* DMA intends to access memory */ |
| 236 | cohc->base->platform->access_memory_state(cohc->base->dev, |
| 237 | true); |
| 238 | } |
| 239 | |
| 240 | pm->started_channels |= (1ULL << cohc->id); |
| 241 | |
| 242 | spin_unlock_irqrestore(&pm->lock, flags); |
| 243 | } |
| 244 | |
| 245 | static inline int coh901318_set_ctrl(struct coh901318_chan *cohc, u32 control) |
| 246 | { |
| 247 | int channel = cohc->id; |
| 248 | void __iomem *virtbase = cohc->base->virtbase; |
| 249 | |
| 250 | writel(control, |
| 251 | virtbase + COH901318_CX_CTRL + |
| 252 | COH901318_CX_CTRL_SPACING * channel); |
| 253 | return 0; |
| 254 | } |
| 255 | |
| 256 | static inline int coh901318_set_conf(struct coh901318_chan *cohc, u32 conf) |
| 257 | { |
| 258 | int channel = cohc->id; |
| 259 | void __iomem *virtbase = cohc->base->virtbase; |
| 260 | |
| 261 | writel(conf, |
| 262 | virtbase + COH901318_CX_CFG + |
| 263 | COH901318_CX_CFG_SPACING*channel); |
| 264 | return 0; |
| 265 | } |
| 266 | |
| 267 | |
| 268 | static int coh901318_start(struct coh901318_chan *cohc) |
| 269 | { |
| 270 | u32 val; |
| 271 | int channel = cohc->id; |
| 272 | void __iomem *virtbase = cohc->base->virtbase; |
| 273 | |
| 274 | disable_powersave(cohc); |
| 275 | |
| 276 | val = readl(virtbase + COH901318_CX_CFG + |
| 277 | COH901318_CX_CFG_SPACING * channel); |
| 278 | |
| 279 | /* Enable channel */ |
| 280 | val |= COH901318_CX_CFG_CH_ENABLE; |
| 281 | writel(val, virtbase + COH901318_CX_CFG + |
| 282 | COH901318_CX_CFG_SPACING * channel); |
| 283 | |
| 284 | return 0; |
| 285 | } |
| 286 | |
| 287 | static int coh901318_prep_linked_list(struct coh901318_chan *cohc, |
| 288 | struct coh901318_lli *data) |
| 289 | { |
| 290 | int channel = cohc->id; |
| 291 | void __iomem *virtbase = cohc->base->virtbase; |
| 292 | |
| 293 | BUG_ON(readl(virtbase + COH901318_CX_STAT + |
| 294 | COH901318_CX_STAT_SPACING*channel) & |
| 295 | COH901318_CX_STAT_ACTIVE); |
| 296 | |
| 297 | writel(data->src_addr, |
| 298 | virtbase + COH901318_CX_SRC_ADDR + |
| 299 | COH901318_CX_SRC_ADDR_SPACING * channel); |
| 300 | |
| 301 | writel(data->dst_addr, virtbase + |
| 302 | COH901318_CX_DST_ADDR + |
| 303 | COH901318_CX_DST_ADDR_SPACING * channel); |
| 304 | |
| 305 | writel(data->link_addr, virtbase + COH901318_CX_LNK_ADDR + |
| 306 | COH901318_CX_LNK_ADDR_SPACING * channel); |
| 307 | |
| 308 | writel(data->control, virtbase + COH901318_CX_CTRL + |
| 309 | COH901318_CX_CTRL_SPACING * channel); |
| 310 | |
| 311 | return 0; |
| 312 | } |
| 313 | static dma_cookie_t |
| 314 | coh901318_assign_cookie(struct coh901318_chan *cohc, |
| 315 | struct coh901318_desc *cohd) |
| 316 | { |
| 317 | dma_cookie_t cookie = cohc->chan.cookie; |
| 318 | |
| 319 | if (++cookie < 0) |
| 320 | cookie = 1; |
| 321 | |
| 322 | cohc->chan.cookie = cookie; |
| 323 | cohd->desc.cookie = cookie; |
| 324 | |
| 325 | return cookie; |
| 326 | } |
| 327 | |
| 328 | static struct coh901318_desc * |
| 329 | coh901318_desc_get(struct coh901318_chan *cohc) |
| 330 | { |
| 331 | struct coh901318_desc *desc; |
| 332 | |
| 333 | if (list_empty(&cohc->free)) { |
| 334 | /* alloc new desc because we're out of used ones |
| 335 | * TODO: alloc a pile of descs instead of just one, |
| 336 | * avoid many small allocations. |
| 337 | */ |
Linus Walleij | b87108a | 2010-03-02 14:17:20 -0700 | [diff] [blame^] | 338 | desc = kzalloc(sizeof(struct coh901318_desc), GFP_NOWAIT); |
Linus Walleij | 61f135b | 2009-11-19 19:49:17 +0100 | [diff] [blame] | 339 | if (desc == NULL) |
| 340 | goto out; |
| 341 | INIT_LIST_HEAD(&desc->node); |
Linus Walleij | b87108a | 2010-03-02 14:17:20 -0700 | [diff] [blame^] | 342 | dma_async_tx_descriptor_init(&desc->desc, &cohc->chan); |
Linus Walleij | 61f135b | 2009-11-19 19:49:17 +0100 | [diff] [blame] | 343 | } else { |
| 344 | /* Reuse an old desc. */ |
| 345 | desc = list_first_entry(&cohc->free, |
| 346 | struct coh901318_desc, |
| 347 | node); |
| 348 | list_del(&desc->node); |
Linus Walleij | b87108a | 2010-03-02 14:17:20 -0700 | [diff] [blame^] | 349 | /* Initialize it a bit so it's not insane */ |
| 350 | desc->sg = NULL; |
| 351 | desc->sg_len = 0; |
| 352 | desc->desc.callback = NULL; |
| 353 | desc->desc.callback_param = NULL; |
Linus Walleij | 61f135b | 2009-11-19 19:49:17 +0100 | [diff] [blame] | 354 | } |
| 355 | |
| 356 | out: |
| 357 | return desc; |
| 358 | } |
| 359 | |
| 360 | static void |
| 361 | coh901318_desc_free(struct coh901318_chan *cohc, struct coh901318_desc *cohd) |
| 362 | { |
| 363 | list_add_tail(&cohd->node, &cohc->free); |
| 364 | } |
| 365 | |
| 366 | /* call with irq lock held */ |
| 367 | static void |
| 368 | coh901318_desc_submit(struct coh901318_chan *cohc, struct coh901318_desc *desc) |
| 369 | { |
| 370 | list_add_tail(&desc->node, &cohc->active); |
| 371 | |
| 372 | BUG_ON(cohc->pending_irqs != 0); |
| 373 | |
| 374 | cohc->pending_irqs = desc->pending_irqs; |
| 375 | } |
| 376 | |
| 377 | static struct coh901318_desc * |
| 378 | coh901318_first_active_get(struct coh901318_chan *cohc) |
| 379 | { |
| 380 | struct coh901318_desc *d; |
| 381 | |
| 382 | if (list_empty(&cohc->active)) |
| 383 | return NULL; |
| 384 | |
| 385 | d = list_first_entry(&cohc->active, |
| 386 | struct coh901318_desc, |
| 387 | node); |
| 388 | return d; |
| 389 | } |
| 390 | |
| 391 | static void |
| 392 | coh901318_desc_remove(struct coh901318_desc *cohd) |
| 393 | { |
| 394 | list_del(&cohd->node); |
| 395 | } |
| 396 | |
| 397 | static void |
| 398 | coh901318_desc_queue(struct coh901318_chan *cohc, struct coh901318_desc *desc) |
| 399 | { |
| 400 | list_add_tail(&desc->node, &cohc->queue); |
| 401 | } |
| 402 | |
| 403 | static struct coh901318_desc * |
| 404 | coh901318_first_queued(struct coh901318_chan *cohc) |
| 405 | { |
| 406 | struct coh901318_desc *d; |
| 407 | |
| 408 | if (list_empty(&cohc->queue)) |
| 409 | return NULL; |
| 410 | |
| 411 | d = list_first_entry(&cohc->queue, |
| 412 | struct coh901318_desc, |
| 413 | node); |
| 414 | return d; |
| 415 | } |
| 416 | |
| 417 | /* |
| 418 | * DMA start/stop controls |
| 419 | */ |
| 420 | u32 coh901318_get_bytes_left(struct dma_chan *chan) |
| 421 | { |
| 422 | unsigned long flags; |
| 423 | u32 ret; |
| 424 | struct coh901318_chan *cohc = to_coh901318_chan(chan); |
| 425 | |
| 426 | spin_lock_irqsave(&cohc->lock, flags); |
| 427 | |
| 428 | /* Read transfer count value */ |
| 429 | ret = readl(cohc->base->virtbase + |
| 430 | COH901318_CX_CTRL+COH901318_CX_CTRL_SPACING * |
| 431 | cohc->id) & COH901318_CX_CTRL_TC_VALUE_MASK; |
| 432 | |
| 433 | spin_unlock_irqrestore(&cohc->lock, flags); |
| 434 | |
| 435 | return ret; |
| 436 | } |
| 437 | EXPORT_SYMBOL(coh901318_get_bytes_left); |
| 438 | |
| 439 | |
| 440 | /* Stops a transfer without losing data. Enables power save. |
| 441 | Use this function in conjunction with coh901318_continue(..) |
| 442 | */ |
| 443 | void coh901318_stop(struct dma_chan *chan) |
| 444 | { |
| 445 | u32 val; |
| 446 | unsigned long flags; |
| 447 | struct coh901318_chan *cohc = to_coh901318_chan(chan); |
| 448 | int channel = cohc->id; |
| 449 | void __iomem *virtbase = cohc->base->virtbase; |
| 450 | |
| 451 | spin_lock_irqsave(&cohc->lock, flags); |
| 452 | |
| 453 | /* Disable channel in HW */ |
| 454 | val = readl(virtbase + COH901318_CX_CFG + |
| 455 | COH901318_CX_CFG_SPACING * channel); |
| 456 | |
| 457 | /* Stopping infinit transfer */ |
| 458 | if ((val & COH901318_CX_CTRL_TC_ENABLE) == 0 && |
| 459 | (val & COH901318_CX_CFG_CH_ENABLE)) |
| 460 | cohc->stopped = 1; |
| 461 | |
| 462 | |
| 463 | val &= ~COH901318_CX_CFG_CH_ENABLE; |
| 464 | /* Enable twice, HW bug work around */ |
| 465 | writel(val, virtbase + COH901318_CX_CFG + |
| 466 | COH901318_CX_CFG_SPACING * channel); |
| 467 | writel(val, virtbase + COH901318_CX_CFG + |
| 468 | COH901318_CX_CFG_SPACING * channel); |
| 469 | |
| 470 | /* Spin-wait for it to actually go inactive */ |
| 471 | while (readl(virtbase + COH901318_CX_STAT+COH901318_CX_STAT_SPACING * |
| 472 | channel) & COH901318_CX_STAT_ACTIVE) |
| 473 | cpu_relax(); |
| 474 | |
| 475 | /* Check if we stopped an active job */ |
| 476 | if ((readl(virtbase + COH901318_CX_CTRL+COH901318_CX_CTRL_SPACING * |
| 477 | channel) & COH901318_CX_CTRL_TC_VALUE_MASK) > 0) |
| 478 | cohc->stopped = 1; |
| 479 | |
| 480 | enable_powersave(cohc); |
| 481 | |
| 482 | spin_unlock_irqrestore(&cohc->lock, flags); |
| 483 | } |
| 484 | EXPORT_SYMBOL(coh901318_stop); |
| 485 | |
| 486 | /* Continues a transfer that has been stopped via 300_dma_stop(..). |
| 487 | Power save is handled. |
| 488 | */ |
| 489 | void coh901318_continue(struct dma_chan *chan) |
| 490 | { |
| 491 | u32 val; |
| 492 | unsigned long flags; |
| 493 | struct coh901318_chan *cohc = to_coh901318_chan(chan); |
| 494 | int channel = cohc->id; |
| 495 | |
| 496 | spin_lock_irqsave(&cohc->lock, flags); |
| 497 | |
| 498 | disable_powersave(cohc); |
| 499 | |
| 500 | if (cohc->stopped) { |
| 501 | /* Enable channel in HW */ |
| 502 | val = readl(cohc->base->virtbase + COH901318_CX_CFG + |
| 503 | COH901318_CX_CFG_SPACING * channel); |
| 504 | |
| 505 | val |= COH901318_CX_CFG_CH_ENABLE; |
| 506 | |
| 507 | writel(val, cohc->base->virtbase + COH901318_CX_CFG + |
| 508 | COH901318_CX_CFG_SPACING*channel); |
| 509 | |
| 510 | cohc->stopped = 0; |
| 511 | } |
| 512 | |
| 513 | spin_unlock_irqrestore(&cohc->lock, flags); |
| 514 | } |
| 515 | EXPORT_SYMBOL(coh901318_continue); |
| 516 | |
| 517 | bool coh901318_filter_id(struct dma_chan *chan, void *chan_id) |
| 518 | { |
| 519 | unsigned int ch_nr = (unsigned int) chan_id; |
| 520 | |
| 521 | if (ch_nr == to_coh901318_chan(chan)->id) |
| 522 | return true; |
| 523 | |
| 524 | return false; |
| 525 | } |
| 526 | EXPORT_SYMBOL(coh901318_filter_id); |
| 527 | |
| 528 | /* |
| 529 | * DMA channel allocation |
| 530 | */ |
| 531 | static int coh901318_config(struct coh901318_chan *cohc, |
| 532 | struct coh901318_params *param) |
| 533 | { |
| 534 | unsigned long flags; |
| 535 | const struct coh901318_params *p; |
| 536 | int channel = cohc->id; |
| 537 | void __iomem *virtbase = cohc->base->virtbase; |
| 538 | |
| 539 | spin_lock_irqsave(&cohc->lock, flags); |
| 540 | |
| 541 | if (param) |
| 542 | p = param; |
| 543 | else |
| 544 | p = &cohc->base->platform->chan_conf[channel].param; |
| 545 | |
| 546 | /* Clear any pending BE or TC interrupt */ |
| 547 | if (channel < 32) { |
| 548 | writel(1 << channel, virtbase + COH901318_BE_INT_CLEAR1); |
| 549 | writel(1 << channel, virtbase + COH901318_TC_INT_CLEAR1); |
| 550 | } else { |
| 551 | writel(1 << (channel - 32), virtbase + |
| 552 | COH901318_BE_INT_CLEAR2); |
| 553 | writel(1 << (channel - 32), virtbase + |
| 554 | COH901318_TC_INT_CLEAR2); |
| 555 | } |
| 556 | |
| 557 | coh901318_set_conf(cohc, p->config); |
| 558 | coh901318_set_ctrl(cohc, p->ctrl_lli_last); |
| 559 | |
| 560 | spin_unlock_irqrestore(&cohc->lock, flags); |
| 561 | |
| 562 | return 0; |
| 563 | } |
| 564 | |
| 565 | /* must lock when calling this function |
| 566 | * start queued jobs, if any |
| 567 | * TODO: start all queued jobs in one go |
| 568 | * |
| 569 | * Returns descriptor if queued job is started otherwise NULL. |
| 570 | * If the queue is empty NULL is returned. |
| 571 | */ |
| 572 | static struct coh901318_desc *coh901318_queue_start(struct coh901318_chan *cohc) |
| 573 | { |
| 574 | struct coh901318_desc *cohd_que; |
| 575 | |
| 576 | /* start queued jobs, if any |
| 577 | * TODO: transmit all queued jobs in one go |
| 578 | */ |
| 579 | cohd_que = coh901318_first_queued(cohc); |
| 580 | |
| 581 | if (cohd_que != NULL) { |
| 582 | /* Remove from queue */ |
| 583 | coh901318_desc_remove(cohd_que); |
| 584 | /* initiate DMA job */ |
| 585 | cohc->busy = 1; |
| 586 | |
| 587 | coh901318_desc_submit(cohc, cohd_que); |
| 588 | |
| 589 | coh901318_prep_linked_list(cohc, cohd_que->data); |
| 590 | |
| 591 | /* start dma job */ |
| 592 | coh901318_start(cohc); |
| 593 | |
| 594 | } |
| 595 | |
| 596 | return cohd_que; |
| 597 | } |
| 598 | |
Linus Walleij | 848ad12 | 2010-03-02 14:17:15 -0700 | [diff] [blame] | 599 | /* |
| 600 | * This tasklet is called from the interrupt handler to |
| 601 | * handle each descriptor (DMA job) that is sent to a channel. |
| 602 | */ |
Linus Walleij | 61f135b | 2009-11-19 19:49:17 +0100 | [diff] [blame] | 603 | static void dma_tasklet(unsigned long data) |
| 604 | { |
| 605 | struct coh901318_chan *cohc = (struct coh901318_chan *) data; |
| 606 | struct coh901318_desc *cohd_fin; |
| 607 | unsigned long flags; |
| 608 | dma_async_tx_callback callback; |
| 609 | void *callback_param; |
| 610 | |
Linus Walleij | 848ad12 | 2010-03-02 14:17:15 -0700 | [diff] [blame] | 611 | dev_vdbg(COHC_2_DEV(cohc), "[%s] chan_id %d" |
| 612 | " nbr_active_done %ld\n", __func__, |
| 613 | cohc->id, cohc->nbr_active_done); |
| 614 | |
Linus Walleij | 61f135b | 2009-11-19 19:49:17 +0100 | [diff] [blame] | 615 | spin_lock_irqsave(&cohc->lock, flags); |
| 616 | |
Linus Walleij | 848ad12 | 2010-03-02 14:17:15 -0700 | [diff] [blame] | 617 | /* get first active descriptor entry from list */ |
Linus Walleij | 61f135b | 2009-11-19 19:49:17 +0100 | [diff] [blame] | 618 | cohd_fin = coh901318_first_active_get(cohc); |
| 619 | |
| 620 | BUG_ON(cohd_fin->pending_irqs == 0); |
| 621 | |
| 622 | if (cohd_fin == NULL) |
| 623 | goto err; |
| 624 | |
| 625 | cohd_fin->pending_irqs--; |
| 626 | cohc->completed = cohd_fin->desc.cookie; |
| 627 | |
Linus Walleij | 61f135b | 2009-11-19 19:49:17 +0100 | [diff] [blame] | 628 | if (cohc->nbr_active_done == 0) |
| 629 | return; |
| 630 | |
| 631 | if (!cohd_fin->pending_irqs) { |
| 632 | /* release the lli allocation*/ |
| 633 | coh901318_lli_free(&cohc->base->pool, &cohd_fin->data); |
| 634 | } |
| 635 | |
| 636 | dev_vdbg(COHC_2_DEV(cohc), "[%s] chan_id %d pending_irqs %d" |
| 637 | " nbr_active_done %ld\n", __func__, |
| 638 | cohc->id, cohc->pending_irqs, cohc->nbr_active_done); |
| 639 | |
| 640 | /* callback to client */ |
| 641 | callback = cohd_fin->desc.callback; |
| 642 | callback_param = cohd_fin->desc.callback_param; |
| 643 | |
| 644 | if (!cohd_fin->pending_irqs) { |
| 645 | coh901318_desc_remove(cohd_fin); |
| 646 | |
| 647 | /* return desc to free-list */ |
| 648 | coh901318_desc_free(cohc, cohd_fin); |
| 649 | } |
| 650 | |
Linus Walleij | 848ad12 | 2010-03-02 14:17:15 -0700 | [diff] [blame] | 651 | /* |
| 652 | * If another interrupt fired while the tasklet was scheduling, |
| 653 | * we don't get called twice, so we have this number of active |
| 654 | * counter that keep track of the number of IRQs expected to |
| 655 | * be handled for this channel. If there happen to be more than |
| 656 | * one IRQ to be ack:ed, we simply schedule this tasklet again. |
| 657 | */ |
Linus Walleij | 61f135b | 2009-11-19 19:49:17 +0100 | [diff] [blame] | 658 | if (cohc->nbr_active_done) |
| 659 | cohc->nbr_active_done--; |
| 660 | |
| 661 | if (cohc->nbr_active_done) { |
Linus Walleij | 848ad12 | 2010-03-02 14:17:15 -0700 | [diff] [blame] | 662 | dev_dbg(COHC_2_DEV(cohc), "scheduling tasklet again, new IRQs " |
| 663 | "came in while we were scheduling this tasklet\n"); |
Linus Walleij | 61f135b | 2009-11-19 19:49:17 +0100 | [diff] [blame] | 664 | if (cohc_chan_conf(cohc)->priority_high) |
| 665 | tasklet_hi_schedule(&cohc->tasklet); |
| 666 | else |
| 667 | tasklet_schedule(&cohc->tasklet); |
| 668 | } |
| 669 | spin_unlock_irqrestore(&cohc->lock, flags); |
| 670 | |
| 671 | if (callback) |
| 672 | callback(callback_param); |
| 673 | |
| 674 | return; |
| 675 | |
| 676 | err: |
| 677 | spin_unlock_irqrestore(&cohc->lock, flags); |
| 678 | dev_err(COHC_2_DEV(cohc), "[%s] No active dma desc\n", __func__); |
| 679 | } |
| 680 | |
| 681 | |
| 682 | /* called from interrupt context */ |
| 683 | static void dma_tc_handle(struct coh901318_chan *cohc) |
| 684 | { |
| 685 | BUG_ON(!cohc->allocated && (list_empty(&cohc->active) || |
| 686 | list_empty(&cohc->queue))); |
| 687 | |
| 688 | if (!cohc->allocated) |
| 689 | return; |
| 690 | |
| 691 | BUG_ON(cohc->pending_irqs == 0); |
| 692 | |
| 693 | cohc->pending_irqs--; |
| 694 | cohc->nbr_active_done++; |
| 695 | |
| 696 | if (cohc->pending_irqs == 0 && coh901318_queue_start(cohc) == NULL) |
| 697 | cohc->busy = 0; |
| 698 | |
| 699 | BUG_ON(list_empty(&cohc->active)); |
| 700 | |
| 701 | if (cohc_chan_conf(cohc)->priority_high) |
| 702 | tasklet_hi_schedule(&cohc->tasklet); |
| 703 | else |
| 704 | tasklet_schedule(&cohc->tasklet); |
| 705 | } |
| 706 | |
| 707 | |
| 708 | static irqreturn_t dma_irq_handler(int irq, void *dev_id) |
| 709 | { |
| 710 | u32 status1; |
| 711 | u32 status2; |
| 712 | int i; |
| 713 | int ch; |
| 714 | struct coh901318_base *base = dev_id; |
| 715 | struct coh901318_chan *cohc; |
| 716 | void __iomem *virtbase = base->virtbase; |
| 717 | |
| 718 | status1 = readl(virtbase + COH901318_INT_STATUS1); |
| 719 | status2 = readl(virtbase + COH901318_INT_STATUS2); |
| 720 | |
| 721 | if (unlikely(status1 == 0 && status2 == 0)) { |
| 722 | dev_warn(base->dev, "spurious DMA IRQ from no channel!\n"); |
| 723 | return IRQ_HANDLED; |
| 724 | } |
| 725 | |
| 726 | /* TODO: consider handle IRQ in tasklet here to |
| 727 | * minimize interrupt latency */ |
| 728 | |
| 729 | /* Check the first 32 DMA channels for IRQ */ |
| 730 | while (status1) { |
| 731 | /* Find first bit set, return as a number. */ |
| 732 | i = ffs(status1) - 1; |
| 733 | ch = i; |
| 734 | |
| 735 | cohc = &base->chans[ch]; |
| 736 | spin_lock(&cohc->lock); |
| 737 | |
| 738 | /* Mask off this bit */ |
| 739 | status1 &= ~(1 << i); |
| 740 | /* Check the individual channel bits */ |
| 741 | if (test_bit(i, virtbase + COH901318_BE_INT_STATUS1)) { |
| 742 | dev_crit(COHC_2_DEV(cohc), |
| 743 | "DMA bus error on channel %d!\n", ch); |
| 744 | BUG_ON(1); |
| 745 | /* Clear BE interrupt */ |
| 746 | __set_bit(i, virtbase + COH901318_BE_INT_CLEAR1); |
| 747 | } else { |
| 748 | /* Caused by TC, really? */ |
| 749 | if (unlikely(!test_bit(i, virtbase + |
| 750 | COH901318_TC_INT_STATUS1))) { |
| 751 | dev_warn(COHC_2_DEV(cohc), |
| 752 | "ignoring interrupt not caused by terminal count on channel %d\n", ch); |
| 753 | /* Clear TC interrupt */ |
| 754 | BUG_ON(1); |
| 755 | __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1); |
| 756 | } else { |
| 757 | /* Enable powersave if transfer has finished */ |
| 758 | if (!(readl(virtbase + COH901318_CX_STAT + |
| 759 | COH901318_CX_STAT_SPACING*ch) & |
| 760 | COH901318_CX_STAT_ENABLED)) { |
| 761 | enable_powersave(cohc); |
| 762 | } |
| 763 | |
| 764 | /* Must clear TC interrupt before calling |
| 765 | * dma_tc_handle |
| 766 | * in case tc_handle initate a new dma job |
| 767 | */ |
| 768 | __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1); |
| 769 | |
| 770 | dma_tc_handle(cohc); |
| 771 | } |
| 772 | } |
| 773 | spin_unlock(&cohc->lock); |
| 774 | } |
| 775 | |
| 776 | /* Check the remaining 32 DMA channels for IRQ */ |
| 777 | while (status2) { |
| 778 | /* Find first bit set, return as a number. */ |
| 779 | i = ffs(status2) - 1; |
| 780 | ch = i + 32; |
| 781 | cohc = &base->chans[ch]; |
| 782 | spin_lock(&cohc->lock); |
| 783 | |
| 784 | /* Mask off this bit */ |
| 785 | status2 &= ~(1 << i); |
| 786 | /* Check the individual channel bits */ |
| 787 | if (test_bit(i, virtbase + COH901318_BE_INT_STATUS2)) { |
| 788 | dev_crit(COHC_2_DEV(cohc), |
| 789 | "DMA bus error on channel %d!\n", ch); |
| 790 | /* Clear BE interrupt */ |
| 791 | BUG_ON(1); |
| 792 | __set_bit(i, virtbase + COH901318_BE_INT_CLEAR2); |
| 793 | } else { |
| 794 | /* Caused by TC, really? */ |
| 795 | if (unlikely(!test_bit(i, virtbase + |
| 796 | COH901318_TC_INT_STATUS2))) { |
| 797 | dev_warn(COHC_2_DEV(cohc), |
| 798 | "ignoring interrupt not caused by terminal count on channel %d\n", ch); |
| 799 | /* Clear TC interrupt */ |
| 800 | __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2); |
| 801 | BUG_ON(1); |
| 802 | } else { |
| 803 | /* Enable powersave if transfer has finished */ |
| 804 | if (!(readl(virtbase + COH901318_CX_STAT + |
| 805 | COH901318_CX_STAT_SPACING*ch) & |
| 806 | COH901318_CX_STAT_ENABLED)) { |
| 807 | enable_powersave(cohc); |
| 808 | } |
| 809 | /* Must clear TC interrupt before calling |
| 810 | * dma_tc_handle |
| 811 | * in case tc_handle initate a new dma job |
| 812 | */ |
| 813 | __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2); |
| 814 | |
| 815 | dma_tc_handle(cohc); |
| 816 | } |
| 817 | } |
| 818 | spin_unlock(&cohc->lock); |
| 819 | } |
| 820 | |
| 821 | return IRQ_HANDLED; |
| 822 | } |
| 823 | |
| 824 | static int coh901318_alloc_chan_resources(struct dma_chan *chan) |
| 825 | { |
| 826 | struct coh901318_chan *cohc = to_coh901318_chan(chan); |
| 827 | |
| 828 | dev_vdbg(COHC_2_DEV(cohc), "[%s] DMA channel %d\n", |
| 829 | __func__, cohc->id); |
| 830 | |
| 831 | if (chan->client_count > 1) |
| 832 | return -EBUSY; |
| 833 | |
| 834 | coh901318_config(cohc, NULL); |
| 835 | |
| 836 | cohc->allocated = 1; |
| 837 | cohc->completed = chan->cookie = 1; |
| 838 | |
| 839 | return 1; |
| 840 | } |
| 841 | |
| 842 | static void |
| 843 | coh901318_free_chan_resources(struct dma_chan *chan) |
| 844 | { |
| 845 | struct coh901318_chan *cohc = to_coh901318_chan(chan); |
| 846 | int channel = cohc->id; |
| 847 | unsigned long flags; |
| 848 | |
| 849 | spin_lock_irqsave(&cohc->lock, flags); |
| 850 | |
| 851 | /* Disable HW */ |
| 852 | writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CFG + |
| 853 | COH901318_CX_CFG_SPACING*channel); |
| 854 | writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CTRL + |
| 855 | COH901318_CX_CTRL_SPACING*channel); |
| 856 | |
| 857 | cohc->allocated = 0; |
| 858 | |
| 859 | spin_unlock_irqrestore(&cohc->lock, flags); |
| 860 | |
| 861 | chan->device->device_terminate_all(chan); |
| 862 | } |
| 863 | |
| 864 | |
| 865 | static dma_cookie_t |
| 866 | coh901318_tx_submit(struct dma_async_tx_descriptor *tx) |
| 867 | { |
| 868 | struct coh901318_desc *cohd = container_of(tx, struct coh901318_desc, |
| 869 | desc); |
| 870 | struct coh901318_chan *cohc = to_coh901318_chan(tx->chan); |
| 871 | unsigned long flags; |
| 872 | |
| 873 | spin_lock_irqsave(&cohc->lock, flags); |
| 874 | |
| 875 | tx->cookie = coh901318_assign_cookie(cohc, cohd); |
| 876 | |
| 877 | coh901318_desc_queue(cohc, cohd); |
| 878 | |
| 879 | spin_unlock_irqrestore(&cohc->lock, flags); |
| 880 | |
| 881 | return tx->cookie; |
| 882 | } |
| 883 | |
| 884 | static struct dma_async_tx_descriptor * |
| 885 | coh901318_prep_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, |
| 886 | size_t size, unsigned long flags) |
| 887 | { |
| 888 | struct coh901318_lli *data; |
| 889 | struct coh901318_desc *cohd; |
| 890 | unsigned long flg; |
| 891 | struct coh901318_chan *cohc = to_coh901318_chan(chan); |
| 892 | int lli_len; |
| 893 | u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last; |
Linus Walleij | b87108a | 2010-03-02 14:17:20 -0700 | [diff] [blame^] | 894 | int ret; |
Linus Walleij | 61f135b | 2009-11-19 19:49:17 +0100 | [diff] [blame] | 895 | |
| 896 | spin_lock_irqsave(&cohc->lock, flg); |
| 897 | |
| 898 | dev_vdbg(COHC_2_DEV(cohc), |
| 899 | "[%s] channel %d src 0x%x dest 0x%x size %d\n", |
| 900 | __func__, cohc->id, src, dest, size); |
| 901 | |
| 902 | if (flags & DMA_PREP_INTERRUPT) |
| 903 | /* Trigger interrupt after last lli */ |
| 904 | ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE; |
| 905 | |
| 906 | lli_len = size >> MAX_DMA_PACKET_SIZE_SHIFT; |
| 907 | if ((lli_len << MAX_DMA_PACKET_SIZE_SHIFT) < size) |
| 908 | lli_len++; |
| 909 | |
| 910 | data = coh901318_lli_alloc(&cohc->base->pool, lli_len); |
| 911 | |
| 912 | if (data == NULL) |
| 913 | goto err; |
| 914 | |
Linus Walleij | b87108a | 2010-03-02 14:17:20 -0700 | [diff] [blame^] | 915 | ret = coh901318_lli_fill_memcpy( |
| 916 | &cohc->base->pool, data, src, size, dest, |
| 917 | cohc_chan_param(cohc)->ctrl_lli_chained, |
| 918 | ctrl_last); |
| 919 | if (ret) |
| 920 | goto err; |
Linus Walleij | 61f135b | 2009-11-19 19:49:17 +0100 | [diff] [blame] | 921 | |
| 922 | COH_DBG(coh901318_list_print(cohc, data)); |
| 923 | |
Linus Walleij | b87108a | 2010-03-02 14:17:20 -0700 | [diff] [blame^] | 924 | /* Pick a descriptor to handle this transfer */ |
| 925 | cohd = coh901318_desc_get(cohc); |
| 926 | cohd->data = data; |
| 927 | cohd->flags = flags; |
Linus Walleij | 61f135b | 2009-11-19 19:49:17 +0100 | [diff] [blame] | 928 | cohd->desc.tx_submit = coh901318_tx_submit; |
| 929 | |
| 930 | spin_unlock_irqrestore(&cohc->lock, flg); |
| 931 | |
| 932 | return &cohd->desc; |
| 933 | err: |
| 934 | spin_unlock_irqrestore(&cohc->lock, flg); |
| 935 | return NULL; |
| 936 | } |
| 937 | |
| 938 | static struct dma_async_tx_descriptor * |
| 939 | coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, |
| 940 | unsigned int sg_len, enum dma_data_direction direction, |
| 941 | unsigned long flags) |
| 942 | { |
| 943 | struct coh901318_chan *cohc = to_coh901318_chan(chan); |
| 944 | struct coh901318_lli *data; |
| 945 | struct coh901318_desc *cohd; |
| 946 | struct scatterlist *sg; |
| 947 | int len = 0; |
| 948 | int size; |
| 949 | int i; |
| 950 | u32 ctrl_chained = cohc_chan_param(cohc)->ctrl_lli_chained; |
| 951 | u32 ctrl = cohc_chan_param(cohc)->ctrl_lli; |
| 952 | u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last; |
| 953 | unsigned long flg; |
| 954 | |
| 955 | if (!sgl) |
| 956 | goto out; |
| 957 | if (sgl->length == 0) |
| 958 | goto out; |
| 959 | |
| 960 | spin_lock_irqsave(&cohc->lock, flg); |
| 961 | |
| 962 | dev_vdbg(COHC_2_DEV(cohc), "[%s] sg_len %d dir %d\n", |
| 963 | __func__, sg_len, direction); |
| 964 | |
| 965 | if (flags & DMA_PREP_INTERRUPT) |
| 966 | /* Trigger interrupt after last lli */ |
| 967 | ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE; |
| 968 | |
Linus Walleij | 61f135b | 2009-11-19 19:49:17 +0100 | [diff] [blame] | 969 | if (direction == DMA_TO_DEVICE) { |
| 970 | u32 tx_flags = COH901318_CX_CTRL_PRDD_SOURCE | |
| 971 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE; |
| 972 | |
| 973 | ctrl_chained |= tx_flags; |
| 974 | ctrl_last |= tx_flags; |
| 975 | ctrl |= tx_flags; |
| 976 | } else if (direction == DMA_FROM_DEVICE) { |
| 977 | u32 rx_flags = COH901318_CX_CTRL_PRDD_DEST | |
| 978 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE; |
| 979 | |
| 980 | ctrl_chained |= rx_flags; |
| 981 | ctrl_last |= rx_flags; |
| 982 | ctrl |= rx_flags; |
| 983 | } else |
| 984 | goto err_direction; |
| 985 | |
Linus Walleij | 61f135b | 2009-11-19 19:49:17 +0100 | [diff] [blame] | 986 | /* The dma only supports transmitting packages up to |
| 987 | * MAX_DMA_PACKET_SIZE. Calculate to total number of |
| 988 | * dma elemts required to send the entire sg list |
| 989 | */ |
| 990 | for_each_sg(sgl, sg, sg_len, i) { |
| 991 | unsigned int factor; |
| 992 | size = sg_dma_len(sg); |
| 993 | |
| 994 | if (size <= MAX_DMA_PACKET_SIZE) { |
| 995 | len++; |
| 996 | continue; |
| 997 | } |
| 998 | |
| 999 | factor = size >> MAX_DMA_PACKET_SIZE_SHIFT; |
| 1000 | if ((factor << MAX_DMA_PACKET_SIZE_SHIFT) < size) |
| 1001 | factor++; |
| 1002 | |
| 1003 | len += factor; |
| 1004 | } |
| 1005 | |
Linus Walleij | 848ad12 | 2010-03-02 14:17:15 -0700 | [diff] [blame] | 1006 | pr_debug("Allocate %d lli:s for this transfer\n", len); |
Linus Walleij | 61f135b | 2009-11-19 19:49:17 +0100 | [diff] [blame] | 1007 | data = coh901318_lli_alloc(&cohc->base->pool, len); |
| 1008 | |
| 1009 | if (data == NULL) |
| 1010 | goto err_dma_alloc; |
| 1011 | |
| 1012 | /* initiate allocated data list */ |
| 1013 | cohd->pending_irqs = |
| 1014 | coh901318_lli_fill_sg(&cohc->base->pool, data, sgl, sg_len, |
| 1015 | cohc_dev_addr(cohc), |
| 1016 | ctrl_chained, |
| 1017 | ctrl, |
| 1018 | ctrl_last, |
| 1019 | direction, COH901318_CX_CTRL_TC_IRQ_ENABLE); |
Linus Walleij | 61f135b | 2009-11-19 19:49:17 +0100 | [diff] [blame] | 1020 | |
| 1021 | COH_DBG(coh901318_list_print(cohc, data)); |
| 1022 | |
Linus Walleij | b87108a | 2010-03-02 14:17:20 -0700 | [diff] [blame^] | 1023 | /* Pick a descriptor to handle this transfer */ |
| 1024 | cohd = coh901318_desc_get(cohc); |
| 1025 | cohd->dir = direction; |
| 1026 | cohd->flags = flags; |
| 1027 | cohd->desc.tx_submit = coh901318_tx_submit; |
| 1028 | cohd->data = data; |
| 1029 | |
Linus Walleij | 61f135b | 2009-11-19 19:49:17 +0100 | [diff] [blame] | 1030 | spin_unlock_irqrestore(&cohc->lock, flg); |
| 1031 | |
| 1032 | return &cohd->desc; |
| 1033 | err_dma_alloc: |
| 1034 | err_direction: |
Linus Walleij | 61f135b | 2009-11-19 19:49:17 +0100 | [diff] [blame] | 1035 | spin_unlock_irqrestore(&cohc->lock, flg); |
| 1036 | out: |
| 1037 | return NULL; |
| 1038 | } |
| 1039 | |
| 1040 | static enum dma_status |
| 1041 | coh901318_is_tx_complete(struct dma_chan *chan, |
| 1042 | dma_cookie_t cookie, dma_cookie_t *done, |
| 1043 | dma_cookie_t *used) |
| 1044 | { |
| 1045 | struct coh901318_chan *cohc = to_coh901318_chan(chan); |
| 1046 | dma_cookie_t last_used; |
| 1047 | dma_cookie_t last_complete; |
| 1048 | int ret; |
| 1049 | |
| 1050 | last_complete = cohc->completed; |
| 1051 | last_used = chan->cookie; |
| 1052 | |
| 1053 | ret = dma_async_is_complete(cookie, last_complete, last_used); |
| 1054 | |
| 1055 | if (done) |
| 1056 | *done = last_complete; |
| 1057 | if (used) |
| 1058 | *used = last_used; |
| 1059 | |
| 1060 | return ret; |
| 1061 | } |
| 1062 | |
| 1063 | static void |
| 1064 | coh901318_issue_pending(struct dma_chan *chan) |
| 1065 | { |
| 1066 | struct coh901318_chan *cohc = to_coh901318_chan(chan); |
| 1067 | unsigned long flags; |
| 1068 | |
| 1069 | spin_lock_irqsave(&cohc->lock, flags); |
| 1070 | |
| 1071 | /* Busy means that pending jobs are already being processed */ |
| 1072 | if (!cohc->busy) |
| 1073 | coh901318_queue_start(cohc); |
| 1074 | |
| 1075 | spin_unlock_irqrestore(&cohc->lock, flags); |
| 1076 | } |
| 1077 | |
| 1078 | static void |
| 1079 | coh901318_terminate_all(struct dma_chan *chan) |
| 1080 | { |
| 1081 | unsigned long flags; |
| 1082 | struct coh901318_chan *cohc = to_coh901318_chan(chan); |
| 1083 | struct coh901318_desc *cohd; |
| 1084 | void __iomem *virtbase = cohc->base->virtbase; |
| 1085 | |
| 1086 | coh901318_stop(chan); |
| 1087 | |
| 1088 | spin_lock_irqsave(&cohc->lock, flags); |
| 1089 | |
| 1090 | /* Clear any pending BE or TC interrupt */ |
| 1091 | if (cohc->id < 32) { |
| 1092 | writel(1 << cohc->id, virtbase + COH901318_BE_INT_CLEAR1); |
| 1093 | writel(1 << cohc->id, virtbase + COH901318_TC_INT_CLEAR1); |
| 1094 | } else { |
| 1095 | writel(1 << (cohc->id - 32), virtbase + |
| 1096 | COH901318_BE_INT_CLEAR2); |
| 1097 | writel(1 << (cohc->id - 32), virtbase + |
| 1098 | COH901318_TC_INT_CLEAR2); |
| 1099 | } |
| 1100 | |
| 1101 | enable_powersave(cohc); |
| 1102 | |
| 1103 | while ((cohd = coh901318_first_active_get(cohc))) { |
| 1104 | /* release the lli allocation*/ |
| 1105 | coh901318_lli_free(&cohc->base->pool, &cohd->data); |
| 1106 | |
Linus Walleij | 61f135b | 2009-11-19 19:49:17 +0100 | [diff] [blame] | 1107 | /* return desc to free-list */ |
Linus Walleij | 848ad12 | 2010-03-02 14:17:15 -0700 | [diff] [blame] | 1108 | coh901318_desc_remove(cohd); |
Linus Walleij | 61f135b | 2009-11-19 19:49:17 +0100 | [diff] [blame] | 1109 | coh901318_desc_free(cohc, cohd); |
| 1110 | } |
| 1111 | |
| 1112 | while ((cohd = coh901318_first_queued(cohc))) { |
| 1113 | /* release the lli allocation*/ |
| 1114 | coh901318_lli_free(&cohc->base->pool, &cohd->data); |
| 1115 | |
Linus Walleij | 61f135b | 2009-11-19 19:49:17 +0100 | [diff] [blame] | 1116 | /* return desc to free-list */ |
Linus Walleij | 848ad12 | 2010-03-02 14:17:15 -0700 | [diff] [blame] | 1117 | coh901318_desc_remove(cohd); |
Linus Walleij | 61f135b | 2009-11-19 19:49:17 +0100 | [diff] [blame] | 1118 | coh901318_desc_free(cohc, cohd); |
| 1119 | } |
| 1120 | |
| 1121 | |
| 1122 | cohc->nbr_active_done = 0; |
| 1123 | cohc->busy = 0; |
| 1124 | cohc->pending_irqs = 0; |
| 1125 | |
| 1126 | spin_unlock_irqrestore(&cohc->lock, flags); |
| 1127 | } |
| 1128 | void coh901318_base_init(struct dma_device *dma, const int *pick_chans, |
| 1129 | struct coh901318_base *base) |
| 1130 | { |
| 1131 | int chans_i; |
| 1132 | int i = 0; |
| 1133 | struct coh901318_chan *cohc; |
| 1134 | |
| 1135 | INIT_LIST_HEAD(&dma->channels); |
| 1136 | |
| 1137 | for (chans_i = 0; pick_chans[chans_i] != -1; chans_i += 2) { |
| 1138 | for (i = pick_chans[chans_i]; i <= pick_chans[chans_i+1]; i++) { |
| 1139 | cohc = &base->chans[i]; |
| 1140 | |
| 1141 | cohc->base = base; |
| 1142 | cohc->chan.device = dma; |
| 1143 | cohc->id = i; |
| 1144 | |
| 1145 | /* TODO: do we really need this lock if only one |
| 1146 | * client is connected to each channel? |
| 1147 | */ |
| 1148 | |
| 1149 | spin_lock_init(&cohc->lock); |
| 1150 | |
| 1151 | cohc->pending_irqs = 0; |
| 1152 | cohc->nbr_active_done = 0; |
| 1153 | cohc->busy = 0; |
| 1154 | INIT_LIST_HEAD(&cohc->free); |
| 1155 | INIT_LIST_HEAD(&cohc->active); |
| 1156 | INIT_LIST_HEAD(&cohc->queue); |
| 1157 | |
| 1158 | tasklet_init(&cohc->tasklet, dma_tasklet, |
| 1159 | (unsigned long) cohc); |
| 1160 | |
| 1161 | list_add_tail(&cohc->chan.device_node, |
| 1162 | &dma->channels); |
| 1163 | } |
| 1164 | } |
| 1165 | } |
| 1166 | |
| 1167 | static int __init coh901318_probe(struct platform_device *pdev) |
| 1168 | { |
| 1169 | int err = 0; |
| 1170 | struct coh901318_platform *pdata; |
| 1171 | struct coh901318_base *base; |
| 1172 | int irq; |
| 1173 | struct resource *io; |
| 1174 | |
| 1175 | io = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1176 | if (!io) |
| 1177 | goto err_get_resource; |
| 1178 | |
| 1179 | /* Map DMA controller registers to virtual memory */ |
| 1180 | if (request_mem_region(io->start, |
| 1181 | resource_size(io), |
| 1182 | pdev->dev.driver->name) == NULL) { |
| 1183 | err = -EBUSY; |
| 1184 | goto err_request_mem; |
| 1185 | } |
| 1186 | |
| 1187 | pdata = pdev->dev.platform_data; |
| 1188 | if (!pdata) |
| 1189 | goto err_no_platformdata; |
| 1190 | |
| 1191 | base = kmalloc(ALIGN(sizeof(struct coh901318_base), 4) + |
| 1192 | pdata->max_channels * |
| 1193 | sizeof(struct coh901318_chan), |
| 1194 | GFP_KERNEL); |
| 1195 | if (!base) |
| 1196 | goto err_alloc_coh_dma_channels; |
| 1197 | |
| 1198 | base->chans = ((void *)base) + ALIGN(sizeof(struct coh901318_base), 4); |
| 1199 | |
| 1200 | base->virtbase = ioremap(io->start, resource_size(io)); |
| 1201 | if (!base->virtbase) { |
| 1202 | err = -ENOMEM; |
| 1203 | goto err_no_ioremap; |
| 1204 | } |
| 1205 | |
| 1206 | base->dev = &pdev->dev; |
| 1207 | base->platform = pdata; |
| 1208 | spin_lock_init(&base->pm.lock); |
| 1209 | base->pm.started_channels = 0; |
| 1210 | |
| 1211 | COH901318_DEBUGFS_ASSIGN(debugfs_dma_base, base); |
| 1212 | |
| 1213 | platform_set_drvdata(pdev, base); |
| 1214 | |
| 1215 | irq = platform_get_irq(pdev, 0); |
| 1216 | if (irq < 0) |
| 1217 | goto err_no_irq; |
| 1218 | |
| 1219 | err = request_irq(irq, dma_irq_handler, IRQF_DISABLED, |
| 1220 | "coh901318", base); |
| 1221 | if (err) { |
| 1222 | dev_crit(&pdev->dev, |
| 1223 | "Cannot allocate IRQ for DMA controller!\n"); |
| 1224 | goto err_request_irq; |
| 1225 | } |
| 1226 | |
| 1227 | err = coh901318_pool_create(&base->pool, &pdev->dev, |
| 1228 | sizeof(struct coh901318_lli), |
| 1229 | 32); |
| 1230 | if (err) |
| 1231 | goto err_pool_create; |
| 1232 | |
| 1233 | /* init channels for device transfers */ |
| 1234 | coh901318_base_init(&base->dma_slave, base->platform->chans_slave, |
| 1235 | base); |
| 1236 | |
| 1237 | dma_cap_zero(base->dma_slave.cap_mask); |
| 1238 | dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask); |
| 1239 | |
| 1240 | base->dma_slave.device_alloc_chan_resources = coh901318_alloc_chan_resources; |
| 1241 | base->dma_slave.device_free_chan_resources = coh901318_free_chan_resources; |
| 1242 | base->dma_slave.device_prep_slave_sg = coh901318_prep_slave_sg; |
| 1243 | base->dma_slave.device_is_tx_complete = coh901318_is_tx_complete; |
| 1244 | base->dma_slave.device_issue_pending = coh901318_issue_pending; |
| 1245 | base->dma_slave.device_terminate_all = coh901318_terminate_all; |
| 1246 | base->dma_slave.dev = &pdev->dev; |
| 1247 | |
| 1248 | err = dma_async_device_register(&base->dma_slave); |
| 1249 | |
| 1250 | if (err) |
| 1251 | goto err_register_slave; |
| 1252 | |
| 1253 | /* init channels for memcpy */ |
| 1254 | coh901318_base_init(&base->dma_memcpy, base->platform->chans_memcpy, |
| 1255 | base); |
| 1256 | |
| 1257 | dma_cap_zero(base->dma_memcpy.cap_mask); |
| 1258 | dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask); |
| 1259 | |
| 1260 | base->dma_memcpy.device_alloc_chan_resources = coh901318_alloc_chan_resources; |
| 1261 | base->dma_memcpy.device_free_chan_resources = coh901318_free_chan_resources; |
| 1262 | base->dma_memcpy.device_prep_dma_memcpy = coh901318_prep_memcpy; |
| 1263 | base->dma_memcpy.device_is_tx_complete = coh901318_is_tx_complete; |
| 1264 | base->dma_memcpy.device_issue_pending = coh901318_issue_pending; |
| 1265 | base->dma_memcpy.device_terminate_all = coh901318_terminate_all; |
| 1266 | base->dma_memcpy.dev = &pdev->dev; |
| 1267 | err = dma_async_device_register(&base->dma_memcpy); |
| 1268 | |
| 1269 | if (err) |
| 1270 | goto err_register_memcpy; |
| 1271 | |
Linus Walleij | 848ad12 | 2010-03-02 14:17:15 -0700 | [diff] [blame] | 1272 | dev_info(&pdev->dev, "Initialized COH901318 DMA on virtual base 0x%08x\n", |
Linus Walleij | 61f135b | 2009-11-19 19:49:17 +0100 | [diff] [blame] | 1273 | (u32) base->virtbase); |
| 1274 | |
| 1275 | return err; |
| 1276 | |
| 1277 | err_register_memcpy: |
| 1278 | dma_async_device_unregister(&base->dma_slave); |
| 1279 | err_register_slave: |
| 1280 | coh901318_pool_destroy(&base->pool); |
| 1281 | err_pool_create: |
| 1282 | free_irq(platform_get_irq(pdev, 0), base); |
| 1283 | err_request_irq: |
| 1284 | err_no_irq: |
| 1285 | iounmap(base->virtbase); |
| 1286 | err_no_ioremap: |
| 1287 | kfree(base); |
| 1288 | err_alloc_coh_dma_channels: |
| 1289 | err_no_platformdata: |
| 1290 | release_mem_region(pdev->resource->start, |
| 1291 | resource_size(pdev->resource)); |
| 1292 | err_request_mem: |
| 1293 | err_get_resource: |
| 1294 | return err; |
| 1295 | } |
| 1296 | |
| 1297 | static int __exit coh901318_remove(struct platform_device *pdev) |
| 1298 | { |
| 1299 | struct coh901318_base *base = platform_get_drvdata(pdev); |
| 1300 | |
| 1301 | dma_async_device_unregister(&base->dma_memcpy); |
| 1302 | dma_async_device_unregister(&base->dma_slave); |
| 1303 | coh901318_pool_destroy(&base->pool); |
| 1304 | free_irq(platform_get_irq(pdev, 0), base); |
Linus Walleij | 61f135b | 2009-11-19 19:49:17 +0100 | [diff] [blame] | 1305 | iounmap(base->virtbase); |
Julia Lawall | 0794ec8 | 2009-12-22 21:30:59 +0100 | [diff] [blame] | 1306 | kfree(base); |
Linus Walleij | 61f135b | 2009-11-19 19:49:17 +0100 | [diff] [blame] | 1307 | release_mem_region(pdev->resource->start, |
| 1308 | resource_size(pdev->resource)); |
| 1309 | return 0; |
| 1310 | } |
| 1311 | |
| 1312 | |
| 1313 | static struct platform_driver coh901318_driver = { |
| 1314 | .remove = __exit_p(coh901318_remove), |
| 1315 | .driver = { |
| 1316 | .name = "coh901318", |
| 1317 | }, |
| 1318 | }; |
| 1319 | |
| 1320 | int __init coh901318_init(void) |
| 1321 | { |
| 1322 | return platform_driver_probe(&coh901318_driver, coh901318_probe); |
| 1323 | } |
| 1324 | subsys_initcall(coh901318_init); |
| 1325 | |
| 1326 | void __exit coh901318_exit(void) |
| 1327 | { |
| 1328 | platform_driver_unregister(&coh901318_driver); |
| 1329 | } |
| 1330 | module_exit(coh901318_exit); |
| 1331 | |
| 1332 | MODULE_LICENSE("GPL"); |
| 1333 | MODULE_AUTHOR("Per Friden"); |