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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/****************************************************************************/
2
3/*
4 * m5249sim.h -- ColdFire 5249 System Integration Module support.
5 *
6 * (C) Copyright 2002, Greg Ungerer (gerg@snapgear.com)
7 */
8
9/****************************************************************************/
10#ifndef m5249sim_h
11#define m5249sim_h
12/****************************************************************************/
13
Greg Ungerer733f31b2010-11-02 17:40:37 +100014#define CPU_NAME "COLDFIRE(m5249)"
15#define CPU_INSTR_PER_JIFFY 3
Greg Ungerer7fc82b62010-11-02 17:13:27 +100016
Greg Ungerera12cf0a2010-11-09 10:12:29 +100017#include <asm/m52xxacr.h>
18
Linus Torvalds1da177e2005-04-16 15:20:36 -070019/*
Greg Ungererf2ba7102011-03-05 21:43:50 +100020 * The 5249 has a second MBAR region, define its address.
21 */
22#define MCF_MBAR2 0x80000000
23
24/*
Linus Torvalds1da177e2005-04-16 15:20:36 -070025 * Define the 5249 SIM register set addresses.
26 */
27#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */
28#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/
29#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */
30#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */
31#define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */
32#define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */
33#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/
34#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */
35#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */
36#define MCFSIM_AVR 0x4b /* Autovector Ctrl reg (r/w) */
37#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */
38#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */
39#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */
40#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */
41#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */
42#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */
43#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */
44#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */
45#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */
46#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */
47#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */
48#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */
49
50#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */
51#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */
52#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */
53#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */
54#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */
55#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */
Joe Perchesab690d92008-02-03 17:38:04 +020056#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */
Linus Torvalds1da177e2005-04-16 15:20:36 -070057#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */
58#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */
Joe Perchesab690d92008-02-03 17:38:04 +020059#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */
Linus Torvalds1da177e2005-04-16 15:20:36 -070060#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */
61#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
62
63#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */
64#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */
65#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */
66#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */
67#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */
68
Greg Ungerer57015422010-11-03 12:50:30 +100069/*
70 * UART module.
71 */
72#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
73#define MCFUART_BASE2 0x200 /* Base address of UART2 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070074
75/*
Greg Ungererbabc08b2011-03-06 00:54:36 +100076 * DMA unit base addresses.
77 */
78#define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */
79#define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */
80#define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */
81#define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */
82
83/*
Linus Torvalds1da177e2005-04-16 15:20:36 -070084 * Some symbol defines for the above...
85 */
86#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
87#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
88#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */
89#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */
90#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
91#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */
92#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */
93#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
94#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
Steven King91d60412010-01-22 12:43:03 -080095#define MCFSIM_QSPIICR MCFSIM_ICR10 /* QSPI ICR */
Linus Torvalds1da177e2005-04-16 15:20:36 -070096
97/*
Greg Ungerer04b75b12009-05-19 14:52:40 +100098 * Define system peripheral IRQ usage.
99 */
Steven King91d60412010-01-22 12:43:03 -0800100#define MCF_IRQ_QSPI 28 /* QSPI, Level 4 */
Greg Ungerer04b75b12009-05-19 14:52:40 +1000101#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
102#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
103
104/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700105 * General purpose IO registers (in MBAR2).
106 */
sfking@fdwdc.com9e8ded12009-06-19 18:11:05 -0700107#define MCFSIM2_GPIOREAD (MCF_MBAR2 + 0x000) /* GPIO read values */
108#define MCFSIM2_GPIOWRITE (MCF_MBAR2 + 0x004) /* GPIO write values */
109#define MCFSIM2_GPIOENABLE (MCF_MBAR2 + 0x008) /* GPIO enabled */
110#define MCFSIM2_GPIOFUNC (MCF_MBAR2 + 0x00C) /* GPIO function */
111#define MCFSIM2_GPIO1READ (MCF_MBAR2 + 0x0B0) /* GPIO1 read values */
112#define MCFSIM2_GPIO1WRITE (MCF_MBAR2 + 0x0B4) /* GPIO1 write values */
113#define MCFSIM2_GPIO1ENABLE (MCF_MBAR2 + 0x0B8) /* GPIO1 enabled */
114#define MCFSIM2_GPIO1FUNC (MCF_MBAR2 + 0x0BC) /* GPIO1 function */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700115
116#define MCFSIM2_GPIOINTSTAT 0xc0 /* GPIO interrupt status */
117#define MCFSIM2_GPIOINTCLEAR 0xc0 /* GPIO interrupt clear */
118#define MCFSIM2_GPIOINTENABLE 0xc4 /* GPIO interrupt enable */
119
120#define MCFSIM2_INTLEVEL1 0x140 /* Interrupt level reg 1 */
121#define MCFSIM2_INTLEVEL2 0x144 /* Interrupt level reg 2 */
122#define MCFSIM2_INTLEVEL3 0x148 /* Interrupt level reg 3 */
123#define MCFSIM2_INTLEVEL4 0x14c /* Interrupt level reg 4 */
124#define MCFSIM2_INTLEVEL5 0x150 /* Interrupt level reg 5 */
125#define MCFSIM2_INTLEVEL6 0x154 /* Interrupt level reg 6 */
126#define MCFSIM2_INTLEVEL7 0x158 /* Interrupt level reg 7 */
127#define MCFSIM2_INTLEVEL8 0x15c /* Interrupt level reg 8 */
128
129#define MCFSIM2_DMAROUTE 0x188 /* DMA routing */
130
131#define MCFSIM2_IDECONFIG1 0x18c /* IDEconfig1 */
132#define MCFSIM2_IDECONFIG2 0x190 /* IDEconfig2 */
133
sfking@fdwdc.com9e8ded12009-06-19 18:11:05 -0700134/*
Greg Ungererda3601a2009-05-22 14:16:39 +1000135 * Define the base interrupt for the second interrupt controller.
136 * We set it to 128, out of the way of the base interrupts, and plenty
137 * of room for its 64 interrupts.
138 */
139#define MCFINTC2_VECBASE 128
140
141#define MCFINTC2_GPIOIRQ0 (MCFINTC2_VECBASE + 32)
142#define MCFINTC2_GPIOIRQ1 (MCFINTC2_VECBASE + 33)
143#define MCFINTC2_GPIOIRQ2 (MCFINTC2_VECBASE + 34)
144#define MCFINTC2_GPIOIRQ3 (MCFINTC2_VECBASE + 35)
145#define MCFINTC2_GPIOIRQ4 (MCFINTC2_VECBASE + 36)
146#define MCFINTC2_GPIOIRQ5 (MCFINTC2_VECBASE + 37)
147#define MCFINTC2_GPIOIRQ6 (MCFINTC2_VECBASE + 38)
148#define MCFINTC2_GPIOIRQ7 (MCFINTC2_VECBASE + 39)
149
150/*
sfking@fdwdc.com9e8ded12009-06-19 18:11:05 -0700151 * Generic GPIO support
152 */
153#define MCFGPIO_PIN_MAX 64
154#define MCFGPIO_IRQ_MAX -1
155#define MCFGPIO_IRQ_VECBASE -1
Linus Torvalds1da177e2005-04-16 15:20:36 -0700156
157/****************************************************************************/
158
159#ifdef __ASSEMBLER__
160
161/*
162 * The M5249C3 board needs a little help getting all its SIM devices
163 * initialized at kernel start time. dBUG doesn't set much up, so
164 * we need to do it manually.
165 */
166.macro m5249c3_setup
167 /*
168 * Set MBAR1 and MBAR2, just incase they are not set.
169 */
170 movel #0x10000001,%a0
171 movec %a0,%MBAR /* map MBAR region */
172 subql #1,%a0 /* get MBAR address in a0 */
173
174 movel #0x80000001,%a1
175 movec %a1,#3086 /* map MBAR2 region */
176 subql #1,%a1 /* get MBAR2 address in a1 */
177
178 /*
Greg Ungererda3601a2009-05-22 14:16:39 +1000179 * Move secondary interrupts to their base (128).
Linus Torvalds1da177e2005-04-16 15:20:36 -0700180 */
Greg Ungererda3601a2009-05-22 14:16:39 +1000181 moveb #MCFINTC2_VECBASE,%d0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700182 moveb %d0,0x16b(%a1) /* interrupt base register */
183
184 /*
185 * Work around broken CSMR0/DRAM vector problem.
186 */
187 movel #0x001F0021,%d0 /* disable C/I bit */
188 movel %d0,0x84(%a0) /* set CSMR0 */
189
190 /*
191 * Disable the PLL firstly. (Who knows what state it is
192 * in here!).
193 */
194 movel 0x180(%a1),%d0 /* get current PLL value */
195 andl #0xfffffffe,%d0 /* PLL bypass first */
196 movel %d0,0x180(%a1) /* set PLL register */
197 nop
198
Greg Ungererafd1b832006-06-26 11:43:35 +1000199#if CONFIG_CLOCK_FREQ == 140000000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700200 /*
201 * Set initial clock frequency. This assumes M5249C3 board
202 * is fitted with 11.2896MHz crystal. It will program the
203 * PLL for 140MHz. Lets go fast :-)
204 */
205 movel #0x125a40f0,%d0 /* set for 140MHz */
206 movel %d0,0x180(%a1) /* set PLL register */
207 orl #0x1,%d0
208 movel %d0,0x180(%a1) /* set PLL register */
209#endif
210
211 /*
212 * Setup CS1 for ethernet controller.
213 * (Setup as per M5249C3 doco).
214 */
215 movel #0xe0000000,%d0 /* CS1 mapped at 0xe0000000 */
216 movel %d0,0x8c(%a0)
217 movel #0x001f0021,%d0 /* CS1 size of 1Mb */
218 movel %d0,0x90(%a0)
219 movew #0x0080,%d0 /* CS1 = 16bit port, AA */
220 movew %d0,0x96(%a0)
221
222 /*
223 * Setup CS2 for IDE interface.
224 */
225 movel #0x50000000,%d0 /* CS2 mapped at 0x50000000 */
226 movel %d0,0x98(%a0)
227 movel #0x001f0001,%d0 /* CS2 size of 1MB */
228 movel %d0,0x9c(%a0)
229 movew #0x0080,%d0 /* CS2 = 16bit, TA */
230 movew %d0,0xa2(%a0)
231
232 movel #0x00107000,%d0 /* IDEconfig1 */
233 movel %d0,0x18c(%a1)
234 movel #0x000c0400,%d0 /* IDEconfig2 */
235 movel %d0,0x190(%a1)
236
237 movel #0x00080000,%d0 /* GPIO19, IDE reset bit */
238 orl %d0,0xc(%a1) /* function GPIO19 */
239 orl %d0,0x8(%a1) /* enable GPIO19 as output */
240 orl %d0,0x4(%a1) /* de-assert IDE reset */
241.endm
242
243#define PLATFORM_SETUP m5249c3_setup
244
245#endif /* __ASSEMBLER__ */
246
247/****************************************************************************/
248#endif /* m5249sim_h */