Vegard Nossum | 77ef50a | 2008-06-18 17:08:48 +0200 | [diff] [blame] | 1 | #ifndef ASM_X86__GART_H |
| 2 | #define ASM_X86__GART_H |
Joerg Roedel | 395624f | 2007-10-24 12:49:47 +0200 | [diff] [blame] | 3 | |
Pavel Machek | 0abbc78 | 2008-05-20 16:27:17 +0200 | [diff] [blame] | 4 | #include <asm/e820.h> |
| 5 | |
Rafael J. Wysocki | 6703f6d | 2008-06-10 00:10:48 +0200 | [diff] [blame] | 6 | extern void set_up_gart_resume(u32, u32); |
FUJITA Tomonori | e93be88 | 2008-07-10 08:27:49 +0900 | [diff] [blame] | 7 | |
Joerg Roedel | 395624f | 2007-10-24 12:49:47 +0200 | [diff] [blame] | 8 | extern int fallback_aper_order; |
| 9 | extern int fallback_aper_force; |
Joerg Roedel | 395624f | 2007-10-24 12:49:47 +0200 | [diff] [blame] | 10 | extern int fix_aperture; |
Joerg Roedel | 395624f | 2007-10-24 12:49:47 +0200 | [diff] [blame] | 11 | |
Pavel Machek | aa134f1 | 2008-04-08 10:49:03 +0200 | [diff] [blame] | 12 | /* PTE bits. */ |
| 13 | #define GPTE_VALID 1 |
| 14 | #define GPTE_COHERENT 2 |
| 15 | |
| 16 | /* Aperture control register bits. */ |
| 17 | #define GARTEN (1<<0) |
| 18 | #define DISGARTCPU (1<<4) |
| 19 | #define DISGARTIO (1<<5) |
| 20 | |
| 21 | /* GART cache control register bits. */ |
| 22 | #define INVGART (1<<0) |
| 23 | #define GARTPTEERR (1<<1) |
| 24 | |
| 25 | /* K8 On-cpu GART registers */ |
| 26 | #define AMD64_GARTAPERTURECTL 0x90 |
| 27 | #define AMD64_GARTAPERTUREBASE 0x94 |
| 28 | #define AMD64_GARTTABLEBASE 0x98 |
| 29 | #define AMD64_GARTCACHECTL 0x9c |
| 30 | #define AMD64_GARTEN (1<<0) |
| 31 | |
Joerg Roedel | 237a622 | 2008-09-25 12:13:53 +0200 | [diff] [blame] | 32 | extern int agp_amd64_init(void); |
| 33 | |
Pavel Machek | 3bb6fbf | 2008-04-15 12:43:57 +0200 | [diff] [blame] | 34 | static inline void enable_gart_translation(struct pci_dev *dev, u64 addr) |
| 35 | { |
| 36 | u32 tmp, ctl; |
| 37 | |
| 38 | /* address of the mappings table */ |
| 39 | addr >>= 12; |
| 40 | tmp = (u32) addr<<4; |
| 41 | tmp &= ~0xf; |
| 42 | pci_write_config_dword(dev, AMD64_GARTTABLEBASE, tmp); |
| 43 | |
| 44 | /* Enable GART translation for this hammer. */ |
| 45 | pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl); |
| 46 | ctl |= GARTEN; |
| 47 | ctl &= ~(DISGARTCPU | DISGARTIO); |
| 48 | pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl); |
| 49 | } |
| 50 | |
Pavel Machek | 0abbc78 | 2008-05-20 16:27:17 +0200 | [diff] [blame] | 51 | static inline int aperture_valid(u64 aper_base, u32 aper_size, u32 min_size) |
| 52 | { |
| 53 | if (!aper_base) |
| 54 | return 0; |
| 55 | |
| 56 | if (aper_base + aper_size > 0x100000000ULL) { |
Adam Jackson | 9b15684 | 2008-09-29 14:52:03 -0400 | [diff] [blame] | 57 | printk(KERN_INFO "Aperture beyond 4GB. Ignoring.\n"); |
Pavel Machek | 0abbc78 | 2008-05-20 16:27:17 +0200 | [diff] [blame] | 58 | return 0; |
| 59 | } |
| 60 | if (e820_any_mapped(aper_base, aper_base + aper_size, E820_RAM)) { |
Adam Jackson | 9b15684 | 2008-09-29 14:52:03 -0400 | [diff] [blame] | 61 | printk(KERN_INFO "Aperture pointing to e820 RAM. Ignoring.\n"); |
Pavel Machek | 0abbc78 | 2008-05-20 16:27:17 +0200 | [diff] [blame] | 62 | return 0; |
| 63 | } |
| 64 | if (aper_size < min_size) { |
Adam Jackson | 9b15684 | 2008-09-29 14:52:03 -0400 | [diff] [blame] | 65 | printk(KERN_INFO "Aperture too small (%d MB) than (%d MB)\n", |
Pavel Machek | 0abbc78 | 2008-05-20 16:27:17 +0200 | [diff] [blame] | 66 | aper_size>>20, min_size>>20); |
| 67 | return 0; |
| 68 | } |
| 69 | |
| 70 | return 1; |
| 71 | } |
| 72 | |
Vegard Nossum | 77ef50a | 2008-06-18 17:08:48 +0200 | [diff] [blame] | 73 | #endif /* ASM_X86__GART_H */ |