blob: 01a89633e2659f0dba8f48098ed4e6de947e9451 [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001/*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Dave Airlie
30 */
31#include <linux/seq_file.h>
32#include <asm/atomic.h>
33#include <linux/wait.h>
34#include <linux/list.h>
35#include <linux/kref.h>
36#include "drmP.h"
37#include "drm.h"
38#include "radeon_reg.h"
39#include "radeon.h"
40
41int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence)
42{
43 unsigned long irq_flags;
44
45 write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
46 if (fence->emited) {
47 write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
48 return 0;
49 }
50 fence->seq = atomic_add_return(1, &rdev->fence_drv.seq);
51 if (!rdev->cp.ready) {
52 /* FIXME: cp is not running assume everythings is done right
53 * away
54 */
55 WREG32(rdev->fence_drv.scratch_reg, fence->seq);
Jerome Glisse3ce0a232009-09-08 10:10:24 +100056 } else
Jerome Glisse771fe6b2009-06-05 14:42:42 +020057 radeon_fence_ring_emit(rdev, fence);
Jerome Glisse3ce0a232009-09-08 10:10:24 +100058
Jerome Glisse771fe6b2009-06-05 14:42:42 +020059 fence->emited = true;
60 fence->timeout = jiffies + ((2000 * HZ) / 1000);
61 list_del(&fence->list);
62 list_add_tail(&fence->list, &rdev->fence_drv.emited);
63 write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
64 return 0;
65}
66
67static bool radeon_fence_poll_locked(struct radeon_device *rdev)
68{
69 struct radeon_fence *fence;
70 struct list_head *i, *n;
71 uint32_t seq;
72 bool wake = false;
73
74 if (rdev == NULL) {
75 return true;
76 }
77 if (rdev->shutdown) {
78 return true;
79 }
80 seq = RREG32(rdev->fence_drv.scratch_reg);
81 rdev->fence_drv.last_seq = seq;
82 n = NULL;
83 list_for_each(i, &rdev->fence_drv.emited) {
84 fence = list_entry(i, struct radeon_fence, list);
85 if (fence->seq == seq) {
86 n = i;
87 break;
88 }
89 }
90 /* all fence previous to this one are considered as signaled */
91 if (n) {
92 i = n;
93 do {
94 n = i->prev;
95 list_del(i);
96 list_add_tail(i, &rdev->fence_drv.signaled);
97 fence = list_entry(i, struct radeon_fence, list);
98 fence->signaled = true;
99 i = n;
100 } while (i != &rdev->fence_drv.emited);
101 wake = true;
102 }
103 return wake;
104}
105
106static void radeon_fence_destroy(struct kref *kref)
107{
108 unsigned long irq_flags;
109 struct radeon_fence *fence;
110
111 fence = container_of(kref, struct radeon_fence, kref);
112 write_lock_irqsave(&fence->rdev->fence_drv.lock, irq_flags);
113 list_del(&fence->list);
114 fence->emited = false;
115 write_unlock_irqrestore(&fence->rdev->fence_drv.lock, irq_flags);
116 kfree(fence);
117}
118
119int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence)
120{
121 unsigned long irq_flags;
122
123 *fence = kmalloc(sizeof(struct radeon_fence), GFP_KERNEL);
124 if ((*fence) == NULL) {
125 return -ENOMEM;
126 }
127 kref_init(&((*fence)->kref));
128 (*fence)->rdev = rdev;
129 (*fence)->emited = false;
130 (*fence)->signaled = false;
131 (*fence)->seq = 0;
132 INIT_LIST_HEAD(&(*fence)->list);
133
134 write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
135 list_add_tail(&(*fence)->list, &rdev->fence_drv.created);
136 write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
137 return 0;
138}
139
140
141bool radeon_fence_signaled(struct radeon_fence *fence)
142{
143 struct radeon_device *rdev = fence->rdev;
144 unsigned long irq_flags;
145 bool signaled = false;
146
147 if (rdev->gpu_lockup) {
148 return true;
149 }
150 if (fence == NULL) {
151 return true;
152 }
153 write_lock_irqsave(&fence->rdev->fence_drv.lock, irq_flags);
154 signaled = fence->signaled;
155 /* if we are shuting down report all fence as signaled */
156 if (fence->rdev->shutdown) {
157 signaled = true;
158 }
159 if (!fence->emited) {
160 WARN(1, "Querying an unemited fence : %p !\n", fence);
161 signaled = true;
162 }
163 if (!signaled) {
164 radeon_fence_poll_locked(fence->rdev);
165 signaled = fence->signaled;
166 }
167 write_unlock_irqrestore(&fence->rdev->fence_drv.lock, irq_flags);
168 return signaled;
169}
170
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000171int r600_fence_wait(struct radeon_fence *fence, bool intr, bool lazy)
172{
173 struct radeon_device *rdev;
174 unsigned long cur_jiffies;
175 unsigned long timeout;
176 int ret = 0;
177
178 cur_jiffies = jiffies;
179 timeout = HZ / 100;
180
181 if (time_after(fence->timeout, cur_jiffies)) {
182 timeout = fence->timeout - cur_jiffies;
183 }
184
185 rdev = fence->rdev;
186
187 __set_current_state(intr ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
188
189 while (1) {
190 if (radeon_fence_signaled(fence))
191 break;
192
193 if (time_after_eq(jiffies, timeout)) {
194 ret = -EBUSY;
195 break;
196 }
197
198 if (lazy)
199 schedule_timeout(1);
200
201 if (intr && signal_pending(current)) {
Dave Airliec746e202009-09-08 14:38:45 +1000202 ret = -ERESTARTSYS;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000203 break;
204 }
205 }
206 __set_current_state(TASK_RUNNING);
207 return ret;
208}
209
210
211int radeon_fence_wait(struct radeon_fence *fence, bool intr)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200212{
213 struct radeon_device *rdev;
214 unsigned long cur_jiffies;
215 unsigned long timeout;
216 bool expired = false;
217 int r;
218
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200219 if (fence == NULL) {
220 WARN(1, "Querying an invalid fence : %p !\n", fence);
221 return 0;
222 }
223 rdev = fence->rdev;
224 if (radeon_fence_signaled(fence)) {
225 return 0;
226 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000227
Dave Airliec746e202009-09-08 14:38:45 +1000228 if (rdev->family >= CHIP_R600) {
229 r = r600_fence_wait(fence, intr, 0);
230 if (r == -ERESTARTSYS)
231 return -EBUSY;
232 return r;
233 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000234
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200235retry:
236 cur_jiffies = jiffies;
237 timeout = HZ / 100;
238 if (time_after(fence->timeout, cur_jiffies)) {
239 timeout = fence->timeout - cur_jiffies;
240 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000241
242 if (intr) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200243 r = wait_event_interruptible_timeout(rdev->fence_drv.queue,
244 radeon_fence_signaled(fence), timeout);
245 if (unlikely(r == -ERESTARTSYS)) {
Dave Airlie3b170c32009-07-24 13:47:45 +1000246 return -EBUSY;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200247 }
248 } else {
249 r = wait_event_timeout(rdev->fence_drv.queue,
250 radeon_fence_signaled(fence), timeout);
251 }
252 if (unlikely(!radeon_fence_signaled(fence))) {
253 if (unlikely(r == 0)) {
254 expired = true;
255 }
256 if (unlikely(expired)) {
257 timeout = 1;
258 if (time_after(cur_jiffies, fence->timeout)) {
259 timeout = cur_jiffies - fence->timeout;
260 }
261 timeout = jiffies_to_msecs(timeout);
262 if (timeout > 500) {
263 DRM_ERROR("fence(%p:0x%08X) %lums timeout "
264 "going to reset GPU\n",
265 fence, fence->seq, timeout);
266 radeon_gpu_reset(rdev);
267 WREG32(rdev->fence_drv.scratch_reg, fence->seq);
268 }
269 }
270 goto retry;
271 }
272 if (unlikely(expired)) {
273 rdev->fence_drv.count_timeout++;
274 cur_jiffies = jiffies;
275 timeout = 1;
276 if (time_after(cur_jiffies, fence->timeout)) {
277 timeout = cur_jiffies - fence->timeout;
278 }
279 timeout = jiffies_to_msecs(timeout);
280 DRM_ERROR("fence(%p:0x%08X) %lums timeout\n",
281 fence, fence->seq, timeout);
282 DRM_ERROR("last signaled fence(0x%08X)\n",
283 rdev->fence_drv.last_seq);
284 }
285 return 0;
286}
287
288int radeon_fence_wait_next(struct radeon_device *rdev)
289{
290 unsigned long irq_flags;
291 struct radeon_fence *fence;
292 int r;
293
294 if (rdev->gpu_lockup) {
295 return 0;
296 }
297 write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
298 if (list_empty(&rdev->fence_drv.emited)) {
299 write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
300 return 0;
301 }
302 fence = list_entry(rdev->fence_drv.emited.next,
303 struct radeon_fence, list);
304 radeon_fence_ref(fence);
305 write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
306 r = radeon_fence_wait(fence, false);
307 radeon_fence_unref(&fence);
308 return r;
309}
310
311int radeon_fence_wait_last(struct radeon_device *rdev)
312{
313 unsigned long irq_flags;
314 struct radeon_fence *fence;
315 int r;
316
317 if (rdev->gpu_lockup) {
318 return 0;
319 }
320 write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
321 if (list_empty(&rdev->fence_drv.emited)) {
322 write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
323 return 0;
324 }
325 fence = list_entry(rdev->fence_drv.emited.prev,
326 struct radeon_fence, list);
327 radeon_fence_ref(fence);
328 write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
329 r = radeon_fence_wait(fence, false);
330 radeon_fence_unref(&fence);
331 return r;
332}
333
334struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence)
335{
336 kref_get(&fence->kref);
337 return fence;
338}
339
340void radeon_fence_unref(struct radeon_fence **fence)
341{
342 struct radeon_fence *tmp = *fence;
343
344 *fence = NULL;
345 if (tmp) {
346 kref_put(&tmp->kref, &radeon_fence_destroy);
347 }
348}
349
350void radeon_fence_process(struct radeon_device *rdev)
351{
352 unsigned long irq_flags;
353 bool wake;
354
355 write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
356 wake = radeon_fence_poll_locked(rdev);
357 write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
358 if (wake) {
359 wake_up_all(&rdev->fence_drv.queue);
360 }
361}
362
363int radeon_fence_driver_init(struct radeon_device *rdev)
364{
365 unsigned long irq_flags;
366 int r;
367
368 write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
369 r = radeon_scratch_get(rdev, &rdev->fence_drv.scratch_reg);
370 if (r) {
371 DRM_ERROR("Fence failed to get a scratch register.");
372 write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
373 return r;
374 }
375 WREG32(rdev->fence_drv.scratch_reg, 0);
376 atomic_set(&rdev->fence_drv.seq, 0);
377 INIT_LIST_HEAD(&rdev->fence_drv.created);
378 INIT_LIST_HEAD(&rdev->fence_drv.emited);
379 INIT_LIST_HEAD(&rdev->fence_drv.signaled);
380 rdev->fence_drv.count_timeout = 0;
381 init_waitqueue_head(&rdev->fence_drv.queue);
382 write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
383 if (radeon_debugfs_fence_init(rdev)) {
384 DRM_ERROR("Failed to register debugfs file for fence !\n");
385 }
386 return 0;
387}
388
389void radeon_fence_driver_fini(struct radeon_device *rdev)
390{
391 unsigned long irq_flags;
392
393 wake_up_all(&rdev->fence_drv.queue);
394 write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
395 radeon_scratch_free(rdev, rdev->fence_drv.scratch_reg);
396 write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
397 DRM_INFO("radeon: fence finalized\n");
398}
399
400
401/*
402 * Fence debugfs
403 */
404#if defined(CONFIG_DEBUG_FS)
405static int radeon_debugfs_fence_info(struct seq_file *m, void *data)
406{
407 struct drm_info_node *node = (struct drm_info_node *)m->private;
408 struct drm_device *dev = node->minor->dev;
409 struct radeon_device *rdev = dev->dev_private;
410 struct radeon_fence *fence;
411
412 seq_printf(m, "Last signaled fence 0x%08X\n",
413 RREG32(rdev->fence_drv.scratch_reg));
414 if (!list_empty(&rdev->fence_drv.emited)) {
415 fence = list_entry(rdev->fence_drv.emited.prev,
416 struct radeon_fence, list);
417 seq_printf(m, "Last emited fence %p with 0x%08X\n",
418 fence, fence->seq);
419 }
420 return 0;
421}
422
423static struct drm_info_list radeon_debugfs_fence_list[] = {
424 {"radeon_fence_info", &radeon_debugfs_fence_info, 0, NULL},
425};
426#endif
427
428int radeon_debugfs_fence_init(struct radeon_device *rdev)
429{
430#if defined(CONFIG_DEBUG_FS)
431 return radeon_debugfs_add_files(rdev, radeon_debugfs_fence_list, 1);
432#else
433 return 0;
434#endif
435}