Gitiles
Code Review Sign In
gerrit-public.fairphone.software / fp2-dev / kernel / msm / cd7e4a2cbb147a2f15abfad93e1af847e6bb339f / . / arch / powerpc / boot / dts / mpc8569mds.dts
blob: fb67910927f189651a996ac2d343e9ac033207d5 [file] [log] [blame]
Haiying Wang4b3b42b2009-05-01 15:40:50 -0400[diff] [blame]1/*
2 * MPC8569E MDS Device Tree Source
3 *
4 * Copyright (C) 2009 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15 model = "MPC8569EMDS";
16 compatible = "fsl,MPC8569EMDS";
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 aliases {
21 serial0 = &serial0;
22 serial1 = &serial1;
23 ethernet0 = &enet0;
24 ethernet1 = &enet1;
25 ethernet2 = &enet2;
26 ethernet3 = &enet3;
27 pci1 = &pci1;
28 };
29
30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
33
34 PowerPC,8569@0 {
35 device_type = "cpu";
36 reg = <0x0>;
37 d-cache-line-size = <32>; // 32 bytes
38 i-cache-line-size = <32>; // 32 bytes
39 d-cache-size = <0x8000>; // L1, 32K
40 i-cache-size = <0x8000>; // L1, 32K
41 timebase-frequency = <0>;
42 bus-frequency = <0>;
43 clock-frequency = <0>;
44 next-level-cache = <&L2>;
45 };
46 };
47
48 memory {
49 device_type = "memory";
50 };
51
52 localbus@e0005000 {
53 #address-cells = <2>;
54 #size-cells = <1>;
55 compatible = "fsl,mpc8569-elbc", "fsl,elbc", "simple-bus";
56 reg = <0 0xe0005000 0 0x1000>;
57 interrupt = <19 2>;
58 interrupt-parent = <&mpic>;
59
60 ranges = <0x0 0x0 0xfe000000 0x02000000
61 0x1 0x0 0xf8000000 0x00008000
62 0x2 0x0 0xf0000000 0x04000000
63 0x4 0x0 0xf8008000 0x00008000
64 0x5 0x0 0xf8010000 0x00008000>;
65
66 nor@0,0 {
67 #address-cells = <1>;
68 #size-cells = <1>;
69 compatible = "cfi-flash";
70 reg = <0x0 0x0 0x02000000>;
71 bank-width = <2>;
72 device-width = <1>;
73 };
74
75 bcsr@1,0 {
76 compatible = "fsl,mpc8569mds-bcsr";
77 reg = <1 0 0x8000>;
78 };
79
80 pib@4,0 {
81 compatible = "fsl,mpc8569mds-pib";
82 reg = <4 0 0x8000>;
83 };
84
85 pib@5,0 {
86 compatible = "fsl,mpc8569mds-pib";
87 reg = <5 0 0x8000>;
88 };
89 };
90
91 soc@e0000000 {
92 #address-cells = <1>;
93 #size-cells = <1>;
94 device_type = "soc";
95 compatible = "fsl,mpc8569-immr", "simple-bus";
96 ranges = <0x0 0xe0000000 0x100000>;
Haiying Wang4b3b42b2009-05-01 15:40:50 -0400[diff] [blame]97 bus-frequency = <0>;
98
99 ecm-law@0 {
100 compatible = "fsl,ecm-law";
101 reg = <0x0 0x1000>;
102 fsl,num-laws = <10>;
103 };
104
105 ecm@1000 {
106 compatible = "fsl,mpc8569-ecm", "fsl,ecm";
107 reg = <0x1000 0x1000>;
108 interrupts = <17 2>;
109 interrupt-parent = <&mpic>;
110 };
111
112 memory-controller@2000 {
113 compatible = "fsl,mpc8569-memory-controller";
114 reg = <0x2000 0x1000>;
115 interrupt-parent = <&mpic>;
116 interrupts = <18 2>;
117 };
118
119 i2c@3000 {
120 #address-cells = <1>;
121 #size-cells = <0>;
122 cell-index = <0>;
123 compatible = "fsl-i2c";
124 reg = <0x3000 0x100>;
125 interrupts = <43 2>;
126 interrupt-parent = <&mpic>;
127 dfsrr;
128
129 rtc@68 {
130 compatible = "dallas,ds1374";
131 reg = <0x68>;
132 };
133 };
134
135 i2c@3100 {
136 #address-cells = <1>;
137 #size-cells = <0>;
138 cell-index = <1>;
139 compatible = "fsl-i2c";
140 reg = <0x3100 0x100>;
141 interrupts = <43 2>;
142 interrupt-parent = <&mpic>;
143 dfsrr;
144 };
145
146 serial0: serial@4500 {
147 cell-index = <0>;
148 device_type = "serial";
149 compatible = "ns16550";
150 reg = <0x4500 0x100>;
151 clock-frequency = <0>;
152 interrupts = <42 2>;
153 interrupt-parent = <&mpic>;
154 };
155
156 serial1: serial@4600 {
157 cell-index = <1>;
158 device_type = "serial";
159 compatible = "ns16550";
160 reg = <0x4600 0x100>;
161 clock-frequency = <0>;
162 interrupts = <42 2>;
163 interrupt-parent = <&mpic>;
164 };
165
166 L2: l2-cache-controller@20000 {
167 compatible = "fsl,mpc8569-l2-cache-controller";
168 reg = <0x20000 0x1000>;
169 cache-line-size = <32>; // 32 bytes
170 cache-size = <0x80000>; // L2, 512K
171 interrupt-parent = <&mpic>;
172 interrupts = <16 2>;
173 };
174
175 dma@21300 {
176 #address-cells = <1>;
177 #size-cells = <1>;
178 compatible = "fsl,mpc8569-dma", "fsl,eloplus-dma";
179 reg = <0x21300 0x4>;
180 ranges = <0x0 0x21100 0x200>;
181 cell-index = <0>;
182 dma-channel@0 {
183 compatible = "fsl,mpc8569-dma-channel",
184 "fsl,eloplus-dma-channel";
185 reg = <0x0 0x80>;
186 cell-index = <0>;
187 interrupt-parent = <&mpic>;
188 interrupts = <20 2>;
189 };
190 dma-channel@80 {
191 compatible = "fsl,mpc8569-dma-channel",
192 "fsl,eloplus-dma-channel";
193 reg = <0x80 0x80>;
194 cell-index = <1>;
195 interrupt-parent = <&mpic>;
196 interrupts = <21 2>;
197 };
198 dma-channel@100 {
199 compatible = "fsl,mpc8569-dma-channel",
200 "fsl,eloplus-dma-channel";
201 reg = <0x100 0x80>;
202 cell-index = <2>;
203 interrupt-parent = <&mpic>;
204 interrupts = <22 2>;
205 };
206 dma-channel@180 {
207 compatible = "fsl,mpc8569-dma-channel",
208 "fsl,eloplus-dma-channel";
209 reg = <0x180 0x80>;
210 cell-index = <3>;
211 interrupt-parent = <&mpic>;
212 interrupts = <23 2>;
213 };
214 };
215
216 crypto@30000 {
217 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
218 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
219 reg = <0x30000 0x10000>;
220 interrupts = <45 2 58 2>;
221 interrupt-parent = <&mpic>;
222 fsl,num-channels = <4>;
223 fsl,channel-fifo-len = <24>;
Anton Vorontsovcd7e4a22009-05-02 06:16:49 +0400[diff] [blame^]224 fsl,exec-units-mask = <0xbfe>;
Haiying Wang4b3b42b2009-05-01 15:40:50 -0400[diff] [blame]225 fsl,descriptor-types-mask = <0x3ab0ebf>;
226 };
227
228 mpic: pic@40000 {
229 interrupt-controller;
230 #address-cells = <0>;
231 #interrupt-cells = <2>;
232 reg = <0x40000 0x40000>;
233 compatible = "chrp,open-pic";
234 device_type = "open-pic";
235 };
236
237 global-utilities@e0000 {
238 compatible = "fsl,mpc8569-guts";
239 reg = <0xe0000 0x1000>;
240 fsl,has-rstcr;
241 };
242
243 par_io@e0100 {
244 reg = <0xe0100 0x100>;
245 device_type = "par_io";
246 num-ports = <7>;
247
248 pio1: ucc_pin@01 {
249 pio-map = <
250 /* port pin dir open_drain assignment has_irq */
251 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
252 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
253 0x2 0x0b 0x2 0x0 0x1 0x0 /* CLK12*/
254 0x0 0x0 0x1 0x0 0x3 0x0 /* ENET1_TXD0_SER1_TXD0 */
255 0x0 0x1 0x1 0x0 0x3 0x0 /* ENET1_TXD1_SER1_TXD1 */
256 0x0 0x2 0x1 0x0 0x1 0x0 /* ENET1_TXD2_SER1_TXD2 */
257 0x0 0x3 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */
258 0x0 0x6 0x2 0x0 0x3 0x0 /* ENET1_RXD0_SER1_RXD0 */
259 0x0 0x7 0x2 0x0 0x1 0x0 /* ENET1_RXD1_SER1_RXD1 */
260 0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */
261 0x0 0x9 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */
262 0x0 0x4 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */
263 0x0 0xc 0x2 0x0 0x3 0x0 /* ENET1_RX_DV_SER1_CTS_B */
264 0x2 0x8 0x2 0x0 0x1 0x0 /* ENET1_GRXCLK */
265 0x2 0x14 0x1 0x0 0x2 0x0>; /* ENET1_GTXCLK */
266 };
267
268 pio2: ucc_pin@02 {
269 pio-map = <
270 /* port pin dir open_drain assignment has_irq */
271 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
272 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
273 0x2 0x10 0x2 0x0 0x3 0x0 /* CLK17 */
274 0x0 0xe 0x1 0x0 0x2 0x0 /* ENET2_TXD0_SER2_TXD0 */
275 0x0 0xf 0x1 0x0 0x2 0x0 /* ENET2_TXD1_SER2_TXD1 */
276 0x0 0x10 0x1 0x0 0x1 0x0 /* ENET2_TXD2_SER2_TXD2 */
277 0x0 0x11 0x1 0x0 0x1 0x0 /* ENET2_TXD3_SER2_TXD3 */
278 0x0 0x14 0x2 0x0 0x2 0x0 /* ENET2_RXD0_SER2_RXD0 */
279 0x0 0x15 0x2 0x0 0x1 0x0 /* ENET2_RXD1_SER2_RXD1 */
280 0x0 0x16 0x2 0x0 0x1 0x0 /* ENET2_RXD2_SER2_RXD2 */
281 0x0 0x17 0x2 0x0 0x1 0x0 /* ENET2_RXD3_SER2_RXD3 */
282 0x0 0x12 0x1 0x0 0x2 0x0 /* ENET2_TX_EN_SER2_RTS_B */
283 0x0 0x1a 0x2 0x0 0x3 0x0 /* ENET2_RX_DV_SER2_CTS_B */
284 0x2 0x3 0x2 0x0 0x1 0x0 /* ENET2_GRXCLK */
285 0x2 0x2 0x1 0x0 0x2 0x0>; /* ENET2_GTXCLK */
286 };
287
288 pio3: ucc_pin@03 {
289 pio-map = <
290 /* port pin dir open_drain assignment has_irq */
291 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
292 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
293 0x2 0x0b 0x2 0x0 0x1 0x0 /* CLK12*/
294 0x0 0x1d 0x1 0x0 0x2 0x0 /* ENET3_TXD0_SER3_TXD0 */
295 0x0 0x1e 0x1 0x0 0x3 0x0 /* ENET3_TXD1_SER3_TXD1 */
296 0x0 0x1f 0x1 0x0 0x2 0x0 /* ENET3_TXD2_SER3_TXD2 */
297 0x1 0x0 0x1 0x0 0x3 0x0 /* ENET3_TXD3_SER3_TXD3 */
298 0x1 0x3 0x2 0x0 0x3 0x0 /* ENET3_RXD0_SER3_RXD0 */
299 0x1 0x4 0x2 0x0 0x1 0x0 /* ENET3_RXD1_SER3_RXD1 */
300 0x1 0x5 0x2 0x0 0x2 0x0 /* ENET3_RXD2_SER3_RXD2 */
301 0x1 0x6 0x2 0x0 0x3 0x0 /* ENET3_RXD3_SER3_RXD3 */
302 0x1 0x1 0x1 0x0 0x1 0x0 /* ENET3_TX_EN_SER3_RTS_B */
303 0x1 0x9 0x2 0x0 0x3 0x0 /* ENET3_RX_DV_SER3_CTS_B */
304 0x2 0x9 0x2 0x0 0x2 0x0 /* ENET3_GRXCLK */
305 0x2 0x19 0x1 0x0 0x2 0x0>; /* ENET3_GTXCLK */
306 };
307
308 pio4: ucc_pin@04 {
309 pio-map = <
310 /* port pin dir open_drain assignment has_irq */
311 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
312 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
313 0x2 0x10 0x2 0x0 0x3 0x0 /* CLK17 */
314 0x1 0xc 0x1 0x0 0x2 0x0 /* ENET4_TXD0_SER4_TXD0 */
315 0x1 0xd 0x1 0x0 0x2 0x0 /* ENET4_TXD1_SER4_TXD1 */
316 0x1 0xe 0x1 0x0 0x1 0x0 /* ENET4_TXD2_SER4_TXD2 */
317 0x1 0xf 0x1 0x0 0x2 0x0 /* ENET4_TXD3_SER4_TXD3 */
318 0x1 0x12 0x2 0x0 0x2 0x0 /* ENET4_RXD0_SER4_RXD0 */
319 0x1 0x13 0x2 0x0 0x1 0x0 /* ENET4_RXD1_SER4_RXD1 */
320 0x1 0x14 0x2 0x0 0x1 0x0 /* ENET4_RXD2_SER4_RXD2 */
321 0x1 0x15 0x2 0x0 0x2 0x0 /* ENET4_RXD3_SER4_RXD3 */
322 0x1 0x10 0x1 0x0 0x2 0x0 /* ENET4_TX_EN_SER4_RTS_B */
323 0x1 0x18 0x2 0x0 0x3 0x0 /* ENET4_RX_DV_SER4_CTS_B */
324 0x2 0x11 0x2 0x0 0x2 0x0 /* ENET4_GRXCLK */
325 0x2 0x18 0x1 0x0 0x2 0x0>; /* ENET4_GTXCLK */
326 };
327 };
328 };
329
330 qe@e0080000 {
331 #address-cells = <1>;
332 #size-cells = <1>;
333 device_type = "qe";
334 compatible = "fsl,qe";
335 ranges = <0x0 0xe0080000 0x40000>;
336 reg = <0xe0080000 0x480>;
337 brg-frequency = <0>;
338 bus-frequency = <0>;
339 fsl,qe-num-riscs = <4>;
340 fsl,qe-num-snums = <46>;
341
342 qeic: interrupt-controller@80 {
343 interrupt-controller;
344 compatible = "fsl,qe-ic";
345 #address-cells = <0>;
346 #interrupt-cells = <1>;
347 reg = <0x80 0x80>;
348 interrupts = <46 2 46 2>; //high:30 low:30
349 interrupt-parent = <&mpic>;
350 };
351
352 spi@4c0 {
353 cell-index = <0>;
354 compatible = "fsl,spi";
355 reg = <0x4c0 0x40>;
356 interrupts = <2>;
357 interrupt-parent = <&qeic>;
358 mode = "cpu";
359 };
360
361 spi@500 {
362 cell-index = <1>;
363 compatible = "fsl,spi";
364 reg = <0x500 0x40>;
365 interrupts = <1>;
366 interrupt-parent = <&qeic>;
367 mode = "cpu";
368 };
369
370 enet0: ucc@2000 {
371 device_type = "network";
372 compatible = "ucc_geth";
373 cell-index = <1>;
374 reg = <0x2000 0x200>;
375 interrupts = <32>;
376 interrupt-parent = <&qeic>;
377 local-mac-address = [ 00 00 00 00 00 00 ];
378 rx-clock-name = "none";
379 tx-clock-name = "clk12";
380 pio-handle = <&pio1>;
381 phy-handle = <&qe_phy0>;
382 phy-connection-type = "rgmii-id";
383 };
384
385 mdio@2120 {
386 #address-cells = <1>;
387 #size-cells = <0>;
388 reg = <0x2120 0x18>;
389 compatible = "fsl,ucc-mdio";
390
391 qe_phy0: ethernet-phy@07 {
392 interrupt-parent = <&mpic>;
393 interrupts = <1 1>;
394 reg = <0x7>;
395 device_type = "ethernet-phy";
396 };
397 qe_phy1: ethernet-phy@01 {
398 interrupt-parent = <&mpic>;
399 interrupts = <2 1>;
400 reg = <0x1>;
401 device_type = "ethernet-phy";
402 };
403 qe_phy2: ethernet-phy@02 {
404 interrupt-parent = <&mpic>;
405 interrupts = <3 1>;
406 reg = <0x2>;
407 device_type = "ethernet-phy";
408 };
409 qe_phy3: ethernet-phy@03 {
410 interrupt-parent = <&mpic>;
411 interrupts = <4 1>;
412 reg = <0x3>;
413 device_type = "ethernet-phy";
414 };
415 };
416
417 enet2: ucc@2200 {
418 device_type = "network";
419 compatible = "ucc_geth";
420 cell-index = <3>;
421 reg = <0x2200 0x200>;
422 interrupts = <34>;
423 interrupt-parent = <&qeic>;
424 local-mac-address = [ 00 00 00 00 00 00 ];
425 rx-clock-name = "none";
426 tx-clock-name = "clk12";
427 pio-handle = <&pio3>;
428 phy-handle = <&qe_phy2>;
429 phy-connection-type = "rgmii-id";
430 };
431
432 enet1: ucc@3000 {
433 device_type = "network";
434 compatible = "ucc_geth";
435 cell-index = <2>;
436 reg = <0x3000 0x200>;
437 interrupts = <33>;
438 interrupt-parent = <&qeic>;
439 local-mac-address = [ 00 00 00 00 00 00 ];
440 rx-clock-name = "none";
441 tx-clock-name = "clk17";
442 pio-handle = <&pio2>;
443 phy-handle = <&qe_phy1>;
444 phy-connection-type = "rgmii-id";
445 };
446
447 enet3: ucc@3200 {
448 device_type = "network";
449 compatible = "ucc_geth";
450 cell-index = <4>;
451 reg = <0x3200 0x200>;
452 interrupts = <35>;
453 interrupt-parent = <&qeic>;
454 local-mac-address = [ 00 00 00 00 00 00 ];
455 rx-clock-name = "none";
456 tx-clock-name = "clk17";
457 pio-handle = <&pio4>;
458 phy-handle = <&qe_phy3>;
459 phy-connection-type = "rgmii-id";
460 };
461
462 muram@10000 {
463 #address-cells = <1>;
464 #size-cells = <1>;
465 compatible = "fsl,qe-muram", "fsl,cpm-muram";
466 ranges = <0x0 0x10000 0x20000>;
467
468 data-only@0 {
469 compatible = "fsl,qe-muram-data",
470 "fsl,cpm-muram-data";
471 reg = <0x0 0x20000>;
472 };
473 };
474
475 };
476
477 /* PCI Express */
478 pci1: pcie@e000a000 {
479 compatible = "fsl,mpc8548-pcie";
480 device_type = "pci";
481 #interrupt-cells = <1>;
482 #size-cells = <2>;
483 #address-cells = <3>;
484 reg = <0xe000a000 0x1000>;
485 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
486 interrupt-map = <
487 /* IDSEL 0x0 (PEX) */
488 00000 0x0 0x0 0x1 &mpic 0x0 0x1
489 00000 0x0 0x0 0x2 &mpic 0x1 0x1
490 00000 0x0 0x0 0x3 &mpic 0x2 0x1
491 00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
492
493 interrupt-parent = <&mpic>;
494 interrupts = <26 2>;
495 bus-range = <0 255>;
496 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
497 0x1000000 0x0 0x00000000 0xe2800000 0x0 0x00800000>;
498 clock-frequency = <33333333>;
499 pcie@0 {
500 reg = <0x0 0x0 0x0 0x0 0x0>;
501 #size-cells = <2>;
502 #address-cells = <3>;
503 device_type = "pci";
504 ranges = <0x2000000 0x0 0xa0000000
505 0x2000000 0x0 0xa0000000
506 0x0 0x10000000
507
508 0x1000000 0x0 0x0
509 0x1000000 0x0 0x0
510 0x0 0x800000>;
511 };
512 };
513};