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Quinn Jensen52c543f2007-07-09 22:06:53 +01001/*
2 * Copyright (C) 2000 Deep Blue Solutions Ltd
3 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
4 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#include <linux/types.h>
22#include <linux/init.h>
23#include <linux/clk.h>
24#include <linux/serial_8250.h>
Mark Brownfe7316b2009-01-15 16:14:30 +000025#include <linux/gpio.h>
26#include <linux/i2c.h>
Gilles Chanteperdrixd7568f72008-09-09 10:19:42 +020027#include <linux/irq.h>
Quinn Jensen52c543f2007-07-09 22:06:53 +010028
Russell Kinga09e64f2008-08-05 16:14:15 +010029#include <mach/hardware.h>
Quinn Jensen52c543f2007-07-09 22:06:53 +010030#include <asm/mach-types.h>
31#include <asm/mach/arch.h>
Juergen Beisertd0f349f2008-07-05 10:02:50 +020032#include <asm/mach/time.h>
Quinn Jensen52c543f2007-07-09 22:06:53 +010033#include <asm/memory.h>
34#include <asm/mach/map.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010035#include <mach/common.h>
36#include <mach/board-mx31ads.h>
Gilles Chanteperdrix07417942008-09-09 10:19:41 +020037#include <mach/imx-uart.h>
38#include <mach/iomux-mx3.h>
Quinn Jensen52c543f2007-07-09 22:06:53 +010039
Mark Brownfe7316b2009-01-15 16:14:30 +000040#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
41#include <linux/mfd/wm8350/audio.h>
42#include <linux/mfd/wm8350/core.h>
43#include <linux/mfd/wm8350/pmic.h>
44#endif
45
Sascha Hauer2eca0472008-10-17 16:10:38 +020046#include "devices.h"
47
Quinn Jensen52c543f2007-07-09 22:06:53 +010048/*!
49 * @file mx31ads.c
50 *
51 * @brief This file contains the board-specific initialization routines.
52 *
53 * @ingroup System
54 */
55
56#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
57/*!
58 * The serial port definition structure.
59 */
60static struct plat_serial8250_port serial_platform_data[] = {
61 {
62 .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA),
63 .mapbase = (unsigned long)(CS4_BASE_ADDR + PBC_SC16C652_UARTA),
64 .irq = EXPIO_INT_XUART_INTA,
65 .uartclk = 14745600,
66 .regshift = 0,
67 .iotype = UPIO_MEM,
68 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
69 }, {
70 .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB),
71 .mapbase = (unsigned long)(CS4_BASE_ADDR + PBC_SC16C652_UARTB),
72 .irq = EXPIO_INT_XUART_INTB,
73 .uartclk = 14745600,
74 .regshift = 0,
75 .iotype = UPIO_MEM,
76 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
77 },
78 {},
79};
80
81static struct platform_device serial_device = {
82 .name = "serial8250",
83 .id = 0,
84 .dev = {
85 .platform_data = serial_platform_data,
86 },
87};
88
89static int __init mxc_init_extuart(void)
90{
91 return platform_device_register(&serial_device);
92}
93#else
94static inline int mxc_init_extuart(void)
95{
96 return 0;
97}
98#endif
99
Gilles Chanteperdrix07417942008-09-09 10:19:41 +0200100#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
101static struct imxuart_platform_data uart_pdata = {
102 .flags = IMXUART_HAVE_RTSCTS,
103};
104
Mark Brown9070e7a2009-04-13 13:02:36 +0100105static unsigned int uart_pins[] = {
Valentin Longchamp945c10b2009-01-28 15:13:52 +0100106 MX31_PIN_CTS1__CTS1,
107 MX31_PIN_RTS1__RTS1,
108 MX31_PIN_TXD1__TXD1,
109 MX31_PIN_RXD1__RXD1
110};
111
Gilles Chanteperdrix07417942008-09-09 10:19:41 +0200112static inline void mxc_init_imx_uart(void)
113{
Valentin Longchamp945c10b2009-01-28 15:13:52 +0100114 mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0");
Gilles Chanteperdrix07417942008-09-09 10:19:41 +0200115 mxc_register_device(&mxc_uart_device0, &uart_pdata);
116}
117#else /* !SERIAL_IMX */
118static inline void mxc_init_imx_uart(void)
119{
120}
121#endif /* !SERIAL_IMX */
122
Gilles Chanteperdrixd7568f72008-09-09 10:19:42 +0200123static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
124{
125 u32 imr_val;
126 u32 int_valid;
127 u32 expio_irq;
128
129 imr_val = __raw_readw(PBC_INTMASK_SET_REG);
130 int_valid = __raw_readw(PBC_INTSTATUS_REG) & imr_val;
131
132 expio_irq = MXC_EXP_IO_BASE;
133 for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
134 if ((int_valid & 1) == 0)
135 continue;
136
137 generic_handle_irq(expio_irq);
138 }
139}
140
141/*
142 * Disable an expio pin's interrupt by setting the bit in the imr.
143 * @param irq an expio virtual irq number
144 */
145static void expio_mask_irq(u32 irq)
146{
147 u32 expio = MXC_IRQ_TO_EXPIO(irq);
148 /* mask the interrupt */
149 __raw_writew(1 << expio, PBC_INTMASK_CLEAR_REG);
150 __raw_readw(PBC_INTMASK_CLEAR_REG);
151}
152
153/*
154 * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
155 * @param irq an expanded io virtual irq number
156 */
157static void expio_ack_irq(u32 irq)
158{
159 u32 expio = MXC_IRQ_TO_EXPIO(irq);
160 /* clear the interrupt status */
161 __raw_writew(1 << expio, PBC_INTSTATUS_REG);
162}
163
164/*
165 * Enable a expio pin's interrupt by clearing the bit in the imr.
166 * @param irq a expio virtual irq number
167 */
168static void expio_unmask_irq(u32 irq)
169{
170 u32 expio = MXC_IRQ_TO_EXPIO(irq);
171 /* unmask the interrupt */
172 __raw_writew(1 << expio, PBC_INTMASK_SET_REG);
173}
174
175static struct irq_chip expio_irq_chip = {
176 .ack = expio_ack_irq,
177 .mask = expio_mask_irq,
178 .unmask = expio_unmask_irq,
179};
180
181static void __init mx31ads_init_expio(void)
182{
183 int i;
184
185 printk(KERN_INFO "MX31ADS EXPIO(CPLD) hardware\n");
186
187 /*
188 * Configure INT line as GPIO input
189 */
Sascha Hauer4f163eb2009-05-06 12:55:50 +0200190 mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio");
Gilles Chanteperdrixd7568f72008-09-09 10:19:42 +0200191
192 /* disable the interrupt and clear the status */
193 __raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG);
194 __raw_writew(0xFFFF, PBC_INTSTATUS_REG);
195 for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
196 i++) {
197 set_irq_chip(i, &expio_irq_chip);
198 set_irq_handler(i, handle_level_irq);
199 set_irq_flags(i, IRQF_VALID);
200 }
201 set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH);
202 set_irq_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler);
203}
204
Mark Brownfe7316b2009-01-15 16:14:30 +0000205#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
206/* This section defines setup for the Wolfson Microelectronics
207 * 1133-EV1 PMU/audio board. When other PMU boards are supported the
208 * regulator definitions may be shared with them, but for now they can
209 * only be used with this board so would generate warnings about
210 * unused statics and some of the configuration is specific to this
211 * module.
212 */
213
214/* CPU */
215static struct regulator_consumer_supply sw1a_consumers[] = {
216 {
217 .supply = "cpu_vcc",
218 }
219};
220
221static struct regulator_init_data sw1a_data = {
222 .constraints = {
223 .name = "SW1A",
224 .min_uV = 1275000,
225 .max_uV = 1600000,
226 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
227 REGULATOR_CHANGE_MODE,
228 .valid_modes_mask = REGULATOR_MODE_NORMAL |
229 REGULATOR_MODE_FAST,
230 .state_mem = {
231 .uV = 1400000,
232 .mode = REGULATOR_MODE_NORMAL,
233 .enabled = 1,
234 },
235 .initial_state = PM_SUSPEND_MEM,
236 .always_on = 1,
237 .boot_on = 1,
238 },
239 .num_consumer_supplies = ARRAY_SIZE(sw1a_consumers),
240 .consumer_supplies = sw1a_consumers,
241};
242
243/* System IO - High */
244static struct regulator_init_data viohi_data = {
245 .constraints = {
246 .name = "VIOHO",
247 .min_uV = 2800000,
248 .max_uV = 2800000,
249 .state_mem = {
250 .uV = 2800000,
251 .mode = REGULATOR_MODE_NORMAL,
252 .enabled = 1,
253 },
254 .initial_state = PM_SUSPEND_MEM,
255 .always_on = 1,
256 .boot_on = 1,
257 },
258};
259
260/* System IO - Low */
261static struct regulator_init_data violo_data = {
262 .constraints = {
263 .name = "VIOLO",
264 .min_uV = 1800000,
265 .max_uV = 1800000,
266 .state_mem = {
267 .uV = 1800000,
268 .mode = REGULATOR_MODE_NORMAL,
269 .enabled = 1,
270 },
271 .initial_state = PM_SUSPEND_MEM,
272 .always_on = 1,
273 .boot_on = 1,
274 },
275};
276
277/* DDR RAM */
278static struct regulator_init_data sw2a_data = {
279 .constraints = {
280 .name = "SW2A",
281 .min_uV = 1800000,
282 .max_uV = 1800000,
283 .valid_modes_mask = REGULATOR_MODE_NORMAL,
284 .state_mem = {
285 .uV = 1800000,
286 .mode = REGULATOR_MODE_NORMAL,
287 .enabled = 1,
288 },
289 .state_disk = {
290 .mode = REGULATOR_MODE_NORMAL,
291 .enabled = 0,
292 },
293 .always_on = 1,
294 .boot_on = 1,
295 .initial_state = PM_SUSPEND_MEM,
296 },
297};
298
299static struct regulator_init_data ldo1_data = {
300 .constraints = {
301 .name = "VCAM/VMMC1/VMMC2",
302 .min_uV = 2800000,
303 .max_uV = 2800000,
304 .valid_modes_mask = REGULATOR_MODE_NORMAL,
305 .apply_uV = 1,
306 },
307};
308
309static struct regulator_consumer_supply ldo2_consumers[] = {
310 {
311 .supply = "AVDD",
312 },
313 {
314 .supply = "HPVDD",
315 },
316};
317
318/* CODEC and SIM */
319static struct regulator_init_data ldo2_data = {
320 .constraints = {
321 .name = "VESIM/VSIM/AVDD",
322 .min_uV = 3300000,
323 .max_uV = 3300000,
324 .valid_modes_mask = REGULATOR_MODE_NORMAL,
325 .apply_uV = 1,
326 },
327 .num_consumer_supplies = ARRAY_SIZE(ldo2_consumers),
328 .consumer_supplies = ldo2_consumers,
329};
330
331/* General */
332static struct regulator_init_data vdig_data = {
333 .constraints = {
334 .name = "VDIG",
335 .min_uV = 1500000,
336 .max_uV = 1500000,
337 .valid_modes_mask = REGULATOR_MODE_NORMAL,
338 .apply_uV = 1,
339 .always_on = 1,
340 .boot_on = 1,
341 },
342};
343
344/* Tranceivers */
345static struct regulator_init_data ldo4_data = {
346 .constraints = {
347 .name = "VRF1/CVDD_2.775",
348 .min_uV = 2500000,
349 .max_uV = 2500000,
350 .valid_modes_mask = REGULATOR_MODE_NORMAL,
351 .apply_uV = 1,
352 .always_on = 1,
353 .boot_on = 1,
354 },
355};
356
357static struct wm8350_led_platform_data wm8350_led_data = {
358 .name = "wm8350:white",
359 .default_trigger = "heartbeat",
360 .max_uA = 27899,
361};
362
363static struct wm8350_audio_platform_data imx32ads_wm8350_setup = {
364 .vmid_discharge_msecs = 1000,
365 .drain_msecs = 30,
366 .cap_discharge_msecs = 700,
367 .vmid_charge_msecs = 700,
368 .vmid_s_curve = WM8350_S_CURVE_SLOW,
369 .dis_out4 = WM8350_DISCHARGE_SLOW,
370 .dis_out3 = WM8350_DISCHARGE_SLOW,
371 .dis_out2 = WM8350_DISCHARGE_SLOW,
372 .dis_out1 = WM8350_DISCHARGE_SLOW,
373 .vroi_out4 = WM8350_TIE_OFF_500R,
374 .vroi_out3 = WM8350_TIE_OFF_500R,
375 .vroi_out2 = WM8350_TIE_OFF_500R,
376 .vroi_out1 = WM8350_TIE_OFF_500R,
377 .vroi_enable = 0,
378 .codec_current_on = WM8350_CODEC_ISEL_1_0,
379 .codec_current_standby = WM8350_CODEC_ISEL_0_5,
380 .codec_current_charge = WM8350_CODEC_ISEL_1_5,
381};
382
383static int mx31_wm8350_init(struct wm8350 *wm8350)
384{
385 int i;
386
387 wm8350_gpio_config(wm8350, 0, WM8350_GPIO_DIR_IN,
388 WM8350_GPIO0_PWR_ON_IN, WM8350_GPIO_ACTIVE_LOW,
389 WM8350_GPIO_PULL_UP, WM8350_GPIO_INVERT_OFF,
390 WM8350_GPIO_DEBOUNCE_ON);
391
392 wm8350_gpio_config(wm8350, 3, WM8350_GPIO_DIR_IN,
393 WM8350_GPIO3_PWR_OFF_IN, WM8350_GPIO_ACTIVE_HIGH,
394 WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
395 WM8350_GPIO_DEBOUNCE_ON);
396
397 wm8350_gpio_config(wm8350, 4, WM8350_GPIO_DIR_IN,
398 WM8350_GPIO4_MR_IN, WM8350_GPIO_ACTIVE_HIGH,
399 WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
400 WM8350_GPIO_DEBOUNCE_OFF);
401
402 wm8350_gpio_config(wm8350, 7, WM8350_GPIO_DIR_IN,
403 WM8350_GPIO7_HIBERNATE_IN, WM8350_GPIO_ACTIVE_HIGH,
404 WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
405 WM8350_GPIO_DEBOUNCE_OFF);
406
407 wm8350_gpio_config(wm8350, 6, WM8350_GPIO_DIR_OUT,
408 WM8350_GPIO6_SDOUT_OUT, WM8350_GPIO_ACTIVE_HIGH,
409 WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
410 WM8350_GPIO_DEBOUNCE_OFF);
411
412 wm8350_gpio_config(wm8350, 8, WM8350_GPIO_DIR_OUT,
413 WM8350_GPIO8_VCC_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
414 WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
415 WM8350_GPIO_DEBOUNCE_OFF);
416
417 wm8350_gpio_config(wm8350, 9, WM8350_GPIO_DIR_OUT,
418 WM8350_GPIO9_BATT_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
419 WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
420 WM8350_GPIO_DEBOUNCE_OFF);
421
422 /* Fix up for our own supplies. */
423 for (i = 0; i < ARRAY_SIZE(ldo2_consumers); i++)
424 ldo2_consumers[i].dev = wm8350->dev;
425
426 wm8350_register_regulator(wm8350, WM8350_DCDC_1, &sw1a_data);
427 wm8350_register_regulator(wm8350, WM8350_DCDC_3, &viohi_data);
428 wm8350_register_regulator(wm8350, WM8350_DCDC_4, &violo_data);
429 wm8350_register_regulator(wm8350, WM8350_DCDC_6, &sw2a_data);
430 wm8350_register_regulator(wm8350, WM8350_LDO_1, &ldo1_data);
431 wm8350_register_regulator(wm8350, WM8350_LDO_2, &ldo2_data);
432 wm8350_register_regulator(wm8350, WM8350_LDO_3, &vdig_data);
433 wm8350_register_regulator(wm8350, WM8350_LDO_4, &ldo4_data);
434
435 /* LEDs */
436 wm8350_dcdc_set_slot(wm8350, WM8350_DCDC_5, 1, 1,
437 WM8350_DC5_ERRACT_SHUTDOWN_CONV);
438 wm8350_isink_set_flash(wm8350, WM8350_ISINK_A,
439 WM8350_ISINK_FLASH_DISABLE,
440 WM8350_ISINK_FLASH_TRIG_BIT,
441 WM8350_ISINK_FLASH_DUR_32MS,
442 WM8350_ISINK_FLASH_ON_INSTANT,
443 WM8350_ISINK_FLASH_OFF_INSTANT,
444 WM8350_ISINK_FLASH_MODE_EN);
445 wm8350_dcdc25_set_mode(wm8350, WM8350_DCDC_5,
446 WM8350_ISINK_MODE_BOOST,
447 WM8350_ISINK_ILIM_NORMAL,
448 WM8350_DC5_RMP_20V,
449 WM8350_DC5_FBSRC_ISINKA);
450 wm8350_register_led(wm8350, 0, WM8350_DCDC_5, WM8350_ISINK_A,
451 &wm8350_led_data);
452
453 wm8350->codec.platform_data = &imx32ads_wm8350_setup;
454
Mark Brown0ac402f2009-04-13 13:05:28 +0100455 regulator_has_full_constraints();
456
Mark Brownfe7316b2009-01-15 16:14:30 +0000457 return 0;
458}
459
460static struct wm8350_platform_data __initdata mx31_wm8350_pdata = {
461 .init = mx31_wm8350_init,
462};
463#endif
464
465#if defined(CONFIG_I2C_IMX) || defined(CONFIG_I2C_IMX_MODULE)
466static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = {
467#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
468 {
469 I2C_BOARD_INFO("wm8350", 0x1a),
470 .platform_data = &mx31_wm8350_pdata,
471 .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
472 },
473#endif
474};
475
476static void mxc_init_i2c(void)
477{
478 i2c_register_board_info(1, mx31ads_i2c1_devices,
479 ARRAY_SIZE(mx31ads_i2c1_devices));
480
481 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1));
482 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1));
483
484 mxc_register_device(&mxc_i2c_device1, NULL);
485}
486#else
487static void mxc_init_i2c(void)
488{
489}
490#endif
491
Quinn Jensen52c543f2007-07-09 22:06:53 +0100492/*!
493 * This structure defines static mappings for the i.MX31ADS board.
494 */
495static struct map_desc mx31ads_io_desc[] __initdata = {
496 {
Quinn Jensen52c543f2007-07-09 22:06:53 +0100497 .virtual = SPBA0_BASE_ADDR_VIRT,
498 .pfn = __phys_to_pfn(SPBA0_BASE_ADDR),
499 .length = SPBA0_SIZE,
Russell King9b727ab2008-09-07 12:45:01 +0100500 .type = MT_DEVICE_NONSHARED
Quinn Jensen52c543f2007-07-09 22:06:53 +0100501 }, {
Quinn Jensen52c543f2007-07-09 22:06:53 +0100502 .virtual = CS4_BASE_ADDR_VIRT,
503 .pfn = __phys_to_pfn(CS4_BASE_ADDR),
504 .length = CS4_SIZE / 2,
505 .type = MT_DEVICE
506 },
507};
508
509/*!
510 * Set up static virtual mappings.
511 */
Mark Brown8b785b92009-01-15 16:14:29 +0000512static void __init mx31ads_map_io(void)
Quinn Jensen52c543f2007-07-09 22:06:53 +0100513{
Sascha Hauercd4a05f2009-04-02 22:32:10 +0200514 mx31_map_io();
Quinn Jensen52c543f2007-07-09 22:06:53 +0100515 iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc));
516}
517
Mark Brown8b785b92009-01-15 16:14:29 +0000518static void __init mx31ads_init_irq(void)
Gilles Chanteperdrixd7568f72008-09-09 10:19:42 +0200519{
520 mxc_init_irq();
521 mx31ads_init_expio();
522}
523
Quinn Jensen52c543f2007-07-09 22:06:53 +0100524/*!
525 * Board specific initialization.
526 */
527static void __init mxc_board_init(void)
528{
529 mxc_init_extuart();
Gilles Chanteperdrix07417942008-09-09 10:19:41 +0200530 mxc_init_imx_uart();
Mark Brownfe7316b2009-01-15 16:14:30 +0000531 mxc_init_i2c();
Quinn Jensen52c543f2007-07-09 22:06:53 +0100532}
533
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200534static void __init mx31ads_timer_init(void)
535{
Sascha Hauer30c730f2009-02-16 14:36:49 +0100536 mx31_clocks_init(26000000);
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200537}
538
Mark Brown8b785b92009-01-15 16:14:29 +0000539static struct sys_timer mx31ads_timer = {
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200540 .init = mx31ads_timer_init,
541};
542
Quinn Jensen52c543f2007-07-09 22:06:53 +0100543/*
544 * The following uses standard kernel macros defined in arch.h in order to
545 * initialize __mach_desc_MX31ADS data structure.
546 */
547MACHINE_START(MX31ADS, "Freescale MX31ADS")
548 /* Maintainer: Freescale Semiconductor, Inc. */
549 .phys_io = AIPS1_BASE_ADDR,
550 .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
551 .boot_params = PHYS_OFFSET + 0x100,
552 .map_io = mx31ads_map_io,
Gilles Chanteperdrixd7568f72008-09-09 10:19:42 +0200553 .init_irq = mx31ads_init_irq,
Quinn Jensen52c543f2007-07-09 22:06:53 +0100554 .init_machine = mxc_board_init,
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200555 .timer = &mx31ads_timer,
Quinn Jensen52c543f2007-07-09 22:06:53 +0100556MACHINE_END