Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. |
| 3 | */ |
| 4 | |
| 5 | /* |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | */ |
| 10 | |
| 11 | #ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__ |
| 12 | #define __ASM_ARCH_MXC_BOARD_MX31ADS_H__ |
| 13 | |
Mark Brown | 4d5f9cd | 2009-01-15 16:14:28 +0000 | [diff] [blame] | 14 | #include <mach/hardware.h> |
| 15 | |
Robert Schwebel | f304fc4 | 2008-03-28 10:59:08 +0100 | [diff] [blame] | 16 | /* Base address of PBC controller */ |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 17 | #define PBC_BASE_ADDRESS IO_ADDRESS(CS4_BASE_ADDR) |
| 18 | /* Offsets for the PBC Controller register */ |
Robert Schwebel | f304fc4 | 2008-03-28 10:59:08 +0100 | [diff] [blame] | 19 | |
| 20 | /* PBC Board status register offset */ |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 21 | #define PBC_BSTAT 0x000002 |
Robert Schwebel | f304fc4 | 2008-03-28 10:59:08 +0100 | [diff] [blame] | 22 | |
| 23 | /* PBC Board control register 1 set address */ |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 24 | #define PBC_BCTRL1_SET 0x000004 |
Robert Schwebel | f304fc4 | 2008-03-28 10:59:08 +0100 | [diff] [blame] | 25 | |
| 26 | /* PBC Board control register 1 clear address */ |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 27 | #define PBC_BCTRL1_CLEAR 0x000006 |
Robert Schwebel | f304fc4 | 2008-03-28 10:59:08 +0100 | [diff] [blame] | 28 | |
| 29 | /* PBC Board control register 2 set address */ |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 30 | #define PBC_BCTRL2_SET 0x000008 |
Robert Schwebel | f304fc4 | 2008-03-28 10:59:08 +0100 | [diff] [blame] | 31 | |
| 32 | /* PBC Board control register 2 clear address */ |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 33 | #define PBC_BCTRL2_CLEAR 0x00000A |
Robert Schwebel | f304fc4 | 2008-03-28 10:59:08 +0100 | [diff] [blame] | 34 | |
| 35 | /* PBC Board control register 3 set address */ |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 36 | #define PBC_BCTRL3_SET 0x00000C |
Robert Schwebel | f304fc4 | 2008-03-28 10:59:08 +0100 | [diff] [blame] | 37 | |
| 38 | /* PBC Board control register 3 clear address */ |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 39 | #define PBC_BCTRL3_CLEAR 0x00000E |
Robert Schwebel | f304fc4 | 2008-03-28 10:59:08 +0100 | [diff] [blame] | 40 | |
| 41 | /* PBC Board control register 4 set address */ |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 42 | #define PBC_BCTRL4_SET 0x000010 |
Robert Schwebel | f304fc4 | 2008-03-28 10:59:08 +0100 | [diff] [blame] | 43 | |
| 44 | /* PBC Board control register 4 clear address */ |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 45 | #define PBC_BCTRL4_CLEAR 0x000012 |
Robert Schwebel | f304fc4 | 2008-03-28 10:59:08 +0100 | [diff] [blame] | 46 | |
| 47 | /* PBC Board status register 1 */ |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 48 | #define PBC_BSTAT1 0x000014 |
Robert Schwebel | f304fc4 | 2008-03-28 10:59:08 +0100 | [diff] [blame] | 49 | |
| 50 | /* PBC Board interrupt status register */ |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 51 | #define PBC_INTSTATUS 0x000016 |
Robert Schwebel | f304fc4 | 2008-03-28 10:59:08 +0100 | [diff] [blame] | 52 | |
| 53 | /* PBC Board interrupt current status register */ |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 54 | #define PBC_INTCURR_STATUS 0x000018 |
Robert Schwebel | f304fc4 | 2008-03-28 10:59:08 +0100 | [diff] [blame] | 55 | |
| 56 | /* PBC Interrupt mask register set address */ |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 57 | #define PBC_INTMASK_SET 0x00001A |
Robert Schwebel | f304fc4 | 2008-03-28 10:59:08 +0100 | [diff] [blame] | 58 | |
| 59 | /* PBC Interrupt mask register clear address */ |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 60 | #define PBC_INTMASK_CLEAR 0x00001C |
| 61 | |
Robert Schwebel | f304fc4 | 2008-03-28 10:59:08 +0100 | [diff] [blame] | 62 | /* External UART A */ |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 63 | #define PBC_SC16C652_UARTA 0x010000 |
Robert Schwebel | f304fc4 | 2008-03-28 10:59:08 +0100 | [diff] [blame] | 64 | |
| 65 | /* External UART B */ |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 66 | #define PBC_SC16C652_UARTB 0x010010 |
Robert Schwebel | f304fc4 | 2008-03-28 10:59:08 +0100 | [diff] [blame] | 67 | |
| 68 | /* Ethernet Controller IO base address */ |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 69 | #define PBC_CS8900A_IOBASE 0x020000 |
Robert Schwebel | f304fc4 | 2008-03-28 10:59:08 +0100 | [diff] [blame] | 70 | |
| 71 | /* Ethernet Controller Memory base address */ |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 72 | #define PBC_CS8900A_MEMBASE 0x021000 |
Robert Schwebel | f304fc4 | 2008-03-28 10:59:08 +0100 | [diff] [blame] | 73 | |
| 74 | /* Ethernet Controller DMA base address */ |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 75 | #define PBC_CS8900A_DMABASE 0x022000 |
Robert Schwebel | f304fc4 | 2008-03-28 10:59:08 +0100 | [diff] [blame] | 76 | |
| 77 | /* External chip select 0 */ |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 78 | #define PBC_XCS0 0x040000 |
Robert Schwebel | f304fc4 | 2008-03-28 10:59:08 +0100 | [diff] [blame] | 79 | |
| 80 | /* LCD Display enable */ |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 81 | #define PBC_LCD_EN_B 0x060000 |
Robert Schwebel | f304fc4 | 2008-03-28 10:59:08 +0100 | [diff] [blame] | 82 | |
| 83 | /* Code test debug enable */ |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 84 | #define PBC_CODE_B 0x070000 |
Robert Schwebel | f304fc4 | 2008-03-28 10:59:08 +0100 | [diff] [blame] | 85 | |
| 86 | /* PSRAM memory select */ |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 87 | #define PBC_PSRAM_B 0x5000000 |
| 88 | |
| 89 | #define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS) |
| 90 | #define PBC_INTCURR_STATUS_REG (PBC_INTCURR_STATUS + PBC_BASE_ADDRESS) |
| 91 | #define PBC_INTMASK_SET_REG (PBC_INTMASK_SET + PBC_BASE_ADDRESS) |
| 92 | #define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS) |
| 93 | #define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4) |
| 94 | |
Sascha Hauer | 9d631b8 | 2008-12-18 11:08:55 +0100 | [diff] [blame] | 95 | #define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START) |
Gilles Chanteperdrix | d7568f7 | 2008-09-09 10:19:42 +0200 | [diff] [blame] | 96 | #define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE) |
| 97 | |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 98 | #define EXPIO_INT_LOW_BAT (MXC_EXP_IO_BASE + 0) |
| 99 | #define EXPIO_INT_PB_IRQ (MXC_EXP_IO_BASE + 1) |
| 100 | #define EXPIO_INT_OTG_FS_OVR (MXC_EXP_IO_BASE + 2) |
| 101 | #define EXPIO_INT_FSH_OVR (MXC_EXP_IO_BASE + 3) |
| 102 | #define EXPIO_INT_RES4 (MXC_EXP_IO_BASE + 4) |
| 103 | #define EXPIO_INT_RES5 (MXC_EXP_IO_BASE + 5) |
| 104 | #define EXPIO_INT_RES6 (MXC_EXP_IO_BASE + 6) |
| 105 | #define EXPIO_INT_RES7 (MXC_EXP_IO_BASE + 7) |
| 106 | #define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8) |
| 107 | #define EXPIO_INT_OTG_FS_INT (MXC_EXP_IO_BASE + 9) |
| 108 | #define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10) |
| 109 | #define EXPIO_INT_XUART_INTB (MXC_EXP_IO_BASE + 11) |
| 110 | #define EXPIO_INT_SYNTH_IRQ (MXC_EXP_IO_BASE + 12) |
| 111 | #define EXPIO_INT_CE_INT1 (MXC_EXP_IO_BASE + 13) |
| 112 | #define EXPIO_INT_CE_INT2 (MXC_EXP_IO_BASE + 14) |
| 113 | #define EXPIO_INT_RES15 (MXC_EXP_IO_BASE + 15) |
| 114 | |
| 115 | #define MXC_MAX_EXP_IO_LINES 16 |
| 116 | |
Magnus Lilja | c133261 | 2009-04-14 22:00:06 +0200 | [diff] [blame] | 117 | /* mandatory for CONFIG_DEBUG_LL */ |
Sascha Hauer | 4bc2565 | 2008-07-05 10:02:51 +0200 | [diff] [blame] | 118 | |
| 119 | #define MXC_LL_UART_PADDR UART1_BASE_ADDR |
| 120 | #define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) |
| 121 | |
Robert Schwebel | f304fc4 | 2008-03-28 10:59:08 +0100 | [diff] [blame] | 122 | #endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */ |