blob: 7cd84547658fa1434368ea69853ac7166bb6f2a2 [file] [log] [blame]
Sascha Hauerbca6ef12009-04-01 11:11:48 +02001/*
2 * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
3 * <armlinux@phytec.de>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#ifndef __MACH_IOMUX_V3_H__
21#define __MACH_IOMUX_V3_H__
22
23/*
24 * build IOMUX_PAD structure
25 *
26 * This iomux scheme is based around pads, which are the physical balls
27 * on the processor.
28 *
29 * - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls
30 * things like driving strength and pullup/pulldown.
31 * - Each pad can have but not necessarily does have an output routing register
32 * (IOMUXC_SW_MUX_CTL_PAD_x).
33 * - Each pad can have but not necessarily does have an input routing register
34 * (IOMUXC_x_SELECT_INPUT)
35 *
36 * The three register sets do not have a fixed offset to each other,
37 * hence we order this table by pad control registers (which all pads
38 * have) and put the optional i/o routing registers into additional
39 * fields.
40 *
41 * The naming convention for the pad modes is MX35_PAD_<padname>__<padmode>
42 * If <padname> or <padmode> refers to a GPIO, it is named
43 * GPIO_<unit>_<num>
44 *
45 */
46
47struct pad_desc {
48 unsigned mux_ctrl_ofs:12; /* IOMUXC_SW_MUX_CTL_PAD offset */
49 unsigned mux_mode:8;
50 unsigned pad_ctrl_ofs:12; /* IOMUXC_SW_PAD_CTRL offset */
51#define NO_PAD_CTRL (1 << 16)
52 unsigned pad_ctrl:17;
53 unsigned select_input_ofs:12; /* IOMUXC_SELECT_INPUT offset */
54 unsigned select_input:3;
55};
56
57#define IOMUX_PAD(_pad_ctrl_ofs, _mux_ctrl_ofs, _mux_mode, _select_input_ofs, \
58 _select_input, _pad_ctrl) \
59 { \
60 .mux_ctrl_ofs = _mux_ctrl_ofs, \
61 .mux_mode = _mux_mode, \
62 .pad_ctrl_ofs = _pad_ctrl_ofs, \
63 .pad_ctrl = _pad_ctrl, \
64 .select_input_ofs = _select_input_ofs, \
65 .select_input = _select_input, \
66 }
67
68/*
69 * Use to set PAD control
70 */
71#define PAD_CTL_DRIVE_VOLTAGE_3_3_V 0
72#define PAD_CTL_DRIVE_VOLTAGE_1_8_V 1
73
74#define PAD_CTL_NO_HYSTERESIS 0
75#define PAD_CTL_HYSTERESIS 1
76
77#define PAD_CTL_PULL_DISABLED 0x0
78#define PAD_CTL_PULL_KEEPER 0xa
79#define PAD_CTL_PULL_DOWN_100K 0xc
80#define PAD_CTL_PULL_UP_47K 0xd
81#define PAD_CTL_PULL_UP_100K 0xe
82#define PAD_CTL_PULL_UP_22K 0xf
83
84#define PAD_CTL_OUTPUT_CMOS 0
85#define PAD_CTL_OUTPUT_OPEN_DRAIN 1
86
87#define PAD_CTL_DRIVE_STRENGTH_NORM 0
88#define PAD_CTL_DRIVE_STRENGTH_HIGH 1
89#define PAD_CTL_DRIVE_STRENGTH_MAX 2
90
91#define PAD_CTL_SLEW_RATE_SLOW 0
92#define PAD_CTL_SLEW_RATE_FAST 1
93
94/*
95 * setups a single pad:
96 * - reserves the pad so that it is not claimed by another driver
97 * - setups the iomux according to the configuration
98 */
99int mxc_iomux_v3_setup_pad(struct pad_desc *pad);
100
101/*
102 * setups mutliple pads
103 * convenient way to call the above function with tables
104 */
105int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count);
106
107/*
108 * releases a single pad:
109 * - make it available for a future use by another driver
110 * - DOES NOT reconfigure the IOMUX in its reset state
111 */
112void mxc_iomux_v3_release_pad(struct pad_desc *pad);
113
114/*
115 * releases multiple pads
116 * convenvient way to call the above function with tables
117 */
118void mxc_iomux_v3_release_multiple_pads(struct pad_desc *pad_list, int count);
119
120#endif /* __MACH_IOMUX_V3_H__*/
121