Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1 | /* |
Mike Frysinger | 287050f | 2007-07-24 15:23:20 +0800 | [diff] [blame] | 2 | * File: include/asm-blackfin/mach-bf561/anomaly.h |
| 3 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 4 | * |
Mike Frysinger | c18e99c | 2009-03-04 17:36:49 +0800 | [diff] [blame] | 5 | * Copyright (C) 2004-2009 Analog Devices Inc. |
Mike Frysinger | 287050f | 2007-07-24 15:23:20 +0800 | [diff] [blame] | 6 | * Licensed under the GPL-2 or later. |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 7 | */ |
| 8 | |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 9 | /* This file should be up to date with: |
Mike Frysinger | 6651ece | 2009-01-07 23:14:38 +0800 | [diff] [blame] | 10 | * - Revision Q, 11/07/2008; ADSP-BF561 Blackfin Processor Anomaly List |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 11 | */ |
| 12 | |
| 13 | #ifndef _MACH_ANOMALY_H_ |
| 14 | #define _MACH_ANOMALY_H_ |
| 15 | |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 16 | /* We do not support 0.1, 0.2, or 0.4 silicon - sorry */ |
| 17 | #if __SILICON_REVISION__ < 3 || __SILICON_REVISION__ == 4 |
Mike Frysinger | 7cc1c4b | 2007-12-24 20:05:09 +0800 | [diff] [blame] | 18 | # error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4 |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 19 | #endif |
| 20 | |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 21 | /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 22 | #define ANOMALY_05000074 (1) |
| 23 | /* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */ |
| 24 | #define ANOMALY_05000099 (__SILICON_REVISION__ < 5) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 25 | /* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 26 | #define ANOMALY_05000116 (__SILICON_REVISION__ < 3) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 27 | /* TESTSET Instructions Restricted to 32-Bit Aligned Memory Locations */ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 28 | #define ANOMALY_05000120 (1) |
| 29 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ |
| 30 | #define ANOMALY_05000122 (1) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 31 | /* Erroneous Exception when Enabling Cache */ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 32 | #define ANOMALY_05000125 (__SILICON_REVISION__ < 3) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 33 | /* SIGNBITS Instruction Not Functional under Certain Conditions */ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 34 | #define ANOMALY_05000127 (1) |
| 35 | /* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */ |
| 36 | #define ANOMALY_05000134 (__SILICON_REVISION__ < 3) |
| 37 | /* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */ |
| 38 | #define ANOMALY_05000135 (__SILICON_REVISION__ < 3) |
| 39 | /* Stall in multi-unit DMA operations */ |
| 40 | #define ANOMALY_05000136 (__SILICON_REVISION__ < 3) |
| 41 | /* Allowing the SPORT RX FIFO to fill will cause an overflow */ |
| 42 | #define ANOMALY_05000140 (__SILICON_REVISION__ < 3) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 43 | /* Infinite Stall may occur with a particular sequence of consecutive dual dag events */ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 44 | #define ANOMALY_05000141 (__SILICON_REVISION__ < 3) |
| 45 | /* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */ |
| 46 | #define ANOMALY_05000142 (__SILICON_REVISION__ < 3) |
| 47 | /* DMA and TESTSET conflict when both are accessing external memory */ |
| 48 | #define ANOMALY_05000144 (__SILICON_REVISION__ < 3) |
| 49 | /* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */ |
| 50 | #define ANOMALY_05000145 (__SILICON_REVISION__ < 3) |
| 51 | /* MDMA may lose the first few words of a descriptor chain */ |
| 52 | #define ANOMALY_05000146 (__SILICON_REVISION__ < 3) |
| 53 | /* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */ |
| 54 | #define ANOMALY_05000147 (__SILICON_REVISION__ < 3) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 55 | /* IMDMA S1/D1 Channel May Stall */ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 56 | #define ANOMALY_05000149 (1) |
| 57 | /* DMA engine may lose data due to incorrect handshaking */ |
| 58 | #define ANOMALY_05000150 (__SILICON_REVISION__ < 3) |
| 59 | /* DMA stalls when all three controllers read data from the same source */ |
| 60 | #define ANOMALY_05000151 (__SILICON_REVISION__ < 3) |
| 61 | /* Execution stall when executing in L2 and doing external accesses */ |
| 62 | #define ANOMALY_05000152 (__SILICON_REVISION__ < 3) |
| 63 | /* Frame Delay in SPORT Multichannel Mode */ |
| 64 | #define ANOMALY_05000153 (__SILICON_REVISION__ < 3) |
| 65 | /* SPORT TFS signal stays active in multichannel mode outside of valid channels */ |
| 66 | #define ANOMALY_05000154 (__SILICON_REVISION__ < 3) |
| 67 | /* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */ |
| 68 | #define ANOMALY_05000156 (__SILICON_REVISION__ < 4) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 69 | /* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 70 | #define ANOMALY_05000157 (__SILICON_REVISION__ < 3) |
| 71 | /* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */ |
| 72 | #define ANOMALY_05000159 (__SILICON_REVISION__ < 3) |
| 73 | /* A read from external memory may return a wrong value with data cache enabled */ |
| 74 | #define ANOMALY_05000160 (__SILICON_REVISION__ < 3) |
| 75 | /* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */ |
| 76 | #define ANOMALY_05000161 (__SILICON_REVISION__ < 3) |
| 77 | /* DMEM_CONTROL<12> is not set on Reset */ |
| 78 | #define ANOMALY_05000162 (__SILICON_REVISION__ < 3) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 79 | /* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 80 | #define ANOMALY_05000163 (__SILICON_REVISION__ < 3) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 81 | /* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 82 | #define ANOMALY_05000166 (1) |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 83 | /* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 84 | #define ANOMALY_05000167 (1) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 85 | /* Undefined Behavior when Power-Up Sequence Is Issued to SDRAM during Auto-Refresh */ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 86 | #define ANOMALY_05000168 (__SILICON_REVISION__ < 5) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 87 | /* DATA CPLB Page Miss Can Result in Lost Write-Through Data Cache Writes */ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 88 | #define ANOMALY_05000169 (__SILICON_REVISION__ < 5) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 89 | /* Boot-ROM Modifies SICA_IWRx Wakeup Registers */ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 90 | #define ANOMALY_05000171 (__SILICON_REVISION__ < 5) |
| 91 | /* DSPID register values incorrect */ |
| 92 | #define ANOMALY_05000172 (__SILICON_REVISION__ < 3) |
| 93 | /* DMA vs Core accesses to external memory */ |
| 94 | #define ANOMALY_05000173 (__SILICON_REVISION__ < 3) |
| 95 | /* Cache Fill Buffer Data lost */ |
| 96 | #define ANOMALY_05000174 (__SILICON_REVISION__ < 5) |
| 97 | /* Overlapping Sequencer and Memory Stalls */ |
| 98 | #define ANOMALY_05000175 (__SILICON_REVISION__ < 5) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 99 | /* Overflow Bit Asserted when Multiplication of -1 by -1 Followed by Accumulator Saturation */ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 100 | #define ANOMALY_05000176 (__SILICON_REVISION__ < 5) |
| 101 | /* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */ |
| 102 | #define ANOMALY_05000179 (__SILICON_REVISION__ < 5) |
| 103 | /* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ |
| 104 | #define ANOMALY_05000180 (1) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 105 | /* Disabling the PPI Resets the PPI Configuration Registers */ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 106 | #define ANOMALY_05000181 (__SILICON_REVISION__ < 5) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 107 | /* Internal Memory DMA Does Not Operate at Full Speed */ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 108 | #define ANOMALY_05000182 (1) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 109 | /* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 110 | #define ANOMALY_05000184 (__SILICON_REVISION__ < 5) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 111 | /* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 112 | #define ANOMALY_05000185 (__SILICON_REVISION__ < 5) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 113 | /* Upper PPI Pins Driven when PPI Packing Enabled and Data Length >8 Bits */ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 114 | #define ANOMALY_05000186 (__SILICON_REVISION__ < 5) |
| 115 | /* IMDMA Corrupted Data after a Halt */ |
| 116 | #define ANOMALY_05000187 (1) |
| 117 | /* IMDMA Restrictions on Descriptor and Buffer Placement in Memory */ |
| 118 | #define ANOMALY_05000188 (__SILICON_REVISION__ < 5) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 119 | /* False Protection Exceptions when Speculative Fetch Is Cancelled */ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 120 | #define ANOMALY_05000189 (__SILICON_REVISION__ < 5) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 121 | /* PPI Not Functional at Core Voltage < 1Volt */ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 122 | #define ANOMALY_05000190 (1) |
| 123 | /* PPI does not invert the Driving PPICLK edge in Transmit Modes */ |
| 124 | #define ANOMALY_05000191 (__SILICON_REVISION__ < 3) |
| 125 | /* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */ |
| 126 | #define ANOMALY_05000193 (__SILICON_REVISION__ < 5) |
| 127 | /* Restarting SPORT in Specific Modes May Cause Data Corruption */ |
| 128 | #define ANOMALY_05000194 (__SILICON_REVISION__ < 5) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 129 | /* Failing MMR Accesses when Preceding Memory Read Stalls */ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 130 | #define ANOMALY_05000198 (__SILICON_REVISION__ < 5) |
| 131 | /* Current DMA Address Shows Wrong Value During Carry Fix */ |
| 132 | #define ANOMALY_05000199 (__SILICON_REVISION__ < 5) |
| 133 | /* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */ |
| 134 | #define ANOMALY_05000200 (__SILICON_REVISION__ < 5) |
| 135 | /* Possible Infinite Stall with Specific Dual-DAG Situation */ |
| 136 | #define ANOMALY_05000202 (__SILICON_REVISION__ < 5) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 137 | /* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 138 | #define ANOMALY_05000204 (__SILICON_REVISION__ < 5) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 139 | /* Specific Sequence that Can Cause DMA Error or DMA Stopping */ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 140 | #define ANOMALY_05000205 (__SILICON_REVISION__ < 5) |
| 141 | /* Recovery from "Brown-Out" Condition */ |
| 142 | #define ANOMALY_05000207 (__SILICON_REVISION__ < 5) |
| 143 | /* VSTAT Status Bit in PLL_STAT Register Is Not Functional */ |
| 144 | #define ANOMALY_05000208 (1) |
| 145 | /* Speed Path in Computational Unit Affects Certain Instructions */ |
| 146 | #define ANOMALY_05000209 (__SILICON_REVISION__ < 5) |
| 147 | /* UART TX Interrupt Masked Erroneously */ |
| 148 | #define ANOMALY_05000215 (__SILICON_REVISION__ < 5) |
| 149 | /* NMI Event at Boot Time Results in Unpredictable State */ |
| 150 | #define ANOMALY_05000219 (__SILICON_REVISION__ < 5) |
| 151 | /* Data Corruption with Cached External Memory and Non-Cached On-Chip L2 Memory */ |
| 152 | #define ANOMALY_05000220 (__SILICON_REVISION__ < 5) |
| 153 | /* Incorrect Pulse-Width of UART Start Bit */ |
| 154 | #define ANOMALY_05000225 (__SILICON_REVISION__ < 5) |
| 155 | /* Scratchpad Memory Bank Reads May Return Incorrect Data */ |
| 156 | #define ANOMALY_05000227 (__SILICON_REVISION__ < 5) |
| 157 | /* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */ |
| 158 | #define ANOMALY_05000230 (__SILICON_REVISION__ < 5) |
| 159 | /* UART STB Bit Incorrectly Affects Receiver Setting */ |
| 160 | #define ANOMALY_05000231 (__SILICON_REVISION__ < 5) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 161 | /* SPORT Data Transmit Lines Are Incorrectly Driven in Multichannel Mode */ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 162 | #define ANOMALY_05000232 (__SILICON_REVISION__ < 5) |
| 163 | /* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */ |
| 164 | #define ANOMALY_05000242 (__SILICON_REVISION__ < 5) |
| 165 | /* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ |
| 166 | #define ANOMALY_05000244 (__SILICON_REVISION__ < 5) |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 167 | /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 168 | #define ANOMALY_05000245 (__SILICON_REVISION__ < 5) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 169 | /* TESTSET Operation Forces Stall on the Other Core */ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 170 | #define ANOMALY_05000248 (__SILICON_REVISION__ < 5) |
| 171 | /* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ |
| 172 | #define ANOMALY_05000250 (__SILICON_REVISION__ > 2 && __SILICON_REVISION__ < 5) |
| 173 | /* Exception Not Generated for MMR Accesses in Reserved Region */ |
| 174 | #define ANOMALY_05000251 (__SILICON_REVISION__ < 5) |
| 175 | /* Maximum External Clock Speed for Timers */ |
| 176 | #define ANOMALY_05000253 (__SILICON_REVISION__ < 5) |
| 177 | /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ |
| 178 | #define ANOMALY_05000254 (__SILICON_REVISION__ > 3) |
| 179 | /* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */ |
| 180 | #define ANOMALY_05000257 (__SILICON_REVISION__ < 5) |
| 181 | /* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */ |
| 182 | #define ANOMALY_05000258 (__SILICON_REVISION__ < 5) |
| 183 | /* ICPLB_STATUS MMR Register May Be Corrupted */ |
| 184 | #define ANOMALY_05000260 (__SILICON_REVISION__ < 5) |
| 185 | /* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */ |
| 186 | #define ANOMALY_05000261 (__SILICON_REVISION__ < 5) |
| 187 | /* Stores To Data Cache May Be Lost */ |
| 188 | #define ANOMALY_05000262 (__SILICON_REVISION__ < 5) |
| 189 | /* Hardware Loop Corrupted When Taking an ICPLB Exception */ |
| 190 | #define ANOMALY_05000263 (__SILICON_REVISION__ < 5) |
| 191 | /* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */ |
| 192 | #define ANOMALY_05000264 (__SILICON_REVISION__ < 5) |
| 193 | /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ |
| 194 | #define ANOMALY_05000265 (__SILICON_REVISION__ < 5) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 195 | /* IMDMA Destination IRQ Status Must Be Read Prior to Using IMDMA */ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 196 | #define ANOMALY_05000266 (__SILICON_REVISION__ > 3) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 197 | /* IMDMA May Corrupt Data under Certain Conditions */ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 198 | #define ANOMALY_05000267 (1) |
| 199 | /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */ |
| 200 | #define ANOMALY_05000269 (1) |
| 201 | /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ |
| 202 | #define ANOMALY_05000270 (1) |
| 203 | /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ |
| 204 | #define ANOMALY_05000272 (1) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 205 | /* Data Cache Write Back to External Synchronous Memory May Be Lost */ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 206 | #define ANOMALY_05000274 (1) |
| 207 | /* PPI Timing and Sampling Information Updates */ |
| 208 | #define ANOMALY_05000275 (__SILICON_REVISION__ > 2) |
| 209 | /* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */ |
| 210 | #define ANOMALY_05000276 (__SILICON_REVISION__ < 5) |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 211 | /* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */ |
Mike Frysinger | 7cc1c4b | 2007-12-24 20:05:09 +0800 | [diff] [blame] | 212 | #define ANOMALY_05000277 (__SILICON_REVISION__ < 3) |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 213 | /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ |
| 214 | #define ANOMALY_05000278 (__SILICON_REVISION__ < 5) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 215 | /* False Hardware Error Exception when ISR Context Is Not Restored */ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 216 | #define ANOMALY_05000281 (__SILICON_REVISION__ < 5) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 217 | /* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 218 | #define ANOMALY_05000283 (1) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 219 | /* Reads Will Receive Incorrect Data under Certain Conditions */ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 220 | #define ANOMALY_05000287 (__SILICON_REVISION__ < 5) |
| 221 | /* SPORTs May Receive Bad Data If FIFOs Fill Up */ |
| 222 | #define ANOMALY_05000288 (__SILICON_REVISION__ < 5) |
| 223 | /* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ |
| 224 | #define ANOMALY_05000301 (1) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 225 | /* SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly */ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 226 | #define ANOMALY_05000302 (1) |
Mike Frysinger | c18e99c | 2009-03-04 17:36:49 +0800 | [diff] [blame] | 227 | /* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 228 | #define ANOMALY_05000305 (__SILICON_REVISION__ < 5) |
| 229 | /* SCKELOW Bit Does Not Maintain State Through Hibernate */ |
| 230 | #define ANOMALY_05000307 (__SILICON_REVISION__ < 5) |
| 231 | /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ |
| 232 | #define ANOMALY_05000310 (1) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 233 | /* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 234 | #define ANOMALY_05000312 (1) |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 235 | /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 236 | #define ANOMALY_05000313 (1) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 237 | /* Killed System MMR Write Completes Erroneously on Next System MMR Access */ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 238 | #define ANOMALY_05000315 (1) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 239 | /* PF2 Output Remains Asserted after SPI Master Boot */ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 240 | #define ANOMALY_05000320 (__SILICON_REVISION__ > 3) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 241 | /* Erroneous GPIO Flag Pin Operations under Specific Sequences */ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 242 | #define ANOMALY_05000323 (1) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 243 | /* SPORT Secondary Receive Channel Not Functional when Word Length >16 Bits */ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 244 | #define ANOMALY_05000326 (__SILICON_REVISION__ > 3) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 245 | /* 24-Bit SPI Boot Mode Is Not Functional */ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 246 | #define ANOMALY_05000331 (__SILICON_REVISION__ < 5) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 247 | /* Slave SPI Boot Mode Is Not Functional */ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 248 | #define ANOMALY_05000332 (__SILICON_REVISION__ < 5) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 249 | /* Flag Data Register Writes One SCLK Cycle after Edge Is Detected May Clear Interrupt Status */ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 250 | #define ANOMALY_05000333 (__SILICON_REVISION__ < 5) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 251 | /* ALT_TIMING Bit in PLL_CTL Register Is Not Functional */ |
Mike Frysinger | 7cc1c4b | 2007-12-24 20:05:09 +0800 | [diff] [blame] | 252 | #define ANOMALY_05000339 (__SILICON_REVISION__ < 5) |
| 253 | /* Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory */ |
| 254 | #define ANOMALY_05000343 (__SILICON_REVISION__ < 5) |
| 255 | /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ |
| 256 | #define ANOMALY_05000357 (1) |
| 257 | /* Conflicting Column Address Widths Causes SDRAM Errors */ |
| 258 | #define ANOMALY_05000362 (1) |
Sonic Zhang | 4d55563 | 2008-04-25 03:28:10 +0800 | [diff] [blame] | 259 | /* UART Break Signal Issues */ |
| 260 | #define ANOMALY_05000363 (__SILICON_REVISION__ < 5) |
Mike Frysinger | 7cc1c4b | 2007-12-24 20:05:09 +0800 | [diff] [blame] | 261 | /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ |
| 262 | #define ANOMALY_05000366 (1) |
| 263 | /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ |
| 264 | #define ANOMALY_05000371 (1) |
Sonic Zhang | 4d55563 | 2008-04-25 03:28:10 +0800 | [diff] [blame] | 265 | /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ |
| 266 | #define ANOMALY_05000403 (1) |
Mike Frysinger | 6651ece | 2009-01-07 23:14:38 +0800 | [diff] [blame] | 267 | /* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */ |
| 268 | #define ANOMALY_05000412 (1) |
| 269 | /* Speculative Fetches Can Cause Undesired External FIFO Operations */ |
| 270 | #define ANOMALY_05000416 (1) |
| 271 | /* Multichannel SPORT Channel Misalignment Under Specific Configuration */ |
| 272 | #define ANOMALY_05000425 (1) |
| 273 | /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ |
| 274 | #define ANOMALY_05000426 (1) |
| 275 | /* Lost/Corrupted L2/L3 Memory Write after Speculative L2 Memory Read by Core B */ |
| 276 | #define ANOMALY_05000428 (__SILICON_REVISION__ > 3) |
Mike Frysinger | 3529e041 | 2008-10-28 16:22:41 +0800 | [diff] [blame] | 277 | /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ |
| 278 | #define ANOMALY_05000443 (1) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 279 | /* False Hardware Error when RETI Points to Invalid Memory */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 280 | #define ANOMALY_05000461 (1) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 281 | |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 282 | /* Anomalies that don't exist on this proc */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 283 | #define ANOMALY_05000119 (0) |
Mike Frysinger | bc8c84c | 2007-08-05 17:32:25 +0800 | [diff] [blame] | 284 | #define ANOMALY_05000158 (0) |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 285 | #define ANOMALY_05000183 (0) |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 286 | #define ANOMALY_05000233 (0) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 287 | #define ANOMALY_05000234 (0) |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 288 | #define ANOMALY_05000273 (0) |
| 289 | #define ANOMALY_05000311 (0) |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 290 | #define ANOMALY_05000353 (1) |
Mike Frysinger | ee554be | 2009-03-03 16:52:55 +0800 | [diff] [blame] | 291 | #define ANOMALY_05000380 (0) |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 292 | #define ANOMALY_05000386 (1) |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 293 | #define ANOMALY_05000389 (0) |
| 294 | #define ANOMALY_05000400 (0) |
| 295 | #define ANOMALY_05000430 (0) |
Mike Frysinger | 6651ece | 2009-01-07 23:14:38 +0800 | [diff] [blame] | 296 | #define ANOMALY_05000432 (0) |
Mike Frysinger | 94b2821 | 2008-11-18 17:48:21 +0800 | [diff] [blame] | 297 | #define ANOMALY_05000435 (0) |
Mike Frysinger | 7dbc3f6 | 2009-03-06 00:20:49 +0800 | [diff] [blame] | 298 | #define ANOMALY_05000447 (0) |
| 299 | #define ANOMALY_05000448 (0) |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 300 | #define ANOMALY_05000456 (0) |
| 301 | #define ANOMALY_05000450 (0) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 302 | #define ANOMALY_05000465 (0) |
| 303 | #define ANOMALY_05000467 (0) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 304 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 305 | #endif |