blob: 94b8e277f09d1d1773291fc6065c4be73e0b285a [file] [log] [blame]
Bryan Wu1394f032007-05-06 14:50:22 -07001/*
Mike Frysinger287050f2007-07-24 15:23:20 +08002 * File: include/asm-blackfin/mach-bf561/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
Bryan Wu1394f032007-05-06 14:50:22 -07004 *
Mike Frysingerc18e99c2009-03-04 17:36:49 +08005 * Copyright (C) 2004-2009 Analog Devices Inc.
Mike Frysinger287050f2007-07-24 15:23:20 +08006 * Licensed under the GPL-2 or later.
Bryan Wu1394f032007-05-06 14:50:22 -07007 */
8
Mike Frysingera4136472009-05-08 07:40:25 +00009/* This file should be up to date with:
Mike Frysinger6651ece2009-01-07 23:14:38 +080010 * - Revision Q, 11/07/2008; ADSP-BF561 Blackfin Processor Anomaly List
Bryan Wu1394f032007-05-06 14:50:22 -070011 */
12
13#ifndef _MACH_ANOMALY_H_
14#define _MACH_ANOMALY_H_
15
Mike Frysinger1aafd902007-07-25 11:19:14 +080016/* We do not support 0.1, 0.2, or 0.4 silicon - sorry */
17#if __SILICON_REVISION__ < 3 || __SILICON_REVISION__ == 4
Mike Frysinger7cc1c4b2007-12-24 20:05:09 +080018# error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4
Bryan Wu1394f032007-05-06 14:50:22 -070019#endif
20
Mike Frysingera200ad22009-06-13 06:37:14 -040021/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
Mike Frysinger1aafd902007-07-25 11:19:14 +080022#define ANOMALY_05000074 (1)
23/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
24#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
Mike Frysingera200ad22009-06-13 06:37:14 -040025/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */
Mike Frysinger1aafd902007-07-25 11:19:14 +080026#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
Mike Frysingera200ad22009-06-13 06:37:14 -040027/* TESTSET Instructions Restricted to 32-Bit Aligned Memory Locations */
Mike Frysinger1aafd902007-07-25 11:19:14 +080028#define ANOMALY_05000120 (1)
29/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
30#define ANOMALY_05000122 (1)
Mike Frysingera200ad22009-06-13 06:37:14 -040031/* Erroneous Exception when Enabling Cache */
Mike Frysinger1aafd902007-07-25 11:19:14 +080032#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
Mike Frysingera200ad22009-06-13 06:37:14 -040033/* SIGNBITS Instruction Not Functional under Certain Conditions */
Mike Frysinger1aafd902007-07-25 11:19:14 +080034#define ANOMALY_05000127 (1)
35/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */
36#define ANOMALY_05000134 (__SILICON_REVISION__ < 3)
37/* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */
38#define ANOMALY_05000135 (__SILICON_REVISION__ < 3)
39/* Stall in multi-unit DMA operations */
40#define ANOMALY_05000136 (__SILICON_REVISION__ < 3)
41/* Allowing the SPORT RX FIFO to fill will cause an overflow */
42#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
Mike Frysingera200ad22009-06-13 06:37:14 -040043/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
Mike Frysinger1aafd902007-07-25 11:19:14 +080044#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
45/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
46#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
47/* DMA and TESTSET conflict when both are accessing external memory */
48#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
49/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
50#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
51/* MDMA may lose the first few words of a descriptor chain */
52#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
53/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
54#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
Mike Frysingera200ad22009-06-13 06:37:14 -040055/* IMDMA S1/D1 Channel May Stall */
Mike Frysinger1aafd902007-07-25 11:19:14 +080056#define ANOMALY_05000149 (1)
57/* DMA engine may lose data due to incorrect handshaking */
58#define ANOMALY_05000150 (__SILICON_REVISION__ < 3)
59/* DMA stalls when all three controllers read data from the same source */
60#define ANOMALY_05000151 (__SILICON_REVISION__ < 3)
61/* Execution stall when executing in L2 and doing external accesses */
62#define ANOMALY_05000152 (__SILICON_REVISION__ < 3)
63/* Frame Delay in SPORT Multichannel Mode */
64#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
65/* SPORT TFS signal stays active in multichannel mode outside of valid channels */
66#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
67/* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */
68#define ANOMALY_05000156 (__SILICON_REVISION__ < 4)
Mike Frysingera200ad22009-06-13 06:37:14 -040069/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
Mike Frysinger1aafd902007-07-25 11:19:14 +080070#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
71/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
72#define ANOMALY_05000159 (__SILICON_REVISION__ < 3)
73/* A read from external memory may return a wrong value with data cache enabled */
74#define ANOMALY_05000160 (__SILICON_REVISION__ < 3)
75/* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */
76#define ANOMALY_05000161 (__SILICON_REVISION__ < 3)
77/* DMEM_CONTROL<12> is not set on Reset */
78#define ANOMALY_05000162 (__SILICON_REVISION__ < 3)
Mike Frysingera200ad22009-06-13 06:37:14 -040079/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */
Mike Frysinger1aafd902007-07-25 11:19:14 +080080#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
Mike Frysingera200ad22009-06-13 06:37:14 -040081/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
Mike Frysinger1aafd902007-07-25 11:19:14 +080082#define ANOMALY_05000166 (1)
Mike Frysingera4136472009-05-08 07:40:25 +000083/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
Mike Frysinger1aafd902007-07-25 11:19:14 +080084#define ANOMALY_05000167 (1)
Mike Frysingera200ad22009-06-13 06:37:14 -040085/* Undefined Behavior when Power-Up Sequence Is Issued to SDRAM during Auto-Refresh */
Mike Frysinger1aafd902007-07-25 11:19:14 +080086#define ANOMALY_05000168 (__SILICON_REVISION__ < 5)
Mike Frysingera200ad22009-06-13 06:37:14 -040087/* DATA CPLB Page Miss Can Result in Lost Write-Through Data Cache Writes */
Mike Frysinger1aafd902007-07-25 11:19:14 +080088#define ANOMALY_05000169 (__SILICON_REVISION__ < 5)
Mike Frysingera200ad22009-06-13 06:37:14 -040089/* Boot-ROM Modifies SICA_IWRx Wakeup Registers */
Mike Frysinger1aafd902007-07-25 11:19:14 +080090#define ANOMALY_05000171 (__SILICON_REVISION__ < 5)
91/* DSPID register values incorrect */
92#define ANOMALY_05000172 (__SILICON_REVISION__ < 3)
93/* DMA vs Core accesses to external memory */
94#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
95/* Cache Fill Buffer Data lost */
96#define ANOMALY_05000174 (__SILICON_REVISION__ < 5)
97/* Overlapping Sequencer and Memory Stalls */
98#define ANOMALY_05000175 (__SILICON_REVISION__ < 5)
Mike Frysingera200ad22009-06-13 06:37:14 -040099/* Overflow Bit Asserted when Multiplication of -1 by -1 Followed by Accumulator Saturation */
Mike Frysinger1aafd902007-07-25 11:19:14 +0800100#define ANOMALY_05000176 (__SILICON_REVISION__ < 5)
101/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
102#define ANOMALY_05000179 (__SILICON_REVISION__ < 5)
103/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
104#define ANOMALY_05000180 (1)
Mike Frysingera200ad22009-06-13 06:37:14 -0400105/* Disabling the PPI Resets the PPI Configuration Registers */
Mike Frysinger1aafd902007-07-25 11:19:14 +0800106#define ANOMALY_05000181 (__SILICON_REVISION__ < 5)
Mike Frysingera200ad22009-06-13 06:37:14 -0400107/* Internal Memory DMA Does Not Operate at Full Speed */
Mike Frysinger1aafd902007-07-25 11:19:14 +0800108#define ANOMALY_05000182 (1)
Mike Frysingera200ad22009-06-13 06:37:14 -0400109/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
Mike Frysinger1aafd902007-07-25 11:19:14 +0800110#define ANOMALY_05000184 (__SILICON_REVISION__ < 5)
Mike Frysingera200ad22009-06-13 06:37:14 -0400111/* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */
Mike Frysinger1aafd902007-07-25 11:19:14 +0800112#define ANOMALY_05000185 (__SILICON_REVISION__ < 5)
Mike Frysingera200ad22009-06-13 06:37:14 -0400113/* Upper PPI Pins Driven when PPI Packing Enabled and Data Length >8 Bits */
Mike Frysinger1aafd902007-07-25 11:19:14 +0800114#define ANOMALY_05000186 (__SILICON_REVISION__ < 5)
115/* IMDMA Corrupted Data after a Halt */
116#define ANOMALY_05000187 (1)
117/* IMDMA Restrictions on Descriptor and Buffer Placement in Memory */
118#define ANOMALY_05000188 (__SILICON_REVISION__ < 5)
Mike Frysingera200ad22009-06-13 06:37:14 -0400119/* False Protection Exceptions when Speculative Fetch Is Cancelled */
Mike Frysinger1aafd902007-07-25 11:19:14 +0800120#define ANOMALY_05000189 (__SILICON_REVISION__ < 5)
Mike Frysingera200ad22009-06-13 06:37:14 -0400121/* PPI Not Functional at Core Voltage < 1Volt */
Mike Frysinger1aafd902007-07-25 11:19:14 +0800122#define ANOMALY_05000190 (1)
123/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
124#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
125/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
126#define ANOMALY_05000193 (__SILICON_REVISION__ < 5)
127/* Restarting SPORT in Specific Modes May Cause Data Corruption */
128#define ANOMALY_05000194 (__SILICON_REVISION__ < 5)
Mike Frysingera200ad22009-06-13 06:37:14 -0400129/* Failing MMR Accesses when Preceding Memory Read Stalls */
Mike Frysinger1aafd902007-07-25 11:19:14 +0800130#define ANOMALY_05000198 (__SILICON_REVISION__ < 5)
131/* Current DMA Address Shows Wrong Value During Carry Fix */
132#define ANOMALY_05000199 (__SILICON_REVISION__ < 5)
133/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */
134#define ANOMALY_05000200 (__SILICON_REVISION__ < 5)
135/* Possible Infinite Stall with Specific Dual-DAG Situation */
136#define ANOMALY_05000202 (__SILICON_REVISION__ < 5)
Mike Frysingera200ad22009-06-13 06:37:14 -0400137/* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */
Mike Frysinger1aafd902007-07-25 11:19:14 +0800138#define ANOMALY_05000204 (__SILICON_REVISION__ < 5)
Mike Frysingera200ad22009-06-13 06:37:14 -0400139/* Specific Sequence that Can Cause DMA Error or DMA Stopping */
Mike Frysinger1aafd902007-07-25 11:19:14 +0800140#define ANOMALY_05000205 (__SILICON_REVISION__ < 5)
141/* Recovery from "Brown-Out" Condition */
142#define ANOMALY_05000207 (__SILICON_REVISION__ < 5)
143/* VSTAT Status Bit in PLL_STAT Register Is Not Functional */
144#define ANOMALY_05000208 (1)
145/* Speed Path in Computational Unit Affects Certain Instructions */
146#define ANOMALY_05000209 (__SILICON_REVISION__ < 5)
147/* UART TX Interrupt Masked Erroneously */
148#define ANOMALY_05000215 (__SILICON_REVISION__ < 5)
149/* NMI Event at Boot Time Results in Unpredictable State */
150#define ANOMALY_05000219 (__SILICON_REVISION__ < 5)
151/* Data Corruption with Cached External Memory and Non-Cached On-Chip L2 Memory */
152#define ANOMALY_05000220 (__SILICON_REVISION__ < 5)
153/* Incorrect Pulse-Width of UART Start Bit */
154#define ANOMALY_05000225 (__SILICON_REVISION__ < 5)
155/* Scratchpad Memory Bank Reads May Return Incorrect Data */
156#define ANOMALY_05000227 (__SILICON_REVISION__ < 5)
157/* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */
158#define ANOMALY_05000230 (__SILICON_REVISION__ < 5)
159/* UART STB Bit Incorrectly Affects Receiver Setting */
160#define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
Mike Frysingera200ad22009-06-13 06:37:14 -0400161/* SPORT Data Transmit Lines Are Incorrectly Driven in Multichannel Mode */
Mike Frysinger1aafd902007-07-25 11:19:14 +0800162#define ANOMALY_05000232 (__SILICON_REVISION__ < 5)
163/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
164#define ANOMALY_05000242 (__SILICON_REVISION__ < 5)
165/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
166#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
Mike Frysingera4136472009-05-08 07:40:25 +0000167/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
Mike Frysinger1aafd902007-07-25 11:19:14 +0800168#define ANOMALY_05000245 (__SILICON_REVISION__ < 5)
Mike Frysingera200ad22009-06-13 06:37:14 -0400169/* TESTSET Operation Forces Stall on the Other Core */
Mike Frysinger1aafd902007-07-25 11:19:14 +0800170#define ANOMALY_05000248 (__SILICON_REVISION__ < 5)
171/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
172#define ANOMALY_05000250 (__SILICON_REVISION__ > 2 && __SILICON_REVISION__ < 5)
173/* Exception Not Generated for MMR Accesses in Reserved Region */
174#define ANOMALY_05000251 (__SILICON_REVISION__ < 5)
175/* Maximum External Clock Speed for Timers */
176#define ANOMALY_05000253 (__SILICON_REVISION__ < 5)
177/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
178#define ANOMALY_05000254 (__SILICON_REVISION__ > 3)
179/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
180#define ANOMALY_05000257 (__SILICON_REVISION__ < 5)
181/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
182#define ANOMALY_05000258 (__SILICON_REVISION__ < 5)
183/* ICPLB_STATUS MMR Register May Be Corrupted */
184#define ANOMALY_05000260 (__SILICON_REVISION__ < 5)
185/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
186#define ANOMALY_05000261 (__SILICON_REVISION__ < 5)
187/* Stores To Data Cache May Be Lost */
188#define ANOMALY_05000262 (__SILICON_REVISION__ < 5)
189/* Hardware Loop Corrupted When Taking an ICPLB Exception */
190#define ANOMALY_05000263 (__SILICON_REVISION__ < 5)
191/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
192#define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
193/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
194#define ANOMALY_05000265 (__SILICON_REVISION__ < 5)
Mike Frysingera200ad22009-06-13 06:37:14 -0400195/* IMDMA Destination IRQ Status Must Be Read Prior to Using IMDMA */
Mike Frysinger1aafd902007-07-25 11:19:14 +0800196#define ANOMALY_05000266 (__SILICON_REVISION__ > 3)
Mike Frysingera200ad22009-06-13 06:37:14 -0400197/* IMDMA May Corrupt Data under Certain Conditions */
Mike Frysinger1aafd902007-07-25 11:19:14 +0800198#define ANOMALY_05000267 (1)
199/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
200#define ANOMALY_05000269 (1)
201/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
202#define ANOMALY_05000270 (1)
203/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
204#define ANOMALY_05000272 (1)
Mike Frysingera200ad22009-06-13 06:37:14 -0400205/* Data Cache Write Back to External Synchronous Memory May Be Lost */
Mike Frysinger1aafd902007-07-25 11:19:14 +0800206#define ANOMALY_05000274 (1)
207/* PPI Timing and Sampling Information Updates */
208#define ANOMALY_05000275 (__SILICON_REVISION__ > 2)
209/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
210#define ANOMALY_05000276 (__SILICON_REVISION__ < 5)
Mike Frysingera4136472009-05-08 07:40:25 +0000211/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
Mike Frysinger7cc1c4b2007-12-24 20:05:09 +0800212#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
Mike Frysinger1aafd902007-07-25 11:19:14 +0800213/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
214#define ANOMALY_05000278 (__SILICON_REVISION__ < 5)
Mike Frysingera200ad22009-06-13 06:37:14 -0400215/* False Hardware Error Exception when ISR Context Is Not Restored */
Mike Frysinger1aafd902007-07-25 11:19:14 +0800216#define ANOMALY_05000281 (__SILICON_REVISION__ < 5)
Mike Frysingera200ad22009-06-13 06:37:14 -0400217/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
Mike Frysinger1aafd902007-07-25 11:19:14 +0800218#define ANOMALY_05000283 (1)
Mike Frysingera200ad22009-06-13 06:37:14 -0400219/* Reads Will Receive Incorrect Data under Certain Conditions */
Mike Frysinger1aafd902007-07-25 11:19:14 +0800220#define ANOMALY_05000287 (__SILICON_REVISION__ < 5)
221/* SPORTs May Receive Bad Data If FIFOs Fill Up */
222#define ANOMALY_05000288 (__SILICON_REVISION__ < 5)
223/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
224#define ANOMALY_05000301 (1)
Mike Frysingera200ad22009-06-13 06:37:14 -0400225/* SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly */
Mike Frysinger1aafd902007-07-25 11:19:14 +0800226#define ANOMALY_05000302 (1)
Mike Frysingerc18e99c2009-03-04 17:36:49 +0800227/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
Mike Frysinger1aafd902007-07-25 11:19:14 +0800228#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
229/* SCKELOW Bit Does Not Maintain State Through Hibernate */
230#define ANOMALY_05000307 (__SILICON_REVISION__ < 5)
231/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
232#define ANOMALY_05000310 (1)
Mike Frysingera200ad22009-06-13 06:37:14 -0400233/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
Mike Frysinger1aafd902007-07-25 11:19:14 +0800234#define ANOMALY_05000312 (1)
Mike Frysingera4136472009-05-08 07:40:25 +0000235/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
Mike Frysinger1aafd902007-07-25 11:19:14 +0800236#define ANOMALY_05000313 (1)
Mike Frysingera200ad22009-06-13 06:37:14 -0400237/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
Mike Frysinger1aafd902007-07-25 11:19:14 +0800238#define ANOMALY_05000315 (1)
Mike Frysingera200ad22009-06-13 06:37:14 -0400239/* PF2 Output Remains Asserted after SPI Master Boot */
Mike Frysinger1aafd902007-07-25 11:19:14 +0800240#define ANOMALY_05000320 (__SILICON_REVISION__ > 3)
Mike Frysingera200ad22009-06-13 06:37:14 -0400241/* Erroneous GPIO Flag Pin Operations under Specific Sequences */
Mike Frysinger1aafd902007-07-25 11:19:14 +0800242#define ANOMALY_05000323 (1)
Mike Frysingera200ad22009-06-13 06:37:14 -0400243/* SPORT Secondary Receive Channel Not Functional when Word Length >16 Bits */
Mike Frysinger1aafd902007-07-25 11:19:14 +0800244#define ANOMALY_05000326 (__SILICON_REVISION__ > 3)
Mike Frysingera200ad22009-06-13 06:37:14 -0400245/* 24-Bit SPI Boot Mode Is Not Functional */
Mike Frysinger1aafd902007-07-25 11:19:14 +0800246#define ANOMALY_05000331 (__SILICON_REVISION__ < 5)
Mike Frysingera200ad22009-06-13 06:37:14 -0400247/* Slave SPI Boot Mode Is Not Functional */
Mike Frysinger1aafd902007-07-25 11:19:14 +0800248#define ANOMALY_05000332 (__SILICON_REVISION__ < 5)
Mike Frysingera200ad22009-06-13 06:37:14 -0400249/* Flag Data Register Writes One SCLK Cycle after Edge Is Detected May Clear Interrupt Status */
Mike Frysinger1aafd902007-07-25 11:19:14 +0800250#define ANOMALY_05000333 (__SILICON_REVISION__ < 5)
Mike Frysingera200ad22009-06-13 06:37:14 -0400251/* ALT_TIMING Bit in PLL_CTL Register Is Not Functional */
Mike Frysinger7cc1c4b2007-12-24 20:05:09 +0800252#define ANOMALY_05000339 (__SILICON_REVISION__ < 5)
253/* Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory */
254#define ANOMALY_05000343 (__SILICON_REVISION__ < 5)
255/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
256#define ANOMALY_05000357 (1)
257/* Conflicting Column Address Widths Causes SDRAM Errors */
258#define ANOMALY_05000362 (1)
Sonic Zhang4d555632008-04-25 03:28:10 +0800259/* UART Break Signal Issues */
260#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
Mike Frysinger7cc1c4b2007-12-24 20:05:09 +0800261/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
262#define ANOMALY_05000366 (1)
263/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
264#define ANOMALY_05000371 (1)
Sonic Zhang4d555632008-04-25 03:28:10 +0800265/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
266#define ANOMALY_05000403 (1)
Mike Frysinger6651ece2009-01-07 23:14:38 +0800267/* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */
268#define ANOMALY_05000412 (1)
269/* Speculative Fetches Can Cause Undesired External FIFO Operations */
270#define ANOMALY_05000416 (1)
271/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
272#define ANOMALY_05000425 (1)
273/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
274#define ANOMALY_05000426 (1)
275/* Lost/Corrupted L2/L3 Memory Write after Speculative L2 Memory Read by Core B */
276#define ANOMALY_05000428 (__SILICON_REVISION__ > 3)
Mike Frysinger3529e0412008-10-28 16:22:41 +0800277/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
278#define ANOMALY_05000443 (1)
Mike Frysingera200ad22009-06-13 06:37:14 -0400279/* False Hardware Error when RETI Points to Invalid Memory */
Mike Frysingera4136472009-05-08 07:40:25 +0000280#define ANOMALY_05000461 (1)
Bryan Wu1394f032007-05-06 14:50:22 -0700281
Mike Frysinger1aafd902007-07-25 11:19:14 +0800282/* Anomalies that don't exist on this proc */
Mike Frysingera4136472009-05-08 07:40:25 +0000283#define ANOMALY_05000119 (0)
Mike Frysingerbc8c84c2007-08-05 17:32:25 +0800284#define ANOMALY_05000158 (0)
Mike Frysinger1aafd902007-07-25 11:19:14 +0800285#define ANOMALY_05000183 (0)
Mike Frysingera4136472009-05-08 07:40:25 +0000286#define ANOMALY_05000233 (0)
Mike Frysingera200ad22009-06-13 06:37:14 -0400287#define ANOMALY_05000234 (0)
Mike Frysinger1aafd902007-07-25 11:19:14 +0800288#define ANOMALY_05000273 (0)
289#define ANOMALY_05000311 (0)
Mike Frysinger4e8086d2008-10-10 21:07:55 +0800290#define ANOMALY_05000353 (1)
Mike Frysingeree554be2009-03-03 16:52:55 +0800291#define ANOMALY_05000380 (0)
Mike Frysinger4e8086d2008-10-10 21:07:55 +0800292#define ANOMALY_05000386 (1)
Mike Frysingera4136472009-05-08 07:40:25 +0000293#define ANOMALY_05000389 (0)
294#define ANOMALY_05000400 (0)
295#define ANOMALY_05000430 (0)
Mike Frysinger6651ece2009-01-07 23:14:38 +0800296#define ANOMALY_05000432 (0)
Mike Frysinger94b28212008-11-18 17:48:21 +0800297#define ANOMALY_05000435 (0)
Mike Frysinger7dbc3f62009-03-06 00:20:49 +0800298#define ANOMALY_05000447 (0)
299#define ANOMALY_05000448 (0)
Mike Frysingera4136472009-05-08 07:40:25 +0000300#define ANOMALY_05000456 (0)
301#define ANOMALY_05000450 (0)
Mike Frysingera200ad22009-06-13 06:37:14 -0400302#define ANOMALY_05000465 (0)
303#define ANOMALY_05000467 (0)
Bryan Wu1394f032007-05-06 14:50:22 -0700304
Bryan Wu1394f032007-05-06 14:50:22 -0700305#endif