Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the "Software"), |
| 7 | * to deal in the Software without restriction, including without limitation |
| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
| 10 | * Software is furnished to do so, subject to the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice shall be included in |
| 13 | * all copies or substantial portions of the Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 21 | * OTHER DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: Dave Airlie |
| 24 | * Alex Deucher |
| 25 | */ |
| 26 | #include <drm/drmP.h> |
| 27 | #include <drm/drm_crtc_helper.h> |
| 28 | #include <drm/radeon_drm.h> |
| 29 | #include "radeon_fixed.h" |
| 30 | #include "radeon.h" |
| 31 | |
| 32 | void radeon_restore_common_regs(struct drm_device *dev) |
| 33 | { |
| 34 | /* don't need this yet */ |
| 35 | } |
| 36 | |
| 37 | static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev) |
| 38 | { |
| 39 | struct radeon_device *rdev = dev->dev_private; |
| 40 | int i = 0; |
| 41 | |
| 42 | /* FIXME: Certain revisions of R300 can't recover here. Not sure of |
| 43 | the cause yet, but this workaround will mask the problem for now. |
| 44 | Other chips usually will pass at the very first test, so the |
| 45 | workaround shouldn't have any effect on them. */ |
| 46 | for (i = 0; |
| 47 | (i < 10000 && |
| 48 | RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); |
| 49 | i++); |
| 50 | } |
| 51 | |
| 52 | static void radeon_pll_write_update(struct drm_device *dev) |
| 53 | { |
| 54 | struct radeon_device *rdev = dev->dev_private; |
| 55 | |
| 56 | while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); |
| 57 | |
| 58 | WREG32_PLL_P(RADEON_PPLL_REF_DIV, |
| 59 | RADEON_PPLL_ATOMIC_UPDATE_W, |
| 60 | ~(RADEON_PPLL_ATOMIC_UPDATE_W)); |
| 61 | } |
| 62 | |
| 63 | static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev) |
| 64 | { |
| 65 | struct radeon_device *rdev = dev->dev_private; |
| 66 | int i = 0; |
| 67 | |
| 68 | |
| 69 | /* FIXME: Certain revisions of R300 can't recover here. Not sure of |
| 70 | the cause yet, but this workaround will mask the problem for now. |
| 71 | Other chips usually will pass at the very first test, so the |
| 72 | workaround shouldn't have any effect on them. */ |
| 73 | for (i = 0; |
| 74 | (i < 10000 && |
| 75 | RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); |
| 76 | i++); |
| 77 | } |
| 78 | |
| 79 | static void radeon_pll2_write_update(struct drm_device *dev) |
| 80 | { |
| 81 | struct radeon_device *rdev = dev->dev_private; |
| 82 | |
| 83 | while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); |
| 84 | |
| 85 | WREG32_PLL_P(RADEON_P2PLL_REF_DIV, |
| 86 | RADEON_P2PLL_ATOMIC_UPDATE_W, |
| 87 | ~(RADEON_P2PLL_ATOMIC_UPDATE_W)); |
| 88 | } |
| 89 | |
| 90 | static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div, |
| 91 | uint16_t fb_div) |
| 92 | { |
| 93 | unsigned int vcoFreq; |
| 94 | |
| 95 | if (!ref_div) |
| 96 | return 1; |
| 97 | |
| 98 | vcoFreq = ((unsigned)ref_freq & fb_div) / ref_div; |
| 99 | |
| 100 | /* |
| 101 | * This is horribly crude: the VCO frequency range is divided into |
| 102 | * 3 parts, each part having a fixed PLL gain value. |
| 103 | */ |
| 104 | if (vcoFreq >= 30000) |
| 105 | /* |
| 106 | * [300..max] MHz : 7 |
| 107 | */ |
| 108 | return 7; |
| 109 | else if (vcoFreq >= 18000) |
| 110 | /* |
| 111 | * [180..300) MHz : 4 |
| 112 | */ |
| 113 | return 4; |
| 114 | else |
| 115 | /* |
| 116 | * [0..180) MHz : 1 |
| 117 | */ |
| 118 | return 1; |
| 119 | } |
| 120 | |
| 121 | void radeon_crtc_dpms(struct drm_crtc *crtc, int mode) |
| 122 | { |
| 123 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 124 | struct drm_device *dev = crtc->dev; |
| 125 | struct radeon_device *rdev = dev->dev_private; |
| 126 | uint32_t mask; |
| 127 | |
| 128 | if (radeon_crtc->crtc_id) |
| 129 | mask = (RADEON_CRTC2_EN | |
| 130 | RADEON_CRTC2_DISP_DIS | |
| 131 | RADEON_CRTC2_VSYNC_DIS | |
| 132 | RADEON_CRTC2_HSYNC_DIS | |
| 133 | RADEON_CRTC2_DISP_REQ_EN_B); |
| 134 | else |
| 135 | mask = (RADEON_CRTC_DISPLAY_DIS | |
| 136 | RADEON_CRTC_VSYNC_DIS | |
| 137 | RADEON_CRTC_HSYNC_DIS); |
| 138 | |
| 139 | switch (mode) { |
| 140 | case DRM_MODE_DPMS_ON: |
| 141 | if (radeon_crtc->crtc_id) |
| 142 | WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~mask); |
| 143 | else { |
| 144 | WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN | |
| 145 | RADEON_CRTC_DISP_REQ_EN_B)); |
| 146 | WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask); |
| 147 | } |
| 148 | break; |
| 149 | case DRM_MODE_DPMS_STANDBY: |
| 150 | case DRM_MODE_DPMS_SUSPEND: |
| 151 | case DRM_MODE_DPMS_OFF: |
| 152 | if (radeon_crtc->crtc_id) |
| 153 | WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~mask); |
| 154 | else { |
| 155 | WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN | |
| 156 | RADEON_CRTC_DISP_REQ_EN_B)); |
| 157 | WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask); |
| 158 | } |
| 159 | break; |
| 160 | } |
| 161 | |
| 162 | if (mode != DRM_MODE_DPMS_OFF) { |
| 163 | radeon_crtc_load_lut(crtc); |
| 164 | } |
| 165 | } |
| 166 | |
| 167 | /* properly set crtc bpp when using atombios */ |
| 168 | void radeon_legacy_atom_set_surface(struct drm_crtc *crtc) |
| 169 | { |
| 170 | struct drm_device *dev = crtc->dev; |
| 171 | struct radeon_device *rdev = dev->dev_private; |
| 172 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 173 | int format; |
| 174 | uint32_t crtc_gen_cntl; |
| 175 | uint32_t disp_merge_cntl; |
| 176 | uint32_t crtc_pitch; |
| 177 | |
| 178 | switch (crtc->fb->bits_per_pixel) { |
| 179 | case 15: /* 555 */ |
| 180 | format = 3; |
| 181 | break; |
| 182 | case 16: /* 565 */ |
| 183 | format = 4; |
| 184 | break; |
| 185 | case 24: /* RGB */ |
| 186 | format = 5; |
| 187 | break; |
| 188 | case 32: /* xRGB */ |
| 189 | format = 6; |
| 190 | break; |
| 191 | default: |
| 192 | return; |
| 193 | } |
| 194 | |
| 195 | crtc_pitch = ((((crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8)) * crtc->fb->bits_per_pixel) + |
| 196 | ((crtc->fb->bits_per_pixel * 8) - 1)) / |
| 197 | (crtc->fb->bits_per_pixel * 8)); |
| 198 | crtc_pitch |= crtc_pitch << 16; |
| 199 | |
| 200 | WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch); |
| 201 | |
| 202 | switch (radeon_crtc->crtc_id) { |
| 203 | case 0: |
| 204 | disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); |
| 205 | disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; |
| 206 | WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); |
| 207 | |
| 208 | crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0xfffff0ff; |
| 209 | crtc_gen_cntl |= (format << 8); |
| 210 | crtc_gen_cntl |= RADEON_CRTC_EXT_DISP_EN; |
| 211 | WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); |
| 212 | break; |
| 213 | case 1: |
| 214 | disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); |
| 215 | disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; |
| 216 | WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl); |
| 217 | |
| 218 | crtc_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0xfffff0ff; |
| 219 | crtc_gen_cntl |= (format << 8); |
| 220 | WREG32(RADEON_CRTC2_GEN_CNTL, crtc_gen_cntl); |
| 221 | WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID)); |
| 222 | WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID)); |
| 223 | break; |
| 224 | } |
| 225 | } |
| 226 | |
| 227 | int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
| 228 | struct drm_framebuffer *old_fb) |
| 229 | { |
| 230 | struct drm_device *dev = crtc->dev; |
| 231 | struct radeon_device *rdev = dev->dev_private; |
| 232 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 233 | struct radeon_framebuffer *radeon_fb; |
| 234 | struct drm_gem_object *obj; |
| 235 | uint64_t base; |
| 236 | uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0; |
| 237 | uint32_t crtc_pitch, pitch_pixels; |
| 238 | |
| 239 | DRM_DEBUG("\n"); |
| 240 | |
| 241 | radeon_fb = to_radeon_framebuffer(crtc->fb); |
| 242 | |
| 243 | obj = radeon_fb->obj; |
| 244 | if (radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &base)) { |
| 245 | return -EINVAL; |
| 246 | } |
| 247 | crtc_offset = (u32)base; |
| 248 | crtc_offset_cntl = 0; |
| 249 | |
| 250 | pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8); |
| 251 | crtc_pitch = (((pitch_pixels * crtc->fb->bits_per_pixel) + |
| 252 | ((crtc->fb->bits_per_pixel * 8) - 1)) / |
| 253 | (crtc->fb->bits_per_pixel * 8)); |
| 254 | crtc_pitch |= crtc_pitch << 16; |
| 255 | |
| 256 | /* TODO tiling */ |
| 257 | if (0) { |
| 258 | if (ASIC_IS_R300(rdev)) |
| 259 | crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN | |
| 260 | R300_CRTC_MICRO_TILE_BUFFER_DIS | |
| 261 | R300_CRTC_MACRO_TILE_EN); |
| 262 | else |
| 263 | crtc_offset_cntl |= RADEON_CRTC_TILE_EN; |
| 264 | } else { |
| 265 | if (ASIC_IS_R300(rdev)) |
| 266 | crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN | |
| 267 | R300_CRTC_MICRO_TILE_BUFFER_DIS | |
| 268 | R300_CRTC_MACRO_TILE_EN); |
| 269 | else |
| 270 | crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN; |
| 271 | } |
| 272 | |
| 273 | |
| 274 | /* TODO more tiling */ |
| 275 | if (0) { |
| 276 | if (ASIC_IS_R300(rdev)) { |
| 277 | crtc_tile_x0_y0 = x | (y << 16); |
| 278 | base &= ~0x7ff; |
| 279 | } else { |
| 280 | int byteshift = crtc->fb->bits_per_pixel >> 4; |
| 281 | int tile_addr = (((y >> 3) * crtc->fb->width + x) >> (8 - byteshift)) << 11; |
| 282 | base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8); |
| 283 | crtc_offset_cntl |= (y % 16); |
| 284 | } |
| 285 | } else { |
| 286 | int offset = y * pitch_pixels + x; |
| 287 | switch (crtc->fb->bits_per_pixel) { |
| 288 | case 15: |
| 289 | case 16: |
| 290 | offset *= 2; |
| 291 | break; |
| 292 | case 24: |
| 293 | offset *= 3; |
| 294 | break; |
| 295 | case 32: |
| 296 | offset *= 4; |
| 297 | break; |
| 298 | default: |
| 299 | return false; |
| 300 | } |
| 301 | base += offset; |
| 302 | } |
| 303 | |
| 304 | base &= ~7; |
| 305 | |
| 306 | /* update sarea TODO */ |
| 307 | |
| 308 | crtc_offset = (u32)base; |
| 309 | |
| 310 | WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, rdev->mc.vram_location); |
| 311 | |
| 312 | if (ASIC_IS_R300(rdev)) { |
| 313 | if (radeon_crtc->crtc_id) |
| 314 | WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0); |
| 315 | else |
| 316 | WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0); |
| 317 | } |
| 318 | WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl); |
| 319 | WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset); |
| 320 | WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch); |
| 321 | |
| 322 | if (old_fb && old_fb != crtc->fb) { |
| 323 | radeon_fb = to_radeon_framebuffer(old_fb); |
| 324 | radeon_gem_object_unpin(radeon_fb->obj); |
| 325 | } |
| 326 | return 0; |
| 327 | } |
| 328 | |
| 329 | static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode) |
| 330 | { |
| 331 | struct drm_device *dev = crtc->dev; |
| 332 | struct radeon_device *rdev = dev->dev_private; |
| 333 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 334 | int format; |
| 335 | int hsync_start; |
| 336 | int hsync_wid; |
| 337 | int vsync_wid; |
| 338 | uint32_t crtc_h_total_disp; |
| 339 | uint32_t crtc_h_sync_strt_wid; |
| 340 | uint32_t crtc_v_total_disp; |
| 341 | uint32_t crtc_v_sync_strt_wid; |
| 342 | |
| 343 | DRM_DEBUG("\n"); |
| 344 | |
| 345 | switch (crtc->fb->bits_per_pixel) { |
| 346 | case 15: /* 555 */ |
| 347 | format = 3; |
| 348 | break; |
| 349 | case 16: /* 565 */ |
| 350 | format = 4; |
| 351 | break; |
| 352 | case 24: /* RGB */ |
| 353 | format = 5; |
| 354 | break; |
| 355 | case 32: /* xRGB */ |
| 356 | format = 6; |
| 357 | break; |
| 358 | default: |
| 359 | return false; |
| 360 | } |
| 361 | |
| 362 | crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff) |
| 363 | | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); |
| 364 | |
| 365 | hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; |
| 366 | if (!hsync_wid) |
| 367 | hsync_wid = 1; |
| 368 | hsync_start = mode->crtc_hsync_start - 8; |
| 369 | |
| 370 | crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
| 371 | | ((hsync_wid & 0x3f) << 16) |
| 372 | | ((mode->flags & DRM_MODE_FLAG_NHSYNC) |
| 373 | ? RADEON_CRTC_H_SYNC_POL |
| 374 | : 0)); |
| 375 | |
| 376 | /* This works for double scan mode. */ |
| 377 | crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff) |
| 378 | | ((mode->crtc_vdisplay - 1) << 16)); |
| 379 | |
| 380 | vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; |
| 381 | if (!vsync_wid) |
| 382 | vsync_wid = 1; |
| 383 | |
| 384 | crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff) |
| 385 | | ((vsync_wid & 0x1f) << 16) |
| 386 | | ((mode->flags & DRM_MODE_FLAG_NVSYNC) |
| 387 | ? RADEON_CRTC_V_SYNC_POL |
| 388 | : 0)); |
| 389 | |
| 390 | /* TODO -> Dell Server */ |
| 391 | if (0) { |
| 392 | uint32_t disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); |
| 393 | uint32_t tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); |
| 394 | uint32_t dac2_cntl = RREG32(RADEON_DAC_CNTL2); |
| 395 | uint32_t crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); |
| 396 | |
| 397 | dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL; |
| 398 | dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL; |
| 399 | |
| 400 | /* For CRT on DAC2, don't turn it on if BIOS didn't |
| 401 | enable it, even it's detected. |
| 402 | */ |
| 403 | disp_hw_debug |= RADEON_CRT2_DISP1_SEL; |
| 404 | tv_dac_cntl &= ~((1<<2) | (3<<8) | (7<<24) | (0xff<<16)); |
| 405 | tv_dac_cntl |= (0x03 | (2<<8) | (0x58<<16)); |
| 406 | |
| 407 | WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); |
| 408 | WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); |
| 409 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); |
| 410 | WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); |
| 411 | } |
| 412 | |
| 413 | if (radeon_crtc->crtc_id) { |
| 414 | uint32_t crtc2_gen_cntl; |
| 415 | uint32_t disp2_merge_cntl; |
| 416 | |
| 417 | /* check to see if TV DAC is enabled for another crtc and keep it enabled */ |
| 418 | if (RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_CRT2_ON) |
| 419 | crtc2_gen_cntl = RADEON_CRTC2_CRT2_ON; |
| 420 | else |
| 421 | crtc2_gen_cntl = 0; |
| 422 | |
| 423 | crtc2_gen_cntl |= ((format << 8) |
| 424 | | RADEON_CRTC2_VSYNC_DIS |
| 425 | | RADEON_CRTC2_HSYNC_DIS |
| 426 | | RADEON_CRTC2_DISP_DIS |
| 427 | | RADEON_CRTC2_DISP_REQ_EN_B |
| 428 | | ((mode->flags & DRM_MODE_FLAG_DBLSCAN) |
| 429 | ? RADEON_CRTC2_DBL_SCAN_EN |
| 430 | : 0) |
| 431 | | ((mode->flags & DRM_MODE_FLAG_CSYNC) |
| 432 | ? RADEON_CRTC2_CSYNC_EN |
| 433 | : 0) |
| 434 | | ((mode->flags & DRM_MODE_FLAG_INTERLACE) |
| 435 | ? RADEON_CRTC2_INTERLACE_EN |
| 436 | : 0)); |
| 437 | |
| 438 | disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); |
| 439 | disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; |
| 440 | |
| 441 | WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl); |
| 442 | WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); |
| 443 | } else { |
| 444 | uint32_t crtc_gen_cntl; |
| 445 | uint32_t crtc_ext_cntl; |
| 446 | uint32_t disp_merge_cntl; |
| 447 | |
| 448 | crtc_gen_cntl = (RADEON_CRTC_EXT_DISP_EN |
| 449 | | (format << 8) |
| 450 | | RADEON_CRTC_DISP_REQ_EN_B |
| 451 | | ((mode->flags & DRM_MODE_FLAG_DBLSCAN) |
| 452 | ? RADEON_CRTC_DBL_SCAN_EN |
| 453 | : 0) |
| 454 | | ((mode->flags & DRM_MODE_FLAG_CSYNC) |
| 455 | ? RADEON_CRTC_CSYNC_EN |
| 456 | : 0) |
| 457 | | ((mode->flags & DRM_MODE_FLAG_INTERLACE) |
| 458 | ? RADEON_CRTC_INTERLACE_EN |
| 459 | : 0)); |
| 460 | |
| 461 | crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); |
| 462 | crtc_ext_cntl |= (RADEON_XCRT_CNT_EN | |
| 463 | RADEON_CRTC_VSYNC_DIS | |
| 464 | RADEON_CRTC_HSYNC_DIS | |
| 465 | RADEON_CRTC_DISPLAY_DIS); |
| 466 | |
| 467 | disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); |
| 468 | disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; |
| 469 | |
| 470 | WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); |
| 471 | WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); |
| 472 | WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); |
| 473 | } |
| 474 | |
| 475 | WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp); |
| 476 | WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid); |
| 477 | WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp); |
| 478 | WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid); |
| 479 | |
| 480 | return true; |
| 481 | } |
| 482 | |
| 483 | static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) |
| 484 | { |
| 485 | struct drm_device *dev = crtc->dev; |
| 486 | struct radeon_device *rdev = dev->dev_private; |
| 487 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 488 | struct drm_encoder *encoder; |
| 489 | uint32_t feedback_div = 0; |
| 490 | uint32_t frac_fb_div = 0; |
| 491 | uint32_t reference_div = 0; |
| 492 | uint32_t post_divider = 0; |
| 493 | uint32_t freq = 0; |
| 494 | uint8_t pll_gain; |
| 495 | int pll_flags = RADEON_PLL_LEGACY; |
| 496 | bool use_bios_divs = false; |
| 497 | /* PLL registers */ |
| 498 | uint32_t pll_ref_div = 0; |
| 499 | uint32_t pll_fb_post_div = 0; |
| 500 | uint32_t htotal_cntl = 0; |
| 501 | |
| 502 | struct radeon_pll *pll; |
| 503 | |
| 504 | struct { |
| 505 | int divider; |
| 506 | int bitvalue; |
| 507 | } *post_div, post_divs[] = { |
| 508 | /* From RAGE 128 VR/RAGE 128 GL Register |
| 509 | * Reference Manual (Technical Reference |
| 510 | * Manual P/N RRG-G04100-C Rev. 0.04), page |
| 511 | * 3-17 (PLL_DIV_[3:0]). |
| 512 | */ |
| 513 | { 1, 0 }, /* VCLK_SRC */ |
| 514 | { 2, 1 }, /* VCLK_SRC/2 */ |
| 515 | { 4, 2 }, /* VCLK_SRC/4 */ |
| 516 | { 8, 3 }, /* VCLK_SRC/8 */ |
| 517 | { 3, 4 }, /* VCLK_SRC/3 */ |
| 518 | { 16, 5 }, /* VCLK_SRC/16 */ |
| 519 | { 6, 6 }, /* VCLK_SRC/6 */ |
| 520 | { 12, 7 }, /* VCLK_SRC/12 */ |
| 521 | { 0, 0 } |
| 522 | }; |
| 523 | |
| 524 | if (radeon_crtc->crtc_id) |
| 525 | pll = &rdev->clock.p2pll; |
| 526 | else |
| 527 | pll = &rdev->clock.p1pll; |
| 528 | |
| 529 | if (mode->clock > 200000) /* range limits??? */ |
| 530 | pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; |
| 531 | else |
| 532 | pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; |
| 533 | |
| 534 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 535 | if (encoder->crtc == crtc) { |
| 536 | if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) |
| 537 | pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; |
| 538 | if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) { |
| 539 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 540 | struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv; |
| 541 | if (lvds) { |
| 542 | if (lvds->use_bios_dividers) { |
| 543 | pll_ref_div = lvds->panel_ref_divider; |
| 544 | pll_fb_post_div = (lvds->panel_fb_divider | |
| 545 | (lvds->panel_post_divider << 16)); |
| 546 | htotal_cntl = 0; |
| 547 | use_bios_divs = true; |
| 548 | } |
| 549 | } |
| 550 | pll_flags |= RADEON_PLL_USE_REF_DIV; |
| 551 | } |
| 552 | } |
| 553 | } |
| 554 | |
| 555 | DRM_DEBUG("\n"); |
| 556 | |
| 557 | if (!use_bios_divs) { |
| 558 | radeon_compute_pll(pll, mode->clock, |
| 559 | &freq, &feedback_div, &frac_fb_div, |
| 560 | &reference_div, &post_divider, |
| 561 | pll_flags); |
| 562 | |
| 563 | for (post_div = &post_divs[0]; post_div->divider; ++post_div) { |
| 564 | if (post_div->divider == post_divider) |
| 565 | break; |
| 566 | } |
| 567 | |
| 568 | if (!post_div->divider) |
| 569 | post_div = &post_divs[0]; |
| 570 | |
| 571 | DRM_DEBUG("dc=%u, fd=%d, rd=%d, pd=%d\n", |
| 572 | (unsigned)freq, |
| 573 | feedback_div, |
| 574 | reference_div, |
| 575 | post_divider); |
| 576 | |
| 577 | pll_ref_div = reference_div; |
| 578 | #if defined(__powerpc__) && (0) /* TODO */ |
| 579 | /* apparently programming this otherwise causes a hang??? */ |
| 580 | if (info->MacModel == RADEON_MAC_IBOOK) |
| 581 | pll_fb_post_div = 0x000600ad; |
| 582 | else |
| 583 | #endif |
| 584 | pll_fb_post_div = (feedback_div | (post_div->bitvalue << 16)); |
| 585 | |
| 586 | htotal_cntl = mode->htotal & 0x7; |
| 587 | |
| 588 | } |
| 589 | |
| 590 | pll_gain = radeon_compute_pll_gain(pll->reference_freq, |
| 591 | pll_ref_div & 0x3ff, |
| 592 | pll_fb_post_div & 0x7ff); |
| 593 | |
| 594 | if (radeon_crtc->crtc_id) { |
| 595 | uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) & |
| 596 | ~(RADEON_PIX2CLK_SRC_SEL_MASK)) | |
| 597 | RADEON_PIX2CLK_SRC_SEL_P2PLLCLK); |
| 598 | |
| 599 | WREG32_PLL_P(RADEON_PIXCLKS_CNTL, |
| 600 | RADEON_PIX2CLK_SRC_SEL_CPUCLK, |
| 601 | ~(RADEON_PIX2CLK_SRC_SEL_MASK)); |
| 602 | |
| 603 | WREG32_PLL_P(RADEON_P2PLL_CNTL, |
| 604 | RADEON_P2PLL_RESET |
| 605 | | RADEON_P2PLL_ATOMIC_UPDATE_EN |
| 606 | | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT), |
| 607 | ~(RADEON_P2PLL_RESET |
| 608 | | RADEON_P2PLL_ATOMIC_UPDATE_EN |
| 609 | | RADEON_P2PLL_PVG_MASK)); |
| 610 | |
| 611 | WREG32_PLL_P(RADEON_P2PLL_REF_DIV, |
| 612 | pll_ref_div, |
| 613 | ~RADEON_P2PLL_REF_DIV_MASK); |
| 614 | |
| 615 | WREG32_PLL_P(RADEON_P2PLL_DIV_0, |
| 616 | pll_fb_post_div, |
| 617 | ~RADEON_P2PLL_FB0_DIV_MASK); |
| 618 | |
| 619 | WREG32_PLL_P(RADEON_P2PLL_DIV_0, |
| 620 | pll_fb_post_div, |
| 621 | ~RADEON_P2PLL_POST0_DIV_MASK); |
| 622 | |
| 623 | radeon_pll2_write_update(dev); |
| 624 | radeon_pll2_wait_for_read_update_complete(dev); |
| 625 | |
| 626 | WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl); |
| 627 | |
| 628 | WREG32_PLL_P(RADEON_P2PLL_CNTL, |
| 629 | 0, |
| 630 | ~(RADEON_P2PLL_RESET |
| 631 | | RADEON_P2PLL_SLEEP |
| 632 | | RADEON_P2PLL_ATOMIC_UPDATE_EN)); |
| 633 | |
| 634 | DRM_DEBUG("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n", |
| 635 | (unsigned)pll_ref_div, |
| 636 | (unsigned)pll_fb_post_div, |
| 637 | (unsigned)htotal_cntl, |
| 638 | RREG32_PLL(RADEON_P2PLL_CNTL)); |
| 639 | DRM_DEBUG("Wrote2: rd=%u, fd=%u, pd=%u\n", |
| 640 | (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, |
| 641 | (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK, |
| 642 | (unsigned)((pll_fb_post_div & |
| 643 | RADEON_P2PLL_POST0_DIV_MASK) >> 16)); |
| 644 | |
| 645 | mdelay(50); /* Let the clock to lock */ |
| 646 | |
| 647 | WREG32_PLL_P(RADEON_PIXCLKS_CNTL, |
| 648 | RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, |
| 649 | ~(RADEON_PIX2CLK_SRC_SEL_MASK)); |
| 650 | |
| 651 | WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); |
| 652 | } else { |
| 653 | if (rdev->flags & RADEON_IS_MOBILITY) { |
| 654 | /* A temporal workaround for the occational blanking on certain laptop panels. |
| 655 | This appears to related to the PLL divider registers (fail to lock?). |
| 656 | It occurs even when all dividers are the same with their old settings. |
| 657 | In this case we really don't need to fiddle with PLL registers. |
| 658 | By doing this we can avoid the blanking problem with some panels. |
| 659 | */ |
| 660 | if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) && |
| 661 | (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) & |
| 662 | (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) { |
| 663 | WREG32_P(RADEON_CLOCK_CNTL_INDEX, |
| 664 | RADEON_PLL_DIV_SEL, |
| 665 | ~(RADEON_PLL_DIV_SEL)); |
| 666 | r100_pll_errata_after_index(rdev); |
| 667 | return; |
| 668 | } |
| 669 | } |
| 670 | |
| 671 | WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, |
| 672 | RADEON_VCLK_SRC_SEL_CPUCLK, |
| 673 | ~(RADEON_VCLK_SRC_SEL_MASK)); |
| 674 | WREG32_PLL_P(RADEON_PPLL_CNTL, |
| 675 | RADEON_PPLL_RESET |
| 676 | | RADEON_PPLL_ATOMIC_UPDATE_EN |
| 677 | | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN |
| 678 | | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT), |
| 679 | ~(RADEON_PPLL_RESET |
| 680 | | RADEON_PPLL_ATOMIC_UPDATE_EN |
| 681 | | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN |
| 682 | | RADEON_PPLL_PVG_MASK)); |
| 683 | |
| 684 | WREG32_P(RADEON_CLOCK_CNTL_INDEX, |
| 685 | RADEON_PLL_DIV_SEL, |
| 686 | ~(RADEON_PLL_DIV_SEL)); |
| 687 | r100_pll_errata_after_index(rdev); |
| 688 | |
| 689 | if (ASIC_IS_R300(rdev) || |
| 690 | (rdev->family == CHIP_RS300) || |
| 691 | (rdev->family == CHIP_RS400) || |
| 692 | (rdev->family == CHIP_RS480)) { |
| 693 | if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { |
| 694 | /* When restoring console mode, use saved PPLL_REF_DIV |
| 695 | * setting. |
| 696 | */ |
| 697 | WREG32_PLL_P(RADEON_PPLL_REF_DIV, |
| 698 | pll_ref_div, |
| 699 | 0); |
| 700 | } else { |
| 701 | /* R300 uses ref_div_acc field as real ref divider */ |
| 702 | WREG32_PLL_P(RADEON_PPLL_REF_DIV, |
| 703 | (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), |
| 704 | ~R300_PPLL_REF_DIV_ACC_MASK); |
| 705 | } |
| 706 | } else |
| 707 | WREG32_PLL_P(RADEON_PPLL_REF_DIV, |
| 708 | pll_ref_div, |
| 709 | ~RADEON_PPLL_REF_DIV_MASK); |
| 710 | |
| 711 | WREG32_PLL_P(RADEON_PPLL_DIV_3, |
| 712 | pll_fb_post_div, |
| 713 | ~RADEON_PPLL_FB3_DIV_MASK); |
| 714 | |
| 715 | WREG32_PLL_P(RADEON_PPLL_DIV_3, |
| 716 | pll_fb_post_div, |
| 717 | ~RADEON_PPLL_POST3_DIV_MASK); |
| 718 | |
| 719 | radeon_pll_write_update(dev); |
| 720 | radeon_pll_wait_for_read_update_complete(dev); |
| 721 | |
| 722 | WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl); |
| 723 | |
| 724 | WREG32_PLL_P(RADEON_PPLL_CNTL, |
| 725 | 0, |
| 726 | ~(RADEON_PPLL_RESET |
| 727 | | RADEON_PPLL_SLEEP |
| 728 | | RADEON_PPLL_ATOMIC_UPDATE_EN |
| 729 | | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN)); |
| 730 | |
| 731 | DRM_DEBUG("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n", |
| 732 | pll_ref_div, |
| 733 | pll_fb_post_div, |
| 734 | (unsigned)htotal_cntl, |
| 735 | RREG32_PLL(RADEON_PPLL_CNTL)); |
| 736 | DRM_DEBUG("Wrote: rd=%d, fd=%d, pd=%d\n", |
| 737 | pll_ref_div & RADEON_PPLL_REF_DIV_MASK, |
| 738 | pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK, |
| 739 | (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16); |
| 740 | |
| 741 | mdelay(50); /* Let the clock to lock */ |
| 742 | |
| 743 | WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, |
| 744 | RADEON_VCLK_SRC_SEL_PPLLCLK, |
| 745 | ~(RADEON_VCLK_SRC_SEL_MASK)); |
| 746 | |
| 747 | } |
| 748 | } |
| 749 | |
| 750 | static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc, |
| 751 | struct drm_display_mode *mode, |
| 752 | struct drm_display_mode *adjusted_mode) |
| 753 | { |
| 754 | return true; |
| 755 | } |
| 756 | |
| 757 | static int radeon_crtc_mode_set(struct drm_crtc *crtc, |
| 758 | struct drm_display_mode *mode, |
| 759 | struct drm_display_mode *adjusted_mode, |
| 760 | int x, int y, struct drm_framebuffer *old_fb) |
| 761 | { |
| 762 | |
| 763 | DRM_DEBUG("\n"); |
| 764 | |
| 765 | /* TODO TV */ |
| 766 | |
| 767 | radeon_crtc_set_base(crtc, x, y, old_fb); |
| 768 | radeon_set_crtc_timing(crtc, adjusted_mode); |
| 769 | radeon_set_pll(crtc, adjusted_mode); |
| 770 | radeon_init_disp_bandwidth(crtc->dev); |
| 771 | |
| 772 | return 0; |
| 773 | } |
| 774 | |
| 775 | static void radeon_crtc_prepare(struct drm_crtc *crtc) |
| 776 | { |
| 777 | radeon_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
| 778 | } |
| 779 | |
| 780 | static void radeon_crtc_commit(struct drm_crtc *crtc) |
| 781 | { |
| 782 | radeon_crtc_dpms(crtc, DRM_MODE_DPMS_ON); |
| 783 | } |
| 784 | |
| 785 | static const struct drm_crtc_helper_funcs legacy_helper_funcs = { |
| 786 | .dpms = radeon_crtc_dpms, |
| 787 | .mode_fixup = radeon_crtc_mode_fixup, |
| 788 | .mode_set = radeon_crtc_mode_set, |
| 789 | .mode_set_base = radeon_crtc_set_base, |
| 790 | .prepare = radeon_crtc_prepare, |
| 791 | .commit = radeon_crtc_commit, |
| 792 | }; |
| 793 | |
| 794 | |
| 795 | void radeon_legacy_init_crtc(struct drm_device *dev, |
| 796 | struct radeon_crtc *radeon_crtc) |
| 797 | { |
| 798 | if (radeon_crtc->crtc_id == 1) |
| 799 | radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP; |
| 800 | drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs); |
| 801 | } |
| 802 | |
| 803 | void radeon_init_disp_bw_legacy(struct drm_device *dev, |
| 804 | struct drm_display_mode *mode1, |
| 805 | uint32_t pixel_bytes1, |
| 806 | struct drm_display_mode *mode2, |
| 807 | uint32_t pixel_bytes2) |
| 808 | { |
| 809 | struct radeon_device *rdev = dev->dev_private; |
| 810 | fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff; |
| 811 | fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff; |
| 812 | fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff; |
| 813 | uint32_t temp, data, mem_trcd, mem_trp, mem_tras; |
| 814 | fixed20_12 memtcas_ff[8] = { |
| 815 | fixed_init(1), |
| 816 | fixed_init(2), |
| 817 | fixed_init(3), |
| 818 | fixed_init(0), |
| 819 | fixed_init_half(1), |
| 820 | fixed_init_half(2), |
| 821 | fixed_init(0), |
| 822 | }; |
| 823 | fixed20_12 memtcas_rs480_ff[8] = { |
| 824 | fixed_init(0), |
| 825 | fixed_init(1), |
| 826 | fixed_init(2), |
| 827 | fixed_init(3), |
| 828 | fixed_init(0), |
| 829 | fixed_init_half(1), |
| 830 | fixed_init_half(2), |
| 831 | fixed_init_half(3), |
| 832 | }; |
| 833 | fixed20_12 memtcas2_ff[8] = { |
| 834 | fixed_init(0), |
| 835 | fixed_init(1), |
| 836 | fixed_init(2), |
| 837 | fixed_init(3), |
| 838 | fixed_init(4), |
| 839 | fixed_init(5), |
| 840 | fixed_init(6), |
| 841 | fixed_init(7), |
| 842 | }; |
| 843 | fixed20_12 memtrbs[8] = { |
| 844 | fixed_init(1), |
| 845 | fixed_init_half(1), |
| 846 | fixed_init(2), |
| 847 | fixed_init_half(2), |
| 848 | fixed_init(3), |
| 849 | fixed_init_half(3), |
| 850 | fixed_init(4), |
| 851 | fixed_init_half(4) |
| 852 | }; |
| 853 | fixed20_12 memtrbs_r4xx[8] = { |
| 854 | fixed_init(4), |
| 855 | fixed_init(5), |
| 856 | fixed_init(6), |
| 857 | fixed_init(7), |
| 858 | fixed_init(8), |
| 859 | fixed_init(9), |
| 860 | fixed_init(10), |
| 861 | fixed_init(11) |
| 862 | }; |
| 863 | fixed20_12 min_mem_eff; |
| 864 | fixed20_12 mc_latency_sclk, mc_latency_mclk, k1; |
| 865 | fixed20_12 cur_latency_mclk, cur_latency_sclk; |
| 866 | fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate, |
| 867 | disp_drain_rate2, read_return_rate; |
| 868 | fixed20_12 time_disp1_drop_priority; |
| 869 | int c; |
| 870 | int cur_size = 16; /* in octawords */ |
| 871 | int critical_point = 0, critical_point2; |
| 872 | /* uint32_t read_return_rate, time_disp1_drop_priority; */ |
| 873 | int stop_req, max_stop_req; |
| 874 | |
| 875 | min_mem_eff.full = rfixed_const_8(0); |
| 876 | /* get modes */ |
| 877 | if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) { |
| 878 | uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER); |
| 879 | mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT); |
| 880 | mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT); |
| 881 | /* check crtc enables */ |
| 882 | if (mode2) |
| 883 | mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT); |
| 884 | if (mode1) |
| 885 | mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT); |
| 886 | WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); |
| 887 | } |
| 888 | |
| 889 | /* |
| 890 | * determine is there is enough bw for current mode |
| 891 | */ |
| 892 | mclk_ff.full = rfixed_const(rdev->clock.default_mclk); |
| 893 | temp_ff.full = rfixed_const(100); |
| 894 | mclk_ff.full = rfixed_div(mclk_ff, temp_ff); |
| 895 | sclk_ff.full = rfixed_const(rdev->clock.default_sclk); |
| 896 | sclk_ff.full = rfixed_div(sclk_ff, temp_ff); |
| 897 | |
| 898 | temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1); |
| 899 | temp_ff.full = rfixed_const(temp); |
| 900 | mem_bw.full = rfixed_mul(mclk_ff, temp_ff); |
| 901 | |
| 902 | pix_clk.full = 0; |
| 903 | pix_clk2.full = 0; |
| 904 | peak_disp_bw.full = 0; |
| 905 | if (mode1) { |
| 906 | temp_ff.full = rfixed_const(1000); |
| 907 | pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */ |
| 908 | pix_clk.full = rfixed_div(pix_clk, temp_ff); |
| 909 | temp_ff.full = rfixed_const(pixel_bytes1); |
| 910 | peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff); |
| 911 | } |
| 912 | if (mode2) { |
| 913 | temp_ff.full = rfixed_const(1000); |
| 914 | pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */ |
| 915 | pix_clk2.full = rfixed_div(pix_clk2, temp_ff); |
| 916 | temp_ff.full = rfixed_const(pixel_bytes2); |
| 917 | peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff); |
| 918 | } |
| 919 | |
| 920 | mem_bw.full = rfixed_mul(mem_bw, min_mem_eff); |
| 921 | if (peak_disp_bw.full >= mem_bw.full) { |
| 922 | DRM_ERROR("You may not have enough display bandwidth for current mode\n" |
| 923 | "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); |
| 924 | } |
| 925 | |
| 926 | /* Get values from the EXT_MEM_CNTL register...converting its contents. */ |
| 927 | temp = RREG32(RADEON_MEM_TIMING_CNTL); |
| 928 | if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */ |
| 929 | mem_trcd = ((temp >> 2) & 0x3) + 1; |
| 930 | mem_trp = ((temp & 0x3)) + 1; |
| 931 | mem_tras = ((temp & 0x70) >> 4) + 1; |
| 932 | } else if (rdev->family == CHIP_R300 || |
| 933 | rdev->family == CHIP_R350) { /* r300, r350 */ |
| 934 | mem_trcd = (temp & 0x7) + 1; |
| 935 | mem_trp = ((temp >> 8) & 0x7) + 1; |
| 936 | mem_tras = ((temp >> 11) & 0xf) + 4; |
| 937 | } else if (rdev->family == CHIP_RV350 || |
| 938 | rdev->family <= CHIP_RV380) { |
| 939 | /* rv3x0 */ |
| 940 | mem_trcd = (temp & 0x7) + 3; |
| 941 | mem_trp = ((temp >> 8) & 0x7) + 3; |
| 942 | mem_tras = ((temp >> 11) & 0xf) + 6; |
| 943 | } else if (rdev->family == CHIP_R420 || |
| 944 | rdev->family == CHIP_R423 || |
| 945 | rdev->family == CHIP_RV410) { |
| 946 | /* r4xx */ |
| 947 | mem_trcd = (temp & 0xf) + 3; |
| 948 | if (mem_trcd > 15) |
| 949 | mem_trcd = 15; |
| 950 | mem_trp = ((temp >> 8) & 0xf) + 3; |
| 951 | if (mem_trp > 15) |
| 952 | mem_trp = 15; |
| 953 | mem_tras = ((temp >> 12) & 0x1f) + 6; |
| 954 | if (mem_tras > 31) |
| 955 | mem_tras = 31; |
| 956 | } else { /* RV200, R200 */ |
| 957 | mem_trcd = (temp & 0x7) + 1; |
| 958 | mem_trp = ((temp >> 8) & 0x7) + 1; |
| 959 | mem_tras = ((temp >> 12) & 0xf) + 4; |
| 960 | } |
| 961 | /* convert to FF */ |
| 962 | trcd_ff.full = rfixed_const(mem_trcd); |
| 963 | trp_ff.full = rfixed_const(mem_trp); |
| 964 | tras_ff.full = rfixed_const(mem_tras); |
| 965 | |
| 966 | /* Get values from the MEM_SDRAM_MODE_REG register...converting its */ |
| 967 | temp = RREG32(RADEON_MEM_SDRAM_MODE_REG); |
| 968 | data = (temp & (7 << 20)) >> 20; |
| 969 | if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) { |
| 970 | if (rdev->family == CHIP_RS480) /* don't think rs400 */ |
| 971 | tcas_ff = memtcas_rs480_ff[data]; |
| 972 | else |
| 973 | tcas_ff = memtcas_ff[data]; |
| 974 | } else |
| 975 | tcas_ff = memtcas2_ff[data]; |
| 976 | |
| 977 | if (rdev->family == CHIP_RS400 || |
| 978 | rdev->family == CHIP_RS480) { |
| 979 | /* extra cas latency stored in bits 23-25 0-4 clocks */ |
| 980 | data = (temp >> 23) & 0x7; |
| 981 | if (data < 5) |
| 982 | tcas_ff.full += rfixed_const(data); |
| 983 | } |
| 984 | |
| 985 | if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) { |
| 986 | /* on the R300, Tcas is included in Trbs. |
| 987 | */ |
| 988 | temp = RREG32(RADEON_MEM_CNTL); |
| 989 | data = (R300_MEM_NUM_CHANNELS_MASK & temp); |
| 990 | if (data == 1) { |
| 991 | if (R300_MEM_USE_CD_CH_ONLY & temp) { |
| 992 | temp = RREG32(R300_MC_IND_INDEX); |
| 993 | temp &= ~R300_MC_IND_ADDR_MASK; |
| 994 | temp |= R300_MC_READ_CNTL_CD_mcind; |
| 995 | WREG32(R300_MC_IND_INDEX, temp); |
| 996 | temp = RREG32(R300_MC_IND_DATA); |
| 997 | data = (R300_MEM_RBS_POSITION_C_MASK & temp); |
| 998 | } else { |
| 999 | temp = RREG32(R300_MC_READ_CNTL_AB); |
| 1000 | data = (R300_MEM_RBS_POSITION_A_MASK & temp); |
| 1001 | } |
| 1002 | } else { |
| 1003 | temp = RREG32(R300_MC_READ_CNTL_AB); |
| 1004 | data = (R300_MEM_RBS_POSITION_A_MASK & temp); |
| 1005 | } |
| 1006 | if (rdev->family == CHIP_RV410 || |
| 1007 | rdev->family == CHIP_R420 || |
| 1008 | rdev->family == CHIP_R423) |
| 1009 | trbs_ff = memtrbs_r4xx[data]; |
| 1010 | else |
| 1011 | trbs_ff = memtrbs[data]; |
| 1012 | tcas_ff.full += trbs_ff.full; |
| 1013 | } |
| 1014 | |
| 1015 | sclk_eff_ff.full = sclk_ff.full; |
| 1016 | |
| 1017 | if (rdev->flags & RADEON_IS_AGP) { |
| 1018 | fixed20_12 agpmode_ff; |
| 1019 | agpmode_ff.full = rfixed_const(radeon_agpmode); |
| 1020 | temp_ff.full = rfixed_const_666(16); |
| 1021 | sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff); |
| 1022 | } |
| 1023 | /* TODO PCIE lanes may affect this - agpmode == 16?? */ |
| 1024 | |
| 1025 | if (ASIC_IS_R300(rdev)) { |
| 1026 | sclk_delay_ff.full = rfixed_const(250); |
| 1027 | } else { |
| 1028 | if ((rdev->family == CHIP_RV100) || |
| 1029 | rdev->flags & RADEON_IS_IGP) { |
| 1030 | if (rdev->mc.vram_is_ddr) |
| 1031 | sclk_delay_ff.full = rfixed_const(41); |
| 1032 | else |
| 1033 | sclk_delay_ff.full = rfixed_const(33); |
| 1034 | } else { |
| 1035 | if (rdev->mc.vram_width == 128) |
| 1036 | sclk_delay_ff.full = rfixed_const(57); |
| 1037 | else |
| 1038 | sclk_delay_ff.full = rfixed_const(41); |
| 1039 | } |
| 1040 | } |
| 1041 | |
| 1042 | mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff); |
| 1043 | |
| 1044 | if (rdev->mc.vram_is_ddr) { |
| 1045 | if (rdev->mc.vram_width == 32) { |
| 1046 | k1.full = rfixed_const(40); |
| 1047 | c = 3; |
| 1048 | } else { |
| 1049 | k1.full = rfixed_const(20); |
| 1050 | c = 1; |
| 1051 | } |
| 1052 | } else { |
| 1053 | k1.full = rfixed_const(40); |
| 1054 | c = 3; |
| 1055 | } |
| 1056 | |
| 1057 | temp_ff.full = rfixed_const(2); |
| 1058 | mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff); |
| 1059 | temp_ff.full = rfixed_const(c); |
| 1060 | mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff); |
| 1061 | temp_ff.full = rfixed_const(4); |
| 1062 | mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff); |
| 1063 | mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff); |
| 1064 | mc_latency_mclk.full += k1.full; |
| 1065 | |
| 1066 | mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff); |
| 1067 | mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff); |
| 1068 | |
| 1069 | /* |
| 1070 | HW cursor time assuming worst case of full size colour cursor. |
| 1071 | */ |
| 1072 | temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1)))); |
| 1073 | temp_ff.full += trcd_ff.full; |
| 1074 | if (temp_ff.full < tras_ff.full) |
| 1075 | temp_ff.full = tras_ff.full; |
| 1076 | cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff); |
| 1077 | |
| 1078 | temp_ff.full = rfixed_const(cur_size); |
| 1079 | cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff); |
| 1080 | /* |
| 1081 | Find the total latency for the display data. |
| 1082 | */ |
| 1083 | disp_latency_overhead.full = rfixed_const(80); |
| 1084 | disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff); |
| 1085 | mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full; |
| 1086 | mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full; |
| 1087 | |
| 1088 | if (mc_latency_mclk.full > mc_latency_sclk.full) |
| 1089 | disp_latency.full = mc_latency_mclk.full; |
| 1090 | else |
| 1091 | disp_latency.full = mc_latency_sclk.full; |
| 1092 | |
| 1093 | /* setup Max GRPH_STOP_REQ default value */ |
| 1094 | if (ASIC_IS_RV100(rdev)) |
| 1095 | max_stop_req = 0x5c; |
| 1096 | else |
| 1097 | max_stop_req = 0x7c; |
| 1098 | |
| 1099 | if (mode1) { |
| 1100 | /* CRTC1 |
| 1101 | Set GRPH_BUFFER_CNTL register using h/w defined optimal values. |
| 1102 | GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ] |
| 1103 | */ |
| 1104 | stop_req = mode1->hdisplay * pixel_bytes1 / 16; |
| 1105 | |
| 1106 | if (stop_req > max_stop_req) |
| 1107 | stop_req = max_stop_req; |
| 1108 | |
| 1109 | /* |
| 1110 | Find the drain rate of the display buffer. |
| 1111 | */ |
| 1112 | temp_ff.full = rfixed_const((16/pixel_bytes1)); |
| 1113 | disp_drain_rate.full = rfixed_div(pix_clk, temp_ff); |
| 1114 | |
| 1115 | /* |
| 1116 | Find the critical point of the display buffer. |
| 1117 | */ |
| 1118 | crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency); |
| 1119 | crit_point_ff.full += rfixed_const_half(0); |
| 1120 | |
| 1121 | critical_point = rfixed_trunc(crit_point_ff); |
| 1122 | |
| 1123 | if (rdev->disp_priority == 2) { |
| 1124 | critical_point = 0; |
| 1125 | } |
| 1126 | |
| 1127 | /* |
| 1128 | The critical point should never be above max_stop_req-4. Setting |
| 1129 | GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time. |
| 1130 | */ |
| 1131 | if (max_stop_req - critical_point < 4) |
| 1132 | critical_point = 0; |
| 1133 | |
| 1134 | if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) { |
| 1135 | /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/ |
| 1136 | critical_point = 0x10; |
| 1137 | } |
| 1138 | |
| 1139 | temp = RREG32(RADEON_GRPH_BUFFER_CNTL); |
| 1140 | temp &= ~(RADEON_GRPH_STOP_REQ_MASK); |
| 1141 | temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); |
| 1142 | temp &= ~(RADEON_GRPH_START_REQ_MASK); |
| 1143 | if ((rdev->family == CHIP_R350) && |
| 1144 | (stop_req > 0x15)) { |
| 1145 | stop_req -= 0x10; |
| 1146 | } |
| 1147 | temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); |
| 1148 | temp |= RADEON_GRPH_BUFFER_SIZE; |
| 1149 | temp &= ~(RADEON_GRPH_CRITICAL_CNTL | |
| 1150 | RADEON_GRPH_CRITICAL_AT_SOF | |
| 1151 | RADEON_GRPH_STOP_CNTL); |
| 1152 | /* |
| 1153 | Write the result into the register. |
| 1154 | */ |
| 1155 | WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | |
| 1156 | (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT))); |
| 1157 | |
| 1158 | #if 0 |
| 1159 | if ((rdev->family == CHIP_RS400) || |
| 1160 | (rdev->family == CHIP_RS480)) { |
| 1161 | /* attempt to program RS400 disp regs correctly ??? */ |
| 1162 | temp = RREG32(RS400_DISP1_REG_CNTL); |
| 1163 | temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK | |
| 1164 | RS400_DISP1_STOP_REQ_LEVEL_MASK); |
| 1165 | WREG32(RS400_DISP1_REQ_CNTL1, (temp | |
| 1166 | (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) | |
| 1167 | (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); |
| 1168 | temp = RREG32(RS400_DMIF_MEM_CNTL1); |
| 1169 | temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK | |
| 1170 | RS400_DISP1_CRITICAL_POINT_STOP_MASK); |
| 1171 | WREG32(RS400_DMIF_MEM_CNTL1, (temp | |
| 1172 | (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) | |
| 1173 | (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT))); |
| 1174 | } |
| 1175 | #endif |
| 1176 | |
| 1177 | DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n", |
| 1178 | /* (unsigned int)info->SavedReg->grph_buffer_cntl, */ |
| 1179 | (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL)); |
| 1180 | } |
| 1181 | |
| 1182 | if (mode2) { |
| 1183 | u32 grph2_cntl; |
| 1184 | stop_req = mode2->hdisplay * pixel_bytes2 / 16; |
| 1185 | |
| 1186 | if (stop_req > max_stop_req) |
| 1187 | stop_req = max_stop_req; |
| 1188 | |
| 1189 | /* |
| 1190 | Find the drain rate of the display buffer. |
| 1191 | */ |
| 1192 | temp_ff.full = rfixed_const((16/pixel_bytes2)); |
| 1193 | disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff); |
| 1194 | |
| 1195 | grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL); |
| 1196 | grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK); |
| 1197 | grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); |
| 1198 | grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK); |
| 1199 | if ((rdev->family == CHIP_R350) && |
| 1200 | (stop_req > 0x15)) { |
| 1201 | stop_req -= 0x10; |
| 1202 | } |
| 1203 | grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); |
| 1204 | grph2_cntl |= RADEON_GRPH_BUFFER_SIZE; |
| 1205 | grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL | |
| 1206 | RADEON_GRPH_CRITICAL_AT_SOF | |
| 1207 | RADEON_GRPH_STOP_CNTL); |
| 1208 | |
| 1209 | if ((rdev->family == CHIP_RS100) || |
| 1210 | (rdev->family == CHIP_RS200)) |
| 1211 | critical_point2 = 0; |
| 1212 | else { |
| 1213 | temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128; |
| 1214 | temp_ff.full = rfixed_const(temp); |
| 1215 | temp_ff.full = rfixed_mul(mclk_ff, temp_ff); |
| 1216 | if (sclk_ff.full < temp_ff.full) |
| 1217 | temp_ff.full = sclk_ff.full; |
| 1218 | |
| 1219 | read_return_rate.full = temp_ff.full; |
| 1220 | |
| 1221 | if (mode1) { |
| 1222 | temp_ff.full = read_return_rate.full - disp_drain_rate.full; |
| 1223 | time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff); |
| 1224 | } else { |
| 1225 | time_disp1_drop_priority.full = 0; |
| 1226 | } |
| 1227 | crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full; |
| 1228 | crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2); |
| 1229 | crit_point_ff.full += rfixed_const_half(0); |
| 1230 | |
| 1231 | critical_point2 = rfixed_trunc(crit_point_ff); |
| 1232 | |
| 1233 | if (rdev->disp_priority == 2) { |
| 1234 | critical_point2 = 0; |
| 1235 | } |
| 1236 | |
| 1237 | if (max_stop_req - critical_point2 < 4) |
| 1238 | critical_point2 = 0; |
| 1239 | |
| 1240 | } |
| 1241 | |
| 1242 | if (critical_point2 == 0 && rdev->family == CHIP_R300) { |
| 1243 | /* some R300 cards have problem with this set to 0 */ |
| 1244 | critical_point2 = 0x10; |
| 1245 | } |
| 1246 | |
| 1247 | WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) | |
| 1248 | (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT))); |
| 1249 | |
| 1250 | if ((rdev->family == CHIP_RS400) || |
| 1251 | (rdev->family == CHIP_RS480)) { |
| 1252 | #if 0 |
| 1253 | /* attempt to program RS400 disp2 regs correctly ??? */ |
| 1254 | temp = RREG32(RS400_DISP2_REQ_CNTL1); |
| 1255 | temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK | |
| 1256 | RS400_DISP2_STOP_REQ_LEVEL_MASK); |
| 1257 | WREG32(RS400_DISP2_REQ_CNTL1, (temp | |
| 1258 | (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) | |
| 1259 | (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); |
| 1260 | temp = RREG32(RS400_DISP2_REQ_CNTL2); |
| 1261 | temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK | |
| 1262 | RS400_DISP2_CRITICAL_POINT_STOP_MASK); |
| 1263 | WREG32(RS400_DISP2_REQ_CNTL2, (temp | |
| 1264 | (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) | |
| 1265 | (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT))); |
| 1266 | #endif |
| 1267 | WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC); |
| 1268 | WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000); |
| 1269 | WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC); |
| 1270 | WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC); |
| 1271 | } |
| 1272 | |
| 1273 | DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n", |
| 1274 | (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL)); |
| 1275 | } |
| 1276 | } |