Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/boot/compressed/head.S |
| 3 | * |
| 4 | * Copyright (C) 1996-2002 Russell King |
Hyok S. Choi | 10c2df6 | 2006-03-27 10:21:34 +0100 | [diff] [blame] | 5 | * Copyright (C) 2004 Hyok S. Choi (MPU support) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 11 | #include <linux/linkage.h> |
| 12 | |
| 13 | /* |
| 14 | * Debugging stuff |
| 15 | * |
| 16 | * Note that these macros must not contain any code which is not |
| 17 | * 100% relocatable. Any attempt to do so will result in a crash. |
| 18 | * Please select one of the following when turning on debugging. |
| 19 | */ |
| 20 | #ifdef DEBUG |
Russell King | 5cd0c34 | 2005-05-03 12:18:46 +0100 | [diff] [blame] | 21 | |
Russell King | 5cd0c34 | 2005-05-03 12:18:46 +0100 | [diff] [blame] | 22 | #if defined(CONFIG_DEBUG_ICEDCC) |
Tony Lindgren | 7d95ded | 2006-09-20 13:03:34 +0100 | [diff] [blame] | 23 | |
| 24 | #ifdef CONFIG_CPU_V6 |
| 25 | .macro loadsp, rb |
| 26 | .endm |
| 27 | .macro writeb, ch, rb |
| 28 | mcr p14, 0, \ch, c0, c5, 0 |
| 29 | .endm |
Jean-Christop PLAGNIOL-VILLARD | c633c3c | 2009-02-25 04:20:40 +0100 | [diff] [blame] | 30 | #elif defined(CONFIG_CPU_XSCALE) |
| 31 | .macro loadsp, rb |
| 32 | .endm |
| 33 | .macro writeb, ch, rb |
| 34 | mcr p14, 0, \ch, c8, c0, 0 |
| 35 | .endm |
Tony Lindgren | 7d95ded | 2006-09-20 13:03:34 +0100 | [diff] [blame] | 36 | #else |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 37 | .macro loadsp, rb |
| 38 | .endm |
Russell King | 224b5be | 2005-11-16 14:59:51 +0000 | [diff] [blame] | 39 | .macro writeb, ch, rb |
Uwe Kleine-König | 41a9e68 | 2007-12-13 09:31:34 +0100 | [diff] [blame] | 40 | mcr p14, 0, \ch, c1, c0, 0 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 41 | .endm |
Tony Lindgren | 7d95ded | 2006-09-20 13:03:34 +0100 | [diff] [blame] | 42 | #endif |
| 43 | |
Russell King | 5cd0c34 | 2005-05-03 12:18:46 +0100 | [diff] [blame] | 44 | #else |
Russell King | 224b5be | 2005-11-16 14:59:51 +0000 | [diff] [blame] | 45 | |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 46 | #include <mach/debug-macro.S> |
Russell King | 224b5be | 2005-11-16 14:59:51 +0000 | [diff] [blame] | 47 | |
Russell King | 5cd0c34 | 2005-05-03 12:18:46 +0100 | [diff] [blame] | 48 | .macro writeb, ch, rb |
| 49 | senduart \ch, \rb |
| 50 | .endm |
| 51 | |
Russell King | 224b5be | 2005-11-16 14:59:51 +0000 | [diff] [blame] | 52 | #if defined(CONFIG_ARCH_SA1100) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 53 | .macro loadsp, rb |
| 54 | mov \rb, #0x80000000 @ physical base address |
Russell King | 224b5be | 2005-11-16 14:59:51 +0000 | [diff] [blame] | 55 | #ifdef CONFIG_DEBUG_LL_SER3 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 56 | add \rb, \rb, #0x00050000 @ Ser3 |
Russell King | 224b5be | 2005-11-16 14:59:51 +0000 | [diff] [blame] | 57 | #else |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 58 | add \rb, \rb, #0x00010000 @ Ser1 |
Russell King | 224b5be | 2005-11-16 14:59:51 +0000 | [diff] [blame] | 59 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 60 | .endm |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 61 | #elif defined(CONFIG_ARCH_S3C2410) |
Russell King | 5cd0c34 | 2005-05-03 12:18:46 +0100 | [diff] [blame] | 62 | .macro loadsp, rb |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 63 | mov \rb, #0x50000000 |
Ben Dooks | c765784 | 2007-07-22 16:11:20 +0100 | [diff] [blame] | 64 | add \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 65 | .endm |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 66 | #else |
Russell King | 224b5be | 2005-11-16 14:59:51 +0000 | [diff] [blame] | 67 | .macro loadsp, rb |
| 68 | addruart \rb |
| 69 | .endm |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 70 | #endif |
| 71 | #endif |
Russell King | 5cd0c34 | 2005-05-03 12:18:46 +0100 | [diff] [blame] | 72 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 73 | |
| 74 | .macro kputc,val |
| 75 | mov r0, \val |
| 76 | bl putc |
| 77 | .endm |
| 78 | |
| 79 | .macro kphex,val,len |
| 80 | mov r0, \val |
| 81 | mov r1, #\len |
| 82 | bl phex |
| 83 | .endm |
| 84 | |
| 85 | .macro debug_reloc_start |
| 86 | #ifdef DEBUG |
| 87 | kputc #'\n' |
| 88 | kphex r6, 8 /* processor id */ |
| 89 | kputc #':' |
| 90 | kphex r7, 8 /* architecture id */ |
Hyok S. Choi | f12d0d7 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 91 | #ifdef CONFIG_CPU_CP15 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 92 | kputc #':' |
| 93 | mrc p15, 0, r0, c1, c0 |
| 94 | kphex r0, 8 /* control reg */ |
Hyok S. Choi | f12d0d7 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 95 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 96 | kputc #'\n' |
| 97 | kphex r5, 8 /* decompressed kernel start */ |
| 98 | kputc #'-' |
Russell King | f461902 | 2006-01-12 17:17:57 +0000 | [diff] [blame] | 99 | kphex r9, 8 /* decompressed kernel end */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 100 | kputc #'>' |
| 101 | kphex r4, 8 /* kernel execution address */ |
| 102 | kputc #'\n' |
| 103 | #endif |
| 104 | .endm |
| 105 | |
| 106 | .macro debug_reloc_end |
| 107 | #ifdef DEBUG |
| 108 | kphex r5, 8 /* end of kernel */ |
| 109 | kputc #'\n' |
| 110 | mov r0, r4 |
| 111 | bl memdump /* dump 256 bytes at start of kernel */ |
| 112 | #endif |
| 113 | .endm |
| 114 | |
| 115 | .section ".start", #alloc, #execinstr |
| 116 | /* |
| 117 | * sort out different calling conventions |
| 118 | */ |
| 119 | .align |
| 120 | start: |
| 121 | .type start,#function |
| 122 | .rept 8 |
| 123 | mov r0, r0 |
| 124 | .endr |
| 125 | |
| 126 | b 1f |
| 127 | .word 0x016f2818 @ Magic numbers to help the loader |
| 128 | .word start @ absolute load/run zImage address |
| 129 | .word _edata @ zImage end address |
| 130 | 1: mov r7, r1 @ save architecture ID |
Russell King | f461902 | 2006-01-12 17:17:57 +0000 | [diff] [blame] | 131 | mov r8, r2 @ save atags pointer |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 132 | |
| 133 | #ifndef __ARM_ARCH_2__ |
| 134 | /* |
| 135 | * Booting from Angel - need to enter SVC mode and disable |
| 136 | * FIQs/IRQs (numeric definitions from angel arm.h source). |
| 137 | * We only do this if we were in user mode on entry. |
| 138 | */ |
| 139 | mrs r2, cpsr @ get current mode |
| 140 | tst r2, #3 @ not user? |
| 141 | bne not_angel |
| 142 | mov r0, #0x17 @ angel_SWIreason_EnterSVC |
Catalin Marinas | 0e056f2 | 2009-07-24 12:32:58 +0100 | [diff] [blame] | 143 | ARM( swi 0x123456 ) @ angel_SWI_ARM |
| 144 | THUMB( svc 0xab ) @ angel_SWI_THUMB |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 145 | not_angel: |
| 146 | mrs r2, cpsr @ turn off interrupts to |
| 147 | orr r2, r2, #0xc0 @ prevent angel from running |
| 148 | msr cpsr_c, r2 |
| 149 | #else |
| 150 | teqp pc, #0x0c000003 @ turn off interrupts |
| 151 | #endif |
| 152 | |
| 153 | /* |
| 154 | * Note that some cache flushing and other stuff may |
| 155 | * be needed here - is there an Angel SWI call for this? |
| 156 | */ |
| 157 | |
| 158 | /* |
| 159 | * some architecture specific code can be inserted |
Russell King | f461902 | 2006-01-12 17:17:57 +0000 | [diff] [blame] | 160 | * by the linker here, but it should preserve r7, r8, and r9. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 161 | */ |
| 162 | |
| 163 | .text |
| 164 | adr r0, LC0 |
Catalin Marinas | 0e056f2 | 2009-07-24 12:32:58 +0100 | [diff] [blame] | 165 | ARM( ldmia r0, {r1, r2, r3, r4, r5, r6, ip, sp} ) |
| 166 | THUMB( ldmia r0, {r1, r2, r3, r4, r5, r6, ip} ) |
| 167 | THUMB( ldr sp, [r0, #28] ) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 168 | subs r0, r0, r1 @ calculate the delta offset |
| 169 | |
| 170 | @ if delta is zero, we are |
| 171 | beq not_relocated @ running at the address we |
| 172 | @ were linked at. |
| 173 | |
| 174 | /* |
| 175 | * We're running at a different address. We need to fix |
| 176 | * up various pointers: |
| 177 | * r5 - zImage base address |
| 178 | * r6 - GOT start |
| 179 | * ip - GOT end |
| 180 | */ |
| 181 | add r5, r5, r0 |
| 182 | add r6, r6, r0 |
| 183 | add ip, ip, r0 |
| 184 | |
| 185 | #ifndef CONFIG_ZBOOT_ROM |
| 186 | /* |
| 187 | * If we're running fully PIC === CONFIG_ZBOOT_ROM = n, |
| 188 | * we need to fix up pointers into the BSS region. |
| 189 | * r2 - BSS start |
| 190 | * r3 - BSS end |
| 191 | * sp - stack pointer |
| 192 | */ |
| 193 | add r2, r2, r0 |
| 194 | add r3, r3, r0 |
| 195 | add sp, sp, r0 |
| 196 | |
| 197 | /* |
| 198 | * Relocate all entries in the GOT table. |
| 199 | */ |
| 200 | 1: ldr r1, [r6, #0] @ relocate entries in the GOT |
| 201 | add r1, r1, r0 @ table. This fixes up the |
| 202 | str r1, [r6], #4 @ C references. |
| 203 | cmp r6, ip |
| 204 | blo 1b |
| 205 | #else |
| 206 | |
| 207 | /* |
| 208 | * Relocate entries in the GOT table. We only relocate |
| 209 | * the entries that are outside the (relocated) BSS region. |
| 210 | */ |
| 211 | 1: ldr r1, [r6, #0] @ relocate entries in the GOT |
| 212 | cmp r1, r2 @ entry < bss_start || |
| 213 | cmphs r3, r1 @ _end < entry |
| 214 | addlo r1, r1, r0 @ table. This fixes up the |
| 215 | str r1, [r6], #4 @ C references. |
| 216 | cmp r6, ip |
| 217 | blo 1b |
| 218 | #endif |
| 219 | |
| 220 | not_relocated: mov r0, #0 |
| 221 | 1: str r0, [r2], #4 @ clear bss |
| 222 | str r0, [r2], #4 |
| 223 | str r0, [r2], #4 |
| 224 | str r0, [r2], #4 |
| 225 | cmp r2, r3 |
| 226 | blo 1b |
| 227 | |
| 228 | /* |
| 229 | * The C runtime environment should now be setup |
| 230 | * sufficiently. Turn the cache on, set up some |
| 231 | * pointers, and start decompressing. |
| 232 | */ |
| 233 | bl cache_on |
| 234 | |
| 235 | mov r1, sp @ malloc space above stack |
| 236 | add r2, sp, #0x10000 @ 64k max |
| 237 | |
| 238 | /* |
| 239 | * Check to see if we will overwrite ourselves. |
| 240 | * r4 = final kernel address |
| 241 | * r5 = start of this image |
| 242 | * r2 = end of malloc space (and therefore this image) |
| 243 | * We basically want: |
| 244 | * r4 >= r2 -> OK |
| 245 | * r4 + image length <= r5 -> OK |
| 246 | */ |
| 247 | cmp r4, r2 |
| 248 | bhs wont_overwrite |
Lennert Buytenhek | 2552fc2 | 2006-09-29 21:14:05 +0100 | [diff] [blame] | 249 | sub r3, sp, r5 @ > compressed kernel size |
| 250 | add r0, r4, r3, lsl #2 @ allow for 4x expansion |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 251 | cmp r0, r5 |
| 252 | bls wont_overwrite |
| 253 | |
| 254 | mov r5, r2 @ decompress after malloc space |
| 255 | mov r0, r5 |
| 256 | mov r3, r7 |
| 257 | bl decompress_kernel |
| 258 | |
Catalin Marinas | c7341d4 | 2007-06-01 17:13:59 +0100 | [diff] [blame] | 259 | add r0, r0, #127 + 128 @ alignment + stack |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 260 | bic r0, r0, #127 @ align the kernel length |
| 261 | /* |
| 262 | * r0 = decompressed kernel length |
| 263 | * r1-r3 = unused |
| 264 | * r4 = kernel execution address |
| 265 | * r5 = decompressed kernel start |
| 266 | * r6 = processor ID |
| 267 | * r7 = architecture ID |
Russell King | f461902 | 2006-01-12 17:17:57 +0000 | [diff] [blame] | 268 | * r8 = atags pointer |
Catalin Marinas | 0e056f2 | 2009-07-24 12:32:58 +0100 | [diff] [blame] | 269 | * r9-r12,r14 = corrupted |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 270 | */ |
| 271 | add r1, r5, r0 @ end of decompressed kernel |
| 272 | adr r2, reloc_start |
| 273 | ldr r3, LC1 |
| 274 | add r3, r2, r3 |
Catalin Marinas | 0e056f2 | 2009-07-24 12:32:58 +0100 | [diff] [blame] | 275 | 1: ldmia r2!, {r9 - r12, r14} @ copy relocation code |
| 276 | stmia r1!, {r9 - r12, r14} |
| 277 | ldmia r2!, {r9 - r12, r14} |
| 278 | stmia r1!, {r9 - r12, r14} |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 279 | cmp r2, r3 |
| 280 | blo 1b |
Catalin Marinas | 0e056f2 | 2009-07-24 12:32:58 +0100 | [diff] [blame] | 281 | mov sp, r1 |
| 282 | add sp, sp, #128 @ relocate the stack |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 283 | |
| 284 | bl cache_clean_flush |
Catalin Marinas | 0e056f2 | 2009-07-24 12:32:58 +0100 | [diff] [blame] | 285 | ARM( add pc, r5, r0 ) @ call relocation code |
| 286 | THUMB( add r12, r5, r0 ) |
| 287 | THUMB( mov pc, r12 ) @ call relocation code |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 288 | |
| 289 | /* |
| 290 | * We're not in danger of overwriting ourselves. Do this the simple way. |
| 291 | * |
| 292 | * r4 = kernel execution address |
| 293 | * r7 = architecture ID |
| 294 | */ |
| 295 | wont_overwrite: mov r0, r4 |
| 296 | mov r3, r7 |
| 297 | bl decompress_kernel |
| 298 | b call_kernel |
| 299 | |
Catalin Marinas | 88987ef | 2009-07-24 12:32:52 +0100 | [diff] [blame] | 300 | .align 2 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 301 | .type LC0, #object |
| 302 | LC0: .word LC0 @ r1 |
| 303 | .word __bss_start @ r2 |
| 304 | .word _end @ r3 |
| 305 | .word zreladdr @ r4 |
| 306 | .word _start @ r5 |
| 307 | .word _got_start @ r6 |
| 308 | .word _got_end @ ip |
| 309 | .word user_stack+4096 @ sp |
| 310 | LC1: .word reloc_end - reloc_start |
| 311 | .size LC0, . - LC0 |
| 312 | |
| 313 | #ifdef CONFIG_ARCH_RPC |
| 314 | .globl params |
| 315 | params: ldr r0, =params_phys |
| 316 | mov pc, lr |
| 317 | .ltorg |
| 318 | .align |
| 319 | #endif |
| 320 | |
| 321 | /* |
| 322 | * Turn on the cache. We need to setup some page tables so that we |
| 323 | * can have both the I and D caches on. |
| 324 | * |
| 325 | * We place the page tables 16k down from the kernel execution address, |
| 326 | * and we hope that nothing else is using it. If we're using it, we |
| 327 | * will go pop! |
| 328 | * |
| 329 | * On entry, |
| 330 | * r4 = kernel execution address |
| 331 | * r6 = processor ID |
| 332 | * r7 = architecture number |
Russell King | f461902 | 2006-01-12 17:17:57 +0000 | [diff] [blame] | 333 | * r8 = atags pointer |
| 334 | * r9 = run-time address of "start" (???) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 335 | * On exit, |
Russell King | f461902 | 2006-01-12 17:17:57 +0000 | [diff] [blame] | 336 | * r1, r2, r3, r9, r10, r12 corrupted |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 337 | * This routine must preserve: |
Russell King | f461902 | 2006-01-12 17:17:57 +0000 | [diff] [blame] | 338 | * r4, r5, r6, r7, r8 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 339 | */ |
| 340 | .align 5 |
| 341 | cache_on: mov r3, #8 @ cache_on function |
| 342 | b call_cache_fn |
| 343 | |
Hyok S. Choi | 10c2df6 | 2006-03-27 10:21:34 +0100 | [diff] [blame] | 344 | /* |
| 345 | * Initialize the highest priority protection region, PR7 |
| 346 | * to cover all 32bit address and cacheable and bufferable. |
| 347 | */ |
| 348 | __armv4_mpu_cache_on: |
| 349 | mov r0, #0x3f @ 4G, the whole |
| 350 | mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting |
| 351 | mcr p15, 0, r0, c6, c7, 1 |
| 352 | |
| 353 | mov r0, #0x80 @ PR7 |
| 354 | mcr p15, 0, r0, c2, c0, 0 @ D-cache on |
| 355 | mcr p15, 0, r0, c2, c0, 1 @ I-cache on |
| 356 | mcr p15, 0, r0, c3, c0, 0 @ write-buffer on |
| 357 | |
| 358 | mov r0, #0xc000 |
| 359 | mcr p15, 0, r0, c5, c0, 1 @ I-access permission |
| 360 | mcr p15, 0, r0, c5, c0, 0 @ D-access permission |
| 361 | |
| 362 | mov r0, #0 |
| 363 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer |
| 364 | mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache |
| 365 | mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache |
| 366 | mrc p15, 0, r0, c1, c0, 0 @ read control reg |
| 367 | @ ...I .... ..D. WC.M |
| 368 | orr r0, r0, #0x002d @ .... .... ..1. 11.1 |
| 369 | orr r0, r0, #0x1000 @ ...1 .... .... .... |
| 370 | |
| 371 | mcr p15, 0, r0, c1, c0, 0 @ write control reg |
| 372 | |
| 373 | mov r0, #0 |
| 374 | mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache |
| 375 | mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache |
| 376 | mov pc, lr |
| 377 | |
| 378 | __armv3_mpu_cache_on: |
| 379 | mov r0, #0x3f @ 4G, the whole |
| 380 | mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting |
| 381 | |
| 382 | mov r0, #0x80 @ PR7 |
| 383 | mcr p15, 0, r0, c2, c0, 0 @ cache on |
| 384 | mcr p15, 0, r0, c3, c0, 0 @ write-buffer on |
| 385 | |
| 386 | mov r0, #0xc000 |
| 387 | mcr p15, 0, r0, c5, c0, 0 @ access permission |
| 388 | |
| 389 | mov r0, #0 |
| 390 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 |
| 391 | mrc p15, 0, r0, c1, c0, 0 @ read control reg |
| 392 | @ .... .... .... WC.M |
| 393 | orr r0, r0, #0x000d @ .... .... .... 11.1 |
| 394 | mov r0, #0 |
| 395 | mcr p15, 0, r0, c1, c0, 0 @ write control reg |
| 396 | |
| 397 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 |
| 398 | mov pc, lr |
| 399 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 400 | __setup_mmu: sub r3, r4, #16384 @ Page directory size |
| 401 | bic r3, r3, #0xff @ Align the pointer |
| 402 | bic r3, r3, #0x3f00 |
| 403 | /* |
| 404 | * Initialise the page tables, turning on the cacheable and bufferable |
| 405 | * bits for the RAM area only. |
| 406 | */ |
| 407 | mov r0, r3 |
Russell King | f461902 | 2006-01-12 17:17:57 +0000 | [diff] [blame] | 408 | mov r9, r0, lsr #18 |
| 409 | mov r9, r9, lsl #18 @ start of RAM |
| 410 | add r10, r9, #0x10000000 @ a reasonable RAM size |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 411 | mov r1, #0x12 |
| 412 | orr r1, r1, #3 << 10 |
| 413 | add r2, r3, #16384 |
Nicolas Pitre | 265d5e4 | 2006-01-18 22:38:51 +0000 | [diff] [blame] | 414 | 1: cmp r1, r9 @ if virt > start of RAM |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 415 | orrhs r1, r1, #0x0c @ set cacheable, bufferable |
Russell King | f461902 | 2006-01-12 17:17:57 +0000 | [diff] [blame] | 416 | cmp r1, r10 @ if virt > end of RAM |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 417 | bichs r1, r1, #0x0c @ clear cacheable, bufferable |
| 418 | str r1, [r0], #4 @ 1:1 mapping |
| 419 | add r1, r1, #1048576 |
| 420 | teq r0, r2 |
| 421 | bne 1b |
| 422 | /* |
| 423 | * If ever we are running from Flash, then we surely want the cache |
| 424 | * to be enabled also for our execution instance... We map 2MB of it |
| 425 | * so there is no map overlap problem for up to 1 MB compressed kernel. |
| 426 | * If the execution is in RAM then we would only be duplicating the above. |
| 427 | */ |
| 428 | mov r1, #0x1e |
| 429 | orr r1, r1, #3 << 10 |
| 430 | mov r2, pc, lsr #20 |
| 431 | orr r1, r1, r2, lsl #20 |
| 432 | add r0, r3, r2, lsl #2 |
| 433 | str r1, [r0], #4 |
| 434 | add r1, r1, #1048576 |
| 435 | str r1, [r0] |
| 436 | mov pc, lr |
Catalin Marinas | 93ed397 | 2008-08-28 11:22:32 +0100 | [diff] [blame] | 437 | ENDPROC(__setup_mmu) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 438 | |
Hyok S. Choi | c76b6b4 | 2006-03-24 09:53:18 +0000 | [diff] [blame] | 439 | __armv4_mmu_cache_on: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 440 | mov r12, lr |
Catalin Marinas | 8bdca0a | 2009-07-24 12:35:06 +0100 | [diff] [blame] | 441 | #ifdef CONFIG_MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 442 | bl __setup_mmu |
| 443 | mov r0, #0 |
| 444 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer |
| 445 | mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs |
| 446 | mrc p15, 0, r0, c1, c0, 0 @ read control reg |
| 447 | orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement |
| 448 | orr r0, r0, #0x0030 |
Catalin Marinas | 2658485 | 2009-05-30 14:00:18 +0100 | [diff] [blame] | 449 | #ifdef CONFIG_CPU_ENDIAN_BE8 |
| 450 | orr r0, r0, #1 << 25 @ big-endian page tables |
| 451 | #endif |
Hyok S. Choi | c76b6b4 | 2006-03-24 09:53:18 +0000 | [diff] [blame] | 452 | bl __common_mmu_cache_on |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 453 | mov r0, #0 |
| 454 | mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs |
Catalin Marinas | 8bdca0a | 2009-07-24 12:35:06 +0100 | [diff] [blame] | 455 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 456 | mov pc, r12 |
| 457 | |
Catalin Marinas | 7d09e85 | 2007-06-01 17:14:53 +0100 | [diff] [blame] | 458 | __armv7_mmu_cache_on: |
| 459 | mov r12, lr |
Catalin Marinas | 8bdca0a | 2009-07-24 12:35:06 +0100 | [diff] [blame] | 460 | #ifdef CONFIG_MMU |
Catalin Marinas | 7d09e85 | 2007-06-01 17:14:53 +0100 | [diff] [blame] | 461 | mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0 |
| 462 | tst r11, #0xf @ VMSA |
| 463 | blne __setup_mmu |
| 464 | mov r0, #0 |
| 465 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer |
| 466 | tst r11, #0xf @ VMSA |
| 467 | mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs |
Catalin Marinas | 8bdca0a | 2009-07-24 12:35:06 +0100 | [diff] [blame] | 468 | #endif |
Catalin Marinas | 7d09e85 | 2007-06-01 17:14:53 +0100 | [diff] [blame] | 469 | mrc p15, 0, r0, c1, c0, 0 @ read control reg |
| 470 | orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement |
| 471 | orr r0, r0, #0x003c @ write buffer |
Catalin Marinas | 8bdca0a | 2009-07-24 12:35:06 +0100 | [diff] [blame] | 472 | #ifdef CONFIG_MMU |
Catalin Marinas | 2658485 | 2009-05-30 14:00:18 +0100 | [diff] [blame] | 473 | #ifdef CONFIG_CPU_ENDIAN_BE8 |
| 474 | orr r0, r0, #1 << 25 @ big-endian page tables |
| 475 | #endif |
Catalin Marinas | 7d09e85 | 2007-06-01 17:14:53 +0100 | [diff] [blame] | 476 | orrne r0, r0, #1 @ MMU enabled |
| 477 | movne r1, #-1 |
| 478 | mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer |
| 479 | mcrne p15, 0, r1, c3, c0, 0 @ load domain access control |
Catalin Marinas | 8bdca0a | 2009-07-24 12:35:06 +0100 | [diff] [blame] | 480 | #endif |
Catalin Marinas | 7d09e85 | 2007-06-01 17:14:53 +0100 | [diff] [blame] | 481 | mcr p15, 0, r0, c1, c0, 0 @ load control register |
| 482 | mrc p15, 0, r0, c1, c0, 0 @ and read it back |
| 483 | mov r0, #0 |
| 484 | mcr p15, 0, r0, c7, c5, 4 @ ISB |
| 485 | mov pc, r12 |
| 486 | |
Paulius Zaleckas | 28853ac | 2009-03-25 13:10:01 +0200 | [diff] [blame] | 487 | __fa526_cache_on: |
| 488 | mov r12, lr |
| 489 | bl __setup_mmu |
| 490 | mov r0, #0 |
| 491 | mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache |
| 492 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer |
| 493 | mcr p15, 0, r0, c8, c7, 0 @ flush UTLB |
| 494 | mrc p15, 0, r0, c1, c0, 0 @ read control reg |
| 495 | orr r0, r0, #0x1000 @ I-cache enable |
| 496 | bl __common_mmu_cache_on |
| 497 | mov r0, #0 |
| 498 | mcr p15, 0, r0, c8, c7, 0 @ flush UTLB |
| 499 | mov pc, r12 |
| 500 | |
Hyok S. Choi | c76b6b4 | 2006-03-24 09:53:18 +0000 | [diff] [blame] | 501 | __arm6_mmu_cache_on: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 502 | mov r12, lr |
| 503 | bl __setup_mmu |
| 504 | mov r0, #0 |
| 505 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 |
| 506 | mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 |
| 507 | mov r0, #0x30 |
Hyok S. Choi | c76b6b4 | 2006-03-24 09:53:18 +0000 | [diff] [blame] | 508 | bl __common_mmu_cache_on |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 509 | mov r0, #0 |
| 510 | mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 |
| 511 | mov pc, r12 |
| 512 | |
Hyok S. Choi | c76b6b4 | 2006-03-24 09:53:18 +0000 | [diff] [blame] | 513 | __common_mmu_cache_on: |
Catalin Marinas | 0e056f2 | 2009-07-24 12:32:58 +0100 | [diff] [blame] | 514 | #ifndef CONFIG_THUMB2_KERNEL |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 515 | #ifndef DEBUG |
| 516 | orr r0, r0, #0x000d @ Write buffer, mmu |
| 517 | #endif |
| 518 | mov r1, #-1 |
| 519 | mcr p15, 0, r3, c2, c0, 0 @ load page table pointer |
| 520 | mcr p15, 0, r1, c3, c0, 0 @ load domain access control |
Nicolas Pitre | 2dc7667 | 2006-07-01 21:29:32 +0100 | [diff] [blame] | 521 | b 1f |
| 522 | .align 5 @ cache line aligned |
| 523 | 1: mcr p15, 0, r0, c1, c0, 0 @ load control register |
| 524 | mrc p15, 0, r0, c1, c0, 0 @ and read it back to |
| 525 | sub pc, lr, r0, lsr #32 @ properly flush pipeline |
Catalin Marinas | 0e056f2 | 2009-07-24 12:32:58 +0100 | [diff] [blame] | 526 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 527 | |
| 528 | /* |
| 529 | * All code following this line is relocatable. It is relocated by |
| 530 | * the above code to the end of the decompressed kernel image and |
| 531 | * executed there. During this time, we have no stacks. |
| 532 | * |
| 533 | * r0 = decompressed kernel length |
| 534 | * r1-r3 = unused |
| 535 | * r4 = kernel execution address |
| 536 | * r5 = decompressed kernel start |
| 537 | * r6 = processor ID |
| 538 | * r7 = architecture ID |
Russell King | f461902 | 2006-01-12 17:17:57 +0000 | [diff] [blame] | 539 | * r8 = atags pointer |
Catalin Marinas | 0e056f2 | 2009-07-24 12:32:58 +0100 | [diff] [blame] | 540 | * r9-r12,r14 = corrupted |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 541 | */ |
| 542 | .align 5 |
Russell King | f461902 | 2006-01-12 17:17:57 +0000 | [diff] [blame] | 543 | reloc_start: add r9, r5, r0 |
Catalin Marinas | c7341d4 | 2007-06-01 17:13:59 +0100 | [diff] [blame] | 544 | sub r9, r9, #128 @ do not copy the stack |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 545 | debug_reloc_start |
| 546 | mov r1, r4 |
| 547 | 1: |
| 548 | .rept 4 |
Catalin Marinas | 0e056f2 | 2009-07-24 12:32:58 +0100 | [diff] [blame] | 549 | ldmia r5!, {r0, r2, r3, r10 - r12, r14} @ relocate kernel |
| 550 | stmia r1!, {r0, r2, r3, r10 - r12, r14} |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 551 | .endr |
| 552 | |
Russell King | f461902 | 2006-01-12 17:17:57 +0000 | [diff] [blame] | 553 | cmp r5, r9 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 554 | blo 1b |
Catalin Marinas | 0e056f2 | 2009-07-24 12:32:58 +0100 | [diff] [blame] | 555 | mov sp, r1 |
| 556 | add sp, sp, #128 @ relocate the stack |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 557 | debug_reloc_end |
| 558 | |
| 559 | call_kernel: bl cache_clean_flush |
| 560 | bl cache_off |
Russell King | f461902 | 2006-01-12 17:17:57 +0000 | [diff] [blame] | 561 | mov r0, #0 @ must be zero |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 562 | mov r1, r7 @ restore architecture number |
Russell King | f461902 | 2006-01-12 17:17:57 +0000 | [diff] [blame] | 563 | mov r2, r8 @ restore atags pointer |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 564 | mov pc, r4 @ call kernel |
| 565 | |
| 566 | /* |
| 567 | * Here follow the relocatable cache support functions for the |
| 568 | * various processors. This is a generic hook for locating an |
| 569 | * entry and jumping to an instruction at the specified offset |
| 570 | * from the start of the block. Please note this is all position |
| 571 | * independent code. |
| 572 | * |
| 573 | * r1 = corrupted |
| 574 | * r2 = corrupted |
| 575 | * r3 = block offset |
| 576 | * r6 = corrupted |
| 577 | * r12 = corrupted |
| 578 | */ |
| 579 | |
| 580 | call_cache_fn: adr r12, proc_types |
Hyok S. Choi | f12d0d7 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 581 | #ifdef CONFIG_CPU_CP15 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 582 | mrc p15, 0, r6, c0, c0 @ get processor ID |
Hyok S. Choi | f12d0d7 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 583 | #else |
| 584 | ldr r6, =CONFIG_PROCESSOR_ID |
| 585 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 586 | 1: ldr r1, [r12, #0] @ get value |
| 587 | ldr r2, [r12, #4] @ get mask |
| 588 | eor r1, r1, r6 @ (real ^ match) |
| 589 | tst r1, r2 @ & mask |
Catalin Marinas | 0e056f2 | 2009-07-24 12:32:58 +0100 | [diff] [blame] | 590 | ARM( addeq pc, r12, r3 ) @ call cache function |
| 591 | THUMB( addeq r12, r3 ) |
| 592 | THUMB( moveq pc, r12 ) @ call cache function |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 593 | add r12, r12, #4*5 |
| 594 | b 1b |
| 595 | |
| 596 | /* |
| 597 | * Table for cache operations. This is basically: |
| 598 | * - CPU ID match |
| 599 | * - CPU ID mask |
| 600 | * - 'cache on' method instruction |
| 601 | * - 'cache off' method instruction |
| 602 | * - 'cache flush' method instruction |
| 603 | * |
| 604 | * We match an entry using: ((real_id ^ match) & mask) == 0 |
| 605 | * |
| 606 | * Writethrough caches generally only need 'on' and 'off' |
| 607 | * methods. Writeback caches _must_ have the flush method |
| 608 | * defined. |
| 609 | */ |
Catalin Marinas | 88987ef | 2009-07-24 12:32:52 +0100 | [diff] [blame] | 610 | .align 2 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 611 | .type proc_types,#object |
| 612 | proc_types: |
| 613 | .word 0x41560600 @ ARM6/610 |
| 614 | .word 0xffffffe0 |
Catalin Marinas | 0e056f2 | 2009-07-24 12:32:58 +0100 | [diff] [blame] | 615 | W(b) __arm6_mmu_cache_off @ works, but slow |
| 616 | W(b) __arm6_mmu_cache_off |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 617 | mov pc, lr |
Catalin Marinas | 0e056f2 | 2009-07-24 12:32:58 +0100 | [diff] [blame] | 618 | THUMB( nop ) |
Hyok S. Choi | c76b6b4 | 2006-03-24 09:53:18 +0000 | [diff] [blame] | 619 | @ b __arm6_mmu_cache_on @ untested |
| 620 | @ b __arm6_mmu_cache_off |
| 621 | @ b __armv3_mmu_cache_flush |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 622 | |
| 623 | .word 0x00000000 @ old ARM ID |
| 624 | .word 0x0000f000 |
| 625 | mov pc, lr |
Catalin Marinas | 0e056f2 | 2009-07-24 12:32:58 +0100 | [diff] [blame] | 626 | THUMB( nop ) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 627 | mov pc, lr |
Catalin Marinas | 0e056f2 | 2009-07-24 12:32:58 +0100 | [diff] [blame] | 628 | THUMB( nop ) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 629 | mov pc, lr |
Catalin Marinas | 0e056f2 | 2009-07-24 12:32:58 +0100 | [diff] [blame] | 630 | THUMB( nop ) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 631 | |
| 632 | .word 0x41007000 @ ARM7/710 |
| 633 | .word 0xfff8fe00 |
Catalin Marinas | 0e056f2 | 2009-07-24 12:32:58 +0100 | [diff] [blame] | 634 | W(b) __arm7_mmu_cache_off |
| 635 | W(b) __arm7_mmu_cache_off |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 636 | mov pc, lr |
Catalin Marinas | 0e056f2 | 2009-07-24 12:32:58 +0100 | [diff] [blame] | 637 | THUMB( nop ) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 638 | |
| 639 | .word 0x41807200 @ ARM720T (writethrough) |
| 640 | .word 0xffffff00 |
Catalin Marinas | 0e056f2 | 2009-07-24 12:32:58 +0100 | [diff] [blame] | 641 | W(b) __armv4_mmu_cache_on |
| 642 | W(b) __armv4_mmu_cache_off |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 643 | mov pc, lr |
Catalin Marinas | 0e056f2 | 2009-07-24 12:32:58 +0100 | [diff] [blame] | 644 | THUMB( nop ) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 645 | |
Hyok S. Choi | 10c2df6 | 2006-03-27 10:21:34 +0100 | [diff] [blame] | 646 | .word 0x41007400 @ ARM74x |
| 647 | .word 0xff00ff00 |
Catalin Marinas | 0e056f2 | 2009-07-24 12:32:58 +0100 | [diff] [blame] | 648 | W(b) __armv3_mpu_cache_on |
| 649 | W(b) __armv3_mpu_cache_off |
| 650 | W(b) __armv3_mpu_cache_flush |
Hyok S. Choi | 10c2df6 | 2006-03-27 10:21:34 +0100 | [diff] [blame] | 651 | |
| 652 | .word 0x41009400 @ ARM94x |
| 653 | .word 0xff00ff00 |
Catalin Marinas | 0e056f2 | 2009-07-24 12:32:58 +0100 | [diff] [blame] | 654 | W(b) __armv4_mpu_cache_on |
| 655 | W(b) __armv4_mpu_cache_off |
| 656 | W(b) __armv4_mpu_cache_flush |
Hyok S. Choi | 10c2df6 | 2006-03-27 10:21:34 +0100 | [diff] [blame] | 657 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 658 | .word 0x00007000 @ ARM7 IDs |
| 659 | .word 0x0000f000 |
| 660 | mov pc, lr |
Catalin Marinas | 0e056f2 | 2009-07-24 12:32:58 +0100 | [diff] [blame] | 661 | THUMB( nop ) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 662 | mov pc, lr |
Catalin Marinas | 0e056f2 | 2009-07-24 12:32:58 +0100 | [diff] [blame] | 663 | THUMB( nop ) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 664 | mov pc, lr |
Catalin Marinas | 0e056f2 | 2009-07-24 12:32:58 +0100 | [diff] [blame] | 665 | THUMB( nop ) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 666 | |
| 667 | @ Everything from here on will be the new ID system. |
| 668 | |
| 669 | .word 0x4401a100 @ sa110 / sa1100 |
| 670 | .word 0xffffffe0 |
Catalin Marinas | 0e056f2 | 2009-07-24 12:32:58 +0100 | [diff] [blame] | 671 | W(b) __armv4_mmu_cache_on |
| 672 | W(b) __armv4_mmu_cache_off |
| 673 | W(b) __armv4_mmu_cache_flush |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 674 | |
| 675 | .word 0x6901b110 @ sa1110 |
| 676 | .word 0xfffffff0 |
Catalin Marinas | 0e056f2 | 2009-07-24 12:32:58 +0100 | [diff] [blame] | 677 | W(b) __armv4_mmu_cache_on |
| 678 | W(b) __armv4_mmu_cache_off |
| 679 | W(b) __armv4_mmu_cache_flush |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 680 | |
Eric Miao | 59c7bcd | 2008-11-29 21:42:39 +0800 | [diff] [blame] | 681 | .word 0x56056930 |
| 682 | .word 0xff0ffff0 @ PXA935 |
Catalin Marinas | 0e056f2 | 2009-07-24 12:32:58 +0100 | [diff] [blame] | 683 | W(b) __armv4_mmu_cache_on |
| 684 | W(b) __armv4_mmu_cache_off |
| 685 | W(b) __armv4_mmu_cache_flush |
Eric Miao | 59c7bcd | 2008-11-29 21:42:39 +0800 | [diff] [blame] | 686 | |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 687 | .word 0x56158000 @ PXA168 |
| 688 | .word 0xfffff000 |
Catalin Marinas | 0e056f2 | 2009-07-24 12:32:58 +0100 | [diff] [blame] | 689 | W(b) __armv4_mmu_cache_on |
| 690 | W(b) __armv4_mmu_cache_off |
| 691 | W(b) __armv5tej_mmu_cache_flush |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 692 | |
| 693 | .word 0x56056930 |
| 694 | .word 0xff0ffff0 @ PXA935 |
Catalin Marinas | 0e056f2 | 2009-07-24 12:32:58 +0100 | [diff] [blame] | 695 | W(b) __armv4_mmu_cache_on |
| 696 | W(b) __armv4_mmu_cache_off |
| 697 | W(b) __armv4_mmu_cache_flush |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 698 | |
Nicolas Pitre | 2e2023f | 2008-06-03 23:06:21 +0200 | [diff] [blame] | 699 | .word 0x56050000 @ Feroceon |
| 700 | .word 0xff0f0000 |
Catalin Marinas | 0e056f2 | 2009-07-24 12:32:58 +0100 | [diff] [blame] | 701 | W(b) __armv4_mmu_cache_on |
| 702 | W(b) __armv4_mmu_cache_off |
| 703 | W(b) __armv5tej_mmu_cache_flush |
Nicolas Pitre | 3ebb5a2 | 2007-10-31 15:31:48 -0400 | [diff] [blame] | 704 | |
Joonyoung Shim | 5587931 | 2009-06-16 20:05:57 +0900 | [diff] [blame] | 705 | #ifdef CONFIG_CPU_FEROCEON_OLD_ID |
| 706 | /* this conflicts with the standard ARMv5TE entry */ |
| 707 | .long 0x41009260 @ Old Feroceon |
| 708 | .long 0xff00fff0 |
| 709 | b __armv4_mmu_cache_on |
| 710 | b __armv4_mmu_cache_off |
| 711 | b __armv5tej_mmu_cache_flush |
| 712 | #endif |
| 713 | |
Paulius Zaleckas | 28853ac | 2009-03-25 13:10:01 +0200 | [diff] [blame] | 714 | .word 0x66015261 @ FA526 |
| 715 | .word 0xff01fff1 |
Catalin Marinas | 0e056f2 | 2009-07-24 12:32:58 +0100 | [diff] [blame] | 716 | W(b) __fa526_cache_on |
| 717 | W(b) __armv4_mmu_cache_off |
| 718 | W(b) __fa526_cache_flush |
Paulius Zaleckas | 28853ac | 2009-03-25 13:10:01 +0200 | [diff] [blame] | 719 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 720 | @ These match on the architecture ID |
| 721 | |
| 722 | .word 0x00020000 @ ARMv4T |
| 723 | .word 0x000f0000 |
Catalin Marinas | 0e056f2 | 2009-07-24 12:32:58 +0100 | [diff] [blame] | 724 | W(b) __armv4_mmu_cache_on |
| 725 | W(b) __armv4_mmu_cache_off |
| 726 | W(b) __armv4_mmu_cache_flush |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 727 | |
| 728 | .word 0x00050000 @ ARMv5TE |
| 729 | .word 0x000f0000 |
Catalin Marinas | 0e056f2 | 2009-07-24 12:32:58 +0100 | [diff] [blame] | 730 | W(b) __armv4_mmu_cache_on |
| 731 | W(b) __armv4_mmu_cache_off |
| 732 | W(b) __armv4_mmu_cache_flush |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 733 | |
| 734 | .word 0x00060000 @ ARMv5TEJ |
| 735 | .word 0x000f0000 |
Catalin Marinas | 0e056f2 | 2009-07-24 12:32:58 +0100 | [diff] [blame] | 736 | W(b) __armv4_mmu_cache_on |
| 737 | W(b) __armv4_mmu_cache_off |
| 738 | W(b) __armv4_mmu_cache_flush |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 739 | |
Catalin Marinas | 45a7b9c | 2006-06-18 16:21:50 +0100 | [diff] [blame] | 740 | .word 0x0007b000 @ ARMv6 |
Catalin Marinas | 7d09e85 | 2007-06-01 17:14:53 +0100 | [diff] [blame] | 741 | .word 0x000ff000 |
Catalin Marinas | 0e056f2 | 2009-07-24 12:32:58 +0100 | [diff] [blame] | 742 | W(b) __armv4_mmu_cache_on |
| 743 | W(b) __armv4_mmu_cache_off |
| 744 | W(b) __armv6_mmu_cache_flush |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 745 | |
Catalin Marinas | 7d09e85 | 2007-06-01 17:14:53 +0100 | [diff] [blame] | 746 | .word 0x000f0000 @ new CPU Id |
| 747 | .word 0x000f0000 |
Catalin Marinas | 0e056f2 | 2009-07-24 12:32:58 +0100 | [diff] [blame] | 748 | W(b) __armv7_mmu_cache_on |
| 749 | W(b) __armv7_mmu_cache_off |
| 750 | W(b) __armv7_mmu_cache_flush |
Catalin Marinas | 7d09e85 | 2007-06-01 17:14:53 +0100 | [diff] [blame] | 751 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 752 | .word 0 @ unrecognised type |
| 753 | .word 0 |
| 754 | mov pc, lr |
Catalin Marinas | 0e056f2 | 2009-07-24 12:32:58 +0100 | [diff] [blame] | 755 | THUMB( nop ) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 756 | mov pc, lr |
Catalin Marinas | 0e056f2 | 2009-07-24 12:32:58 +0100 | [diff] [blame] | 757 | THUMB( nop ) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 758 | mov pc, lr |
Catalin Marinas | 0e056f2 | 2009-07-24 12:32:58 +0100 | [diff] [blame] | 759 | THUMB( nop ) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 760 | |
| 761 | .size proc_types, . - proc_types |
| 762 | |
| 763 | /* |
| 764 | * Turn off the Cache and MMU. ARMv3 does not support |
| 765 | * reading the control register, but ARMv4 does. |
| 766 | * |
| 767 | * On entry, r6 = processor ID |
| 768 | * On exit, r0, r1, r2, r3, r12 corrupted |
| 769 | * This routine must preserve: r4, r6, r7 |
| 770 | */ |
| 771 | .align 5 |
| 772 | cache_off: mov r3, #12 @ cache_off function |
| 773 | b call_cache_fn |
| 774 | |
Hyok S. Choi | 10c2df6 | 2006-03-27 10:21:34 +0100 | [diff] [blame] | 775 | __armv4_mpu_cache_off: |
| 776 | mrc p15, 0, r0, c1, c0 |
| 777 | bic r0, r0, #0x000d |
| 778 | mcr p15, 0, r0, c1, c0 @ turn MPU and cache off |
| 779 | mov r0, #0 |
| 780 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer |
| 781 | mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache |
| 782 | mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache |
| 783 | mov pc, lr |
| 784 | |
| 785 | __armv3_mpu_cache_off: |
| 786 | mrc p15, 0, r0, c1, c0 |
| 787 | bic r0, r0, #0x000d |
| 788 | mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off |
| 789 | mov r0, #0 |
| 790 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 |
| 791 | mov pc, lr |
| 792 | |
Hyok S. Choi | c76b6b4 | 2006-03-24 09:53:18 +0000 | [diff] [blame] | 793 | __armv4_mmu_cache_off: |
Catalin Marinas | 8bdca0a | 2009-07-24 12:35:06 +0100 | [diff] [blame] | 794 | #ifdef CONFIG_MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 795 | mrc p15, 0, r0, c1, c0 |
| 796 | bic r0, r0, #0x000d |
| 797 | mcr p15, 0, r0, c1, c0 @ turn MMU and cache off |
| 798 | mov r0, #0 |
| 799 | mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4 |
| 800 | mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4 |
Catalin Marinas | 8bdca0a | 2009-07-24 12:35:06 +0100 | [diff] [blame] | 801 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 802 | mov pc, lr |
| 803 | |
Catalin Marinas | 7d09e85 | 2007-06-01 17:14:53 +0100 | [diff] [blame] | 804 | __armv7_mmu_cache_off: |
| 805 | mrc p15, 0, r0, c1, c0 |
Catalin Marinas | 8bdca0a | 2009-07-24 12:35:06 +0100 | [diff] [blame] | 806 | #ifdef CONFIG_MMU |
Catalin Marinas | 7d09e85 | 2007-06-01 17:14:53 +0100 | [diff] [blame] | 807 | bic r0, r0, #0x000d |
Catalin Marinas | 8bdca0a | 2009-07-24 12:35:06 +0100 | [diff] [blame] | 808 | #else |
| 809 | bic r0, r0, #0x000c |
| 810 | #endif |
Catalin Marinas | 7d09e85 | 2007-06-01 17:14:53 +0100 | [diff] [blame] | 811 | mcr p15, 0, r0, c1, c0 @ turn MMU and cache off |
| 812 | mov r12, lr |
| 813 | bl __armv7_mmu_cache_flush |
| 814 | mov r0, #0 |
Catalin Marinas | 8bdca0a | 2009-07-24 12:35:06 +0100 | [diff] [blame] | 815 | #ifdef CONFIG_MMU |
Catalin Marinas | 7d09e85 | 2007-06-01 17:14:53 +0100 | [diff] [blame] | 816 | mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB |
Catalin Marinas | 8bdca0a | 2009-07-24 12:35:06 +0100 | [diff] [blame] | 817 | #endif |
Catalin Marinas | c30c2f9 | 2008-11-06 13:23:07 +0000 | [diff] [blame] | 818 | mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC |
| 819 | mcr p15, 0, r0, c7, c10, 4 @ DSB |
| 820 | mcr p15, 0, r0, c7, c5, 4 @ ISB |
Catalin Marinas | 7d09e85 | 2007-06-01 17:14:53 +0100 | [diff] [blame] | 821 | mov pc, r12 |
| 822 | |
Hyok S. Choi | c76b6b4 | 2006-03-24 09:53:18 +0000 | [diff] [blame] | 823 | __arm6_mmu_cache_off: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 824 | mov r0, #0x00000030 @ ARM6 control reg. |
Hyok S. Choi | c76b6b4 | 2006-03-24 09:53:18 +0000 | [diff] [blame] | 825 | b __armv3_mmu_cache_off |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 826 | |
Hyok S. Choi | c76b6b4 | 2006-03-24 09:53:18 +0000 | [diff] [blame] | 827 | __arm7_mmu_cache_off: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 828 | mov r0, #0x00000070 @ ARM7 control reg. |
Hyok S. Choi | c76b6b4 | 2006-03-24 09:53:18 +0000 | [diff] [blame] | 829 | b __armv3_mmu_cache_off |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 830 | |
Hyok S. Choi | c76b6b4 | 2006-03-24 09:53:18 +0000 | [diff] [blame] | 831 | __armv3_mmu_cache_off: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 832 | mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off |
| 833 | mov r0, #0 |
| 834 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 |
| 835 | mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 |
| 836 | mov pc, lr |
| 837 | |
| 838 | /* |
| 839 | * Clean and flush the cache to maintain consistency. |
| 840 | * |
| 841 | * On entry, |
| 842 | * r6 = processor ID |
| 843 | * On exit, |
| 844 | * r1, r2, r3, r11, r12 corrupted |
| 845 | * This routine must preserve: |
| 846 | * r0, r4, r5, r6, r7 |
| 847 | */ |
| 848 | .align 5 |
| 849 | cache_clean_flush: |
| 850 | mov r3, #16 |
| 851 | b call_cache_fn |
| 852 | |
Hyok S. Choi | 10c2df6 | 2006-03-27 10:21:34 +0100 | [diff] [blame] | 853 | __armv4_mpu_cache_flush: |
| 854 | mov r2, #1 |
| 855 | mov r3, #0 |
| 856 | mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache |
| 857 | mov r1, #7 << 5 @ 8 segments |
| 858 | 1: orr r3, r1, #63 << 26 @ 64 entries |
| 859 | 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index |
| 860 | subs r3, r3, #1 << 26 |
| 861 | bcs 2b @ entries 63 to 0 |
| 862 | subs r1, r1, #1 << 5 |
| 863 | bcs 1b @ segments 7 to 0 |
| 864 | |
| 865 | teq r2, #0 |
| 866 | mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache |
| 867 | mcr p15, 0, ip, c7, c10, 4 @ drain WB |
| 868 | mov pc, lr |
| 869 | |
Paulius Zaleckas | 28853ac | 2009-03-25 13:10:01 +0200 | [diff] [blame] | 870 | __fa526_cache_flush: |
| 871 | mov r1, #0 |
| 872 | mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache |
| 873 | mcr p15, 0, r1, c7, c5, 0 @ flush I cache |
| 874 | mcr p15, 0, r1, c7, c10, 4 @ drain WB |
| 875 | mov pc, lr |
Hyok S. Choi | 10c2df6 | 2006-03-27 10:21:34 +0100 | [diff] [blame] | 876 | |
Hyok S. Choi | c76b6b4 | 2006-03-24 09:53:18 +0000 | [diff] [blame] | 877 | __armv6_mmu_cache_flush: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 878 | mov r1, #0 |
| 879 | mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D |
| 880 | mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB |
| 881 | mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified |
| 882 | mcr p15, 0, r1, c7, c10, 4 @ drain WB |
| 883 | mov pc, lr |
| 884 | |
Catalin Marinas | 7d09e85 | 2007-06-01 17:14:53 +0100 | [diff] [blame] | 885 | __armv7_mmu_cache_flush: |
| 886 | mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1 |
| 887 | tst r10, #0xf << 16 @ hierarchical cache (ARMv7) |
Catalin Marinas | 7d09e85 | 2007-06-01 17:14:53 +0100 | [diff] [blame] | 888 | mov r10, #0 |
Catalin Marinas | c30c2f9 | 2008-11-06 13:23:07 +0000 | [diff] [blame] | 889 | beq hierarchical |
Catalin Marinas | 7d09e85 | 2007-06-01 17:14:53 +0100 | [diff] [blame] | 890 | mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D |
| 891 | b iflush |
| 892 | hierarchical: |
Catalin Marinas | c30c2f9 | 2008-11-06 13:23:07 +0000 | [diff] [blame] | 893 | mcr p15, 0, r10, c7, c10, 5 @ DMB |
Catalin Marinas | 0e056f2 | 2009-07-24 12:32:58 +0100 | [diff] [blame] | 894 | stmfd sp!, {r0-r7, r9-r11} |
Catalin Marinas | 7d09e85 | 2007-06-01 17:14:53 +0100 | [diff] [blame] | 895 | mrc p15, 1, r0, c0, c0, 1 @ read clidr |
| 896 | ands r3, r0, #0x7000000 @ extract loc from clidr |
| 897 | mov r3, r3, lsr #23 @ left align loc bit field |
| 898 | beq finished @ if loc is 0, then no need to clean |
| 899 | mov r10, #0 @ start clean at cache level 0 |
| 900 | loop1: |
| 901 | add r2, r10, r10, lsr #1 @ work out 3x current cache level |
| 902 | mov r1, r0, lsr r2 @ extract cache type bits from clidr |
| 903 | and r1, r1, #7 @ mask of the bits for current cache only |
| 904 | cmp r1, #2 @ see what cache we have at this level |
| 905 | blt skip @ skip if no cache, or just i-cache |
| 906 | mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr |
| 907 | mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr |
| 908 | mrc p15, 1, r1, c0, c0, 0 @ read the new csidr |
| 909 | and r2, r1, #7 @ extract the length of the cache lines |
| 910 | add r2, r2, #4 @ add 4 (line length offset) |
| 911 | ldr r4, =0x3ff |
| 912 | ands r4, r4, r1, lsr #3 @ find maximum number on the way size |
Catalin Marinas | 000b502 | 2008-10-03 11:09:10 +0100 | [diff] [blame] | 913 | clz r5, r4 @ find bit position of way size increment |
Catalin Marinas | 7d09e85 | 2007-06-01 17:14:53 +0100 | [diff] [blame] | 914 | ldr r7, =0x7fff |
| 915 | ands r7, r7, r1, lsr #13 @ extract max number of the index size |
| 916 | loop2: |
| 917 | mov r9, r4 @ create working copy of max way size |
| 918 | loop3: |
Catalin Marinas | 0e056f2 | 2009-07-24 12:32:58 +0100 | [diff] [blame] | 919 | ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11 |
| 920 | ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11 |
| 921 | THUMB( lsl r6, r9, r5 ) |
| 922 | THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11 |
| 923 | THUMB( lsl r6, r7, r2 ) |
| 924 | THUMB( orr r11, r11, r6 ) @ factor index number into r11 |
Catalin Marinas | 7d09e85 | 2007-06-01 17:14:53 +0100 | [diff] [blame] | 925 | mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way |
| 926 | subs r9, r9, #1 @ decrement the way |
| 927 | bge loop3 |
| 928 | subs r7, r7, #1 @ decrement the index |
| 929 | bge loop2 |
| 930 | skip: |
| 931 | add r10, r10, #2 @ increment cache number |
| 932 | cmp r3, r10 |
| 933 | bgt loop1 |
| 934 | finished: |
Catalin Marinas | 0e056f2 | 2009-07-24 12:32:58 +0100 | [diff] [blame] | 935 | ldmfd sp!, {r0-r7, r9-r11} |
Catalin Marinas | 7d09e85 | 2007-06-01 17:14:53 +0100 | [diff] [blame] | 936 | mov r10, #0 @ swith back to cache level 0 |
| 937 | mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr |
Catalin Marinas | 7d09e85 | 2007-06-01 17:14:53 +0100 | [diff] [blame] | 938 | iflush: |
Catalin Marinas | c30c2f9 | 2008-11-06 13:23:07 +0000 | [diff] [blame] | 939 | mcr p15, 0, r10, c7, c10, 4 @ DSB |
Catalin Marinas | 7d09e85 | 2007-06-01 17:14:53 +0100 | [diff] [blame] | 940 | mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB |
Catalin Marinas | c30c2f9 | 2008-11-06 13:23:07 +0000 | [diff] [blame] | 941 | mcr p15, 0, r10, c7, c10, 4 @ DSB |
| 942 | mcr p15, 0, r10, c7, c5, 4 @ ISB |
Catalin Marinas | 7d09e85 | 2007-06-01 17:14:53 +0100 | [diff] [blame] | 943 | mov pc, lr |
| 944 | |
Nicolas Pitre | 15754bf | 2007-10-31 15:15:29 -0400 | [diff] [blame] | 945 | __armv5tej_mmu_cache_flush: |
| 946 | 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache |
| 947 | bne 1b |
| 948 | mcr p15, 0, r0, c7, c5, 0 @ flush I cache |
| 949 | mcr p15, 0, r0, c7, c10, 4 @ drain WB |
| 950 | mov pc, lr |
| 951 | |
Hyok S. Choi | c76b6b4 | 2006-03-24 09:53:18 +0000 | [diff] [blame] | 952 | __armv4_mmu_cache_flush: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 953 | mov r2, #64*1024 @ default: 32K dcache size (*2) |
| 954 | mov r11, #32 @ default: 32 byte line size |
| 955 | mrc p15, 0, r3, c0, c0, 1 @ read cache type |
| 956 | teq r3, r6 @ cache ID register present? |
| 957 | beq no_cache_id |
| 958 | mov r1, r3, lsr #18 |
| 959 | and r1, r1, #7 |
| 960 | mov r2, #1024 |
| 961 | mov r2, r2, lsl r1 @ base dcache size *2 |
| 962 | tst r3, #1 << 14 @ test M bit |
| 963 | addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1 |
| 964 | mov r3, r3, lsr #12 |
| 965 | and r3, r3, #3 |
| 966 | mov r11, #8 |
| 967 | mov r11, r11, lsl r3 @ cache line size in bytes |
| 968 | no_cache_id: |
Catalin Marinas | 0e056f2 | 2009-07-24 12:32:58 +0100 | [diff] [blame] | 969 | mov r1, pc |
| 970 | bic r1, r1, #63 @ align to longest cache line |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 971 | add r2, r1, r2 |
Catalin Marinas | 0e056f2 | 2009-07-24 12:32:58 +0100 | [diff] [blame] | 972 | 1: |
| 973 | ARM( ldr r3, [r1], r11 ) @ s/w flush D cache |
| 974 | THUMB( ldr r3, [r1] ) @ s/w flush D cache |
| 975 | THUMB( add r1, r1, r11 ) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 976 | teq r1, r2 |
| 977 | bne 1b |
| 978 | |
| 979 | mcr p15, 0, r1, c7, c5, 0 @ flush I cache |
| 980 | mcr p15, 0, r1, c7, c6, 0 @ flush D cache |
| 981 | mcr p15, 0, r1, c7, c10, 4 @ drain WB |
| 982 | mov pc, lr |
| 983 | |
Hyok S. Choi | c76b6b4 | 2006-03-24 09:53:18 +0000 | [diff] [blame] | 984 | __armv3_mmu_cache_flush: |
Hyok S. Choi | 10c2df6 | 2006-03-27 10:21:34 +0100 | [diff] [blame] | 985 | __armv3_mpu_cache_flush: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 986 | mov r1, #0 |
| 987 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 |
| 988 | mov pc, lr |
| 989 | |
| 990 | /* |
| 991 | * Various debugging routines for printing hex characters and |
| 992 | * memory, which again must be relocatable. |
| 993 | */ |
| 994 | #ifdef DEBUG |
Catalin Marinas | 88987ef | 2009-07-24 12:32:52 +0100 | [diff] [blame] | 995 | .align 2 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 996 | .type phexbuf,#object |
| 997 | phexbuf: .space 12 |
| 998 | .size phexbuf, . - phexbuf |
| 999 | |
| 1000 | phex: adr r3, phexbuf |
| 1001 | mov r2, #0 |
| 1002 | strb r2, [r3, r1] |
| 1003 | 1: subs r1, r1, #1 |
| 1004 | movmi r0, r3 |
| 1005 | bmi puts |
| 1006 | and r2, r0, #15 |
| 1007 | mov r0, r0, lsr #4 |
| 1008 | cmp r2, #10 |
| 1009 | addge r2, r2, #7 |
| 1010 | add r2, r2, #'0' |
| 1011 | strb r2, [r3, r1] |
| 1012 | b 1b |
| 1013 | |
| 1014 | puts: loadsp r3 |
| 1015 | 1: ldrb r2, [r0], #1 |
| 1016 | teq r2, #0 |
| 1017 | moveq pc, lr |
Russell King | 5cd0c34 | 2005-05-03 12:18:46 +0100 | [diff] [blame] | 1018 | 2: writeb r2, r3 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1019 | mov r1, #0x00020000 |
| 1020 | 3: subs r1, r1, #1 |
| 1021 | bne 3b |
| 1022 | teq r2, #'\n' |
| 1023 | moveq r2, #'\r' |
| 1024 | beq 2b |
| 1025 | teq r0, #0 |
| 1026 | bne 1b |
| 1027 | mov pc, lr |
| 1028 | putc: |
| 1029 | mov r2, r0 |
| 1030 | mov r0, #0 |
| 1031 | loadsp r3 |
| 1032 | b 2b |
| 1033 | |
| 1034 | memdump: mov r12, r0 |
| 1035 | mov r10, lr |
| 1036 | mov r11, #0 |
| 1037 | 2: mov r0, r11, lsl #2 |
| 1038 | add r0, r0, r12 |
| 1039 | mov r1, #8 |
| 1040 | bl phex |
| 1041 | mov r0, #':' |
| 1042 | bl putc |
| 1043 | 1: mov r0, #' ' |
| 1044 | bl putc |
| 1045 | ldr r0, [r12, r11, lsl #2] |
| 1046 | mov r1, #8 |
| 1047 | bl phex |
| 1048 | and r0, r11, #7 |
| 1049 | teq r0, #3 |
| 1050 | moveq r0, #' ' |
| 1051 | bleq putc |
| 1052 | and r0, r11, #7 |
| 1053 | add r11, r11, #1 |
| 1054 | teq r0, #7 |
| 1055 | bne 1b |
| 1056 | mov r0, #'\n' |
| 1057 | bl putc |
| 1058 | cmp r11, #64 |
| 1059 | blt 2b |
| 1060 | mov pc, r10 |
| 1061 | #endif |
| 1062 | |
Catalin Marinas | 92c83ff | 2007-06-22 14:27:50 +0100 | [diff] [blame] | 1063 | .ltorg |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1064 | reloc_end: |
| 1065 | |
| 1066 | .align |
| 1067 | .section ".stack", "w" |
| 1068 | user_stack: .space 4096 |