Dmitriy Taychenachev | fd6ac7b | 2009-07-31 20:29:22 +0900 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2006 Freescale Semiconductor, Inc. |
| 3 | * Copyright 2006-2007 Motorola, Inc. |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation; either version 2 of the License, or |
| 8 | * (at your option) any later version. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 18 | * |
| 19 | */ |
| 20 | |
| 21 | #ifndef _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_ |
| 22 | #define _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_ |
| 23 | |
| 24 | #define CKIL_CLK_FREQ 32768 |
| 25 | |
| 26 | #define MXC_CRM_AP_BASE MXC91231_IO_ADDRESS(MXC91231_CRM_AP_BASE_ADDR) |
| 27 | #define MXC_CRM_COM_BASE MXC91231_IO_ADDRESS(MXC91231_CRM_COM_BASE_ADDR) |
| 28 | #define MXC_DSM_BASE MXC91231_IO_ADDRESS(MXC91231_DSM_BASE_ADDR) |
| 29 | #define MXC_PLL0_BASE MXC91231_IO_ADDRESS(MXC91231_PLL0_BASE_ADDR) |
| 30 | #define MXC_PLL1_BASE MXC91231_IO_ADDRESS(MXC91231_PLL1_BASE_ADDR) |
| 31 | #define MXC_PLL2_BASE MXC91231_IO_ADDRESS(MXC91231_PLL2_BASE_ADDR) |
| 32 | #define MXC_CLKCTL_BASE MXC91231_IO_ADDRESS(MXC91231_CLKCTL_BASE_ADDR) |
| 33 | |
| 34 | /* PLL Register Offsets */ |
| 35 | #define MXC_PLL_DP_CTL 0x00 |
| 36 | #define MXC_PLL_DP_CONFIG 0x04 |
| 37 | #define MXC_PLL_DP_OP 0x08 |
| 38 | #define MXC_PLL_DP_MFD 0x0C |
| 39 | #define MXC_PLL_DP_MFN 0x10 |
| 40 | #define MXC_PLL_DP_HFS_OP 0x1C |
| 41 | #define MXC_PLL_DP_HFS_MFD 0x20 |
| 42 | #define MXC_PLL_DP_HFS_MFN 0x24 |
| 43 | |
| 44 | /* PLL Register Bit definitions */ |
| 45 | #define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000 |
| 46 | #define MXC_PLL_DP_CTL_ADE 0x800 |
| 47 | #define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400 |
| 48 | #define MXC_PLL_DP_CTL_HFSM 0x80 |
| 49 | #define MXC_PLL_DP_CTL_PRE 0x40 |
| 50 | #define MXC_PLL_DP_CTL_UPEN 0x20 |
| 51 | #define MXC_PLL_DP_CTL_RST 0x10 |
| 52 | #define MXC_PLL_DP_CTL_RCP 0x8 |
| 53 | #define MXC_PLL_DP_CTL_PLM 0x4 |
| 54 | #define MXC_PLL_DP_CTL_BRM0 0x2 |
| 55 | #define MXC_PLL_DP_CTL_LRF 0x1 |
| 56 | |
| 57 | #define MXC_PLL_DP_OP_MFI_OFFSET 4 |
| 58 | #define MXC_PLL_DP_OP_MFI_MASK 0xF |
| 59 | #define MXC_PLL_DP_OP_PDF_OFFSET 0 |
| 60 | #define MXC_PLL_DP_OP_PDF_MASK 0xF |
| 61 | |
| 62 | #define MXC_PLL_DP_MFD_OFFSET 0 |
| 63 | #define MXC_PLL_DP_MFD_MASK 0x7FFFFFF |
| 64 | |
| 65 | #define MXC_PLL_DP_MFN_OFFSET 0 |
| 66 | #define MXC_PLL_DP_MFN_MASK 0x7FFFFFF |
| 67 | |
| 68 | /* CRM AP Register Offsets */ |
| 69 | #define MXC_CRMAP_ASCSR (MXC_CRM_AP_BASE + 0x00) |
| 70 | #define MXC_CRMAP_ACDR (MXC_CRM_AP_BASE + 0x04) |
| 71 | #define MXC_CRMAP_ACDER1 (MXC_CRM_AP_BASE + 0x08) |
| 72 | #define MXC_CRMAP_ACDER2 (MXC_CRM_AP_BASE + 0x0C) |
| 73 | #define MXC_CRMAP_ACGCR (MXC_CRM_AP_BASE + 0x10) |
| 74 | #define MXC_CRMAP_ACCGCR (MXC_CRM_AP_BASE + 0x14) |
| 75 | #define MXC_CRMAP_AMLPMRA (MXC_CRM_AP_BASE + 0x18) |
| 76 | #define MXC_CRMAP_AMLPMRB (MXC_CRM_AP_BASE + 0x1C) |
| 77 | #define MXC_CRMAP_AMLPMRC (MXC_CRM_AP_BASE + 0x20) |
| 78 | #define MXC_CRMAP_AMLPMRD (MXC_CRM_AP_BASE + 0x24) |
| 79 | #define MXC_CRMAP_AMLPMRE1 (MXC_CRM_AP_BASE + 0x28) |
| 80 | #define MXC_CRMAP_AMLPMRE2 (MXC_CRM_AP_BASE + 0x2C) |
| 81 | #define MXC_CRMAP_AMLPMRF (MXC_CRM_AP_BASE + 0x30) |
| 82 | #define MXC_CRMAP_AMLPMRG (MXC_CRM_AP_BASE + 0x34) |
| 83 | #define MXC_CRMAP_APGCR (MXC_CRM_AP_BASE + 0x38) |
| 84 | #define MXC_CRMAP_ACSR (MXC_CRM_AP_BASE + 0x3C) |
| 85 | #define MXC_CRMAP_ADCR (MXC_CRM_AP_BASE + 0x40) |
| 86 | #define MXC_CRMAP_ACR (MXC_CRM_AP_BASE + 0x44) |
| 87 | #define MXC_CRMAP_AMCR (MXC_CRM_AP_BASE + 0x48) |
| 88 | #define MXC_CRMAP_APCR (MXC_CRM_AP_BASE + 0x4C) |
| 89 | #define MXC_CRMAP_AMORA (MXC_CRM_AP_BASE + 0x50) |
| 90 | #define MXC_CRMAP_AMORB (MXC_CRM_AP_BASE + 0x54) |
| 91 | #define MXC_CRMAP_AGPR (MXC_CRM_AP_BASE + 0x58) |
| 92 | #define MXC_CRMAP_APRA (MXC_CRM_AP_BASE + 0x5C) |
| 93 | #define MXC_CRMAP_APRB (MXC_CRM_AP_BASE + 0x60) |
| 94 | #define MXC_CRMAP_APOR (MXC_CRM_AP_BASE + 0x64) |
| 95 | #define MXC_CRMAP_ADFMR (MXC_CRM_AP_BASE + 0x68) |
| 96 | |
| 97 | /* CRM AP Register Bit definitions */ |
| 98 | #define MXC_CRMAP_ASCSR_CRS 0x10000 |
| 99 | #define MXC_CRMAP_ASCSR_AP_PATDIV2_OFFSET 15 |
| 100 | #define MXC_CRMAP_ASCSR_AP_PATREF_DIV2 0x8000 |
| 101 | #define MXC_CRMAP_ASCSR_USBSEL_OFFSET 13 |
| 102 | #define MXC_CRMAP_ASCSR_USBSEL_MASK (0x3 << 13) |
| 103 | #define MXC_CRMAP_ASCSR_CSISEL_OFFSET 11 |
| 104 | #define MXC_CRMAP_ASCSR_CSISEL_MASK (0x3 << 11) |
| 105 | #define MXC_CRMAP_ASCSR_SSI2SEL_OFFSET 7 |
| 106 | #define MXC_CRMAP_ASCSR_SSI2SEL_MASK (0x3 << 7) |
| 107 | #define MXC_CRMAP_ASCSR_SSI1SEL_OFFSET 5 |
| 108 | #define MXC_CRMAP_ASCSR_SSI1SEL_MASK (0x3 << 5) |
| 109 | #define MXC_CRMAP_ASCSR_APSEL_OFFSET 3 |
| 110 | #define MXC_CRMAP_ASCSR_APSEL_MASK (0x3 << 3) |
| 111 | #define MXC_CRMAP_ASCSR_AP_PATDIV1_OFFSET 2 |
| 112 | #define MXC_CRMAP_ASCSR_AP_PATREF_DIV1 0x4 |
| 113 | #define MXC_CRMAP_ASCSR_APISEL 0x1 |
| 114 | |
| 115 | #define MXC_CRMAP_ACDR_ARMDIV_OFFSET 8 |
| 116 | #define MXC_CRMAP_ACDR_ARMDIV_MASK (0xF << 8) |
| 117 | #define MXC_CRMAP_ACDR_AHBDIV_OFFSET 4 |
| 118 | #define MXC_CRMAP_ACDR_AHBDIV_MASK (0xF << 4) |
| 119 | #define MXC_CRMAP_ACDR_IPDIV_OFFSET 0 |
| 120 | #define MXC_CRMAP_ACDR_IPDIV_MASK 0xF |
| 121 | |
| 122 | #define MXC_CRMAP_ACDER1_CSIEN_OFFSET 30 |
| 123 | #define MXC_CRMAP_ACDER1_CSIDIV_OFFSET 24 |
| 124 | #define MXC_CRMAP_ACDER1_CSIDIV_MASK (0x3F << 24) |
| 125 | #define MXC_CRMAP_ACDER1_SSI2EN_OFFSET 14 |
| 126 | #define MXC_CRMAP_ACDER1_SSI2DIV_OFFSET 8 |
| 127 | #define MXC_CRMAP_ACDER1_SSI2DIV_MASK (0x3F << 8) |
| 128 | #define MXC_CRMAP_ACDER1_SSI1EN_OFFSET 6 |
| 129 | #define MXC_CRMAP_ACDER1_SSI1DIV_OFFSET 0 |
| 130 | #define MXC_CRMAP_ACDER1_SSI1DIV_MASK 0x3F |
| 131 | |
| 132 | #define MXC_CRMAP_ACDER2_CRCT_CLK_DIV_OFFSET 24 |
| 133 | #define MXC_CRMAP_ACDER2_CRCT_CLK_DIV_MASK (0x7 << 24) |
| 134 | #define MXC_CRMAP_ACDER2_NFCEN_OFFSET 20 |
| 135 | #define MXC_CRMAP_ACDER2_NFCDIV_OFFSET 16 |
| 136 | #define MXC_CRMAP_ACDER2_NFCDIV_MASK (0xF << 16) |
| 137 | #define MXC_CRMAP_ACDER2_USBEN_OFFSET 12 |
| 138 | #define MXC_CRMAP_ACDER2_USBDIV_OFFSET 8 |
| 139 | #define MXC_CRMAP_ACDER2_USBDIV_MASK (0xF << 8) |
| 140 | #define MXC_CRMAP_ACDER2_BAUD_ISEL_OFFSET 5 |
| 141 | #define MXC_CRMAP_ACDER2_BAUD_ISEL_MASK (0x3 << 5) |
| 142 | #define MXC_CRMAP_ACDER2_BAUDDIV_OFFSET 0 |
| 143 | #define MXC_CRMAP_ACDER2_BAUDDIV_MASK 0xF |
| 144 | |
| 145 | #define MXC_CRMAP_AMLPMRA_MLPMA7_OFFSET 22 |
| 146 | #define MXC_CRMAP_AMLPMRA_MLPMA7_MASK (0x7 << 22) |
| 147 | #define MXC_CRMAP_AMLPMRA_MLPMA6_OFFSET 19 |
| 148 | #define MXC_CRMAP_AMLPMRA_MLPMA6_MASK (0x7 << 19) |
| 149 | #define MXC_CRMAP_AMLPMRA_MLPMA4_OFFSET 12 |
| 150 | #define MXC_CRMAP_AMLPMRA_MLPMA4_MASK (0x7 << 12) |
| 151 | #define MXC_CRMAP_AMLPMRA_MLPMA3_OFFSET 9 |
| 152 | #define MXC_CRMAP_AMLPMRA_MLPMA3_MASK (0x7 << 9) |
| 153 | #define MXC_CRMAP_AMLPMRA_MLPMA2_OFFSET 6 |
| 154 | #define MXC_CRMAP_AMLPMRA_MLPMA2_MASK (0x7 << 6) |
| 155 | #define MXC_CRMAP_AMLPMRA_MLPMA1_OFFSET 3 |
| 156 | #define MXC_CRMAP_AMLPMRA_MLPMA1_MASK (0x7 << 3) |
| 157 | |
| 158 | #define MXC_CRMAP_AMLPMRB_MLPMB0_OFFSET 0 |
| 159 | #define MXC_CRMAP_AMLPMRB_MLPMB0_MASK 0x7 |
| 160 | |
| 161 | #define MXC_CRMAP_AMLPMRC_MLPMC9_OFFSET 28 |
| 162 | #define MXC_CRMAP_AMLPMRC_MLPMC9_MASK (0x7 << 28) |
| 163 | #define MXC_CRMAP_AMLPMRC_MLPMC7_OFFSET 22 |
| 164 | #define MXC_CRMAP_AMLPMRC_MLPMC7_MASK (0x7 << 22) |
| 165 | #define MXC_CRMAP_AMLPMRC_MLPMC5_OFFSET 16 |
| 166 | #define MXC_CRMAP_AMLPMRC_MLPMC5_MASK (0x7 << 16) |
| 167 | #define MXC_CRMAP_AMLPMRC_MLPMC4_OFFSET 12 |
| 168 | #define MXC_CRMAP_AMLPMRC_MLPMC4_MASK (0x7 << 12) |
| 169 | #define MXC_CRMAP_AMLPMRC_MLPMC3_OFFSET 9 |
| 170 | #define MXC_CRMAP_AMLPMRC_MLPMC3_MASK (0x7 << 9) |
| 171 | #define MXC_CRMAP_AMLPMRC_MLPMC2_OFFSET 6 |
| 172 | #define MXC_CRMAP_AMLPMRC_MLPMC2_MASK (0x7 << 6) |
| 173 | #define MXC_CRMAP_AMLPMRC_MLPMC1_OFFSET 3 |
| 174 | #define MXC_CRMAP_AMLPMRC_MLPMC1_MASK (0x7 << 3) |
| 175 | #define MXC_CRMAP_AMLPMRC_MLPMC0_OFFSET 0 |
| 176 | #define MXC_CRMAP_AMLPMRC_MLPMC0_MASK 0x7 |
| 177 | |
| 178 | #define MXC_CRMAP_AMLPMRD_MLPMD7_OFFSET 22 |
| 179 | #define MXC_CRMAP_AMLPMRD_MLPMD7_MASK (0x7 << 22) |
| 180 | #define MXC_CRMAP_AMLPMRD_MLPMD4_OFFSET 12 |
| 181 | #define MXC_CRMAP_AMLPMRD_MLPMD4_MASK (0x7 << 12) |
| 182 | #define MXC_CRMAP_AMLPMRD_MLPMD3_OFFSET 9 |
| 183 | #define MXC_CRMAP_AMLPMRD_MLPMD3_MASK (0x7 << 9) |
| 184 | #define MXC_CRMAP_AMLPMRD_MLPMD2_OFFSET 6 |
| 185 | #define MXC_CRMAP_AMLPMRD_MLPMD2_MASK (0x7 << 6) |
| 186 | #define MXC_CRMAP_AMLPMRD_MLPMD0_OFFSET 0 |
| 187 | #define MXC_CRMAP_AMLPMRD_MLPMD0_MASK 0x7 |
| 188 | |
| 189 | #define MXC_CRMAP_AMLPMRE1_MLPME9_OFFSET 28 |
| 190 | #define MXC_CRMAP_AMLPMRE1_MLPME9_MASK (0x7 << 28) |
| 191 | #define MXC_CRMAP_AMLPMRE1_MLPME8_OFFSET 25 |
| 192 | #define MXC_CRMAP_AMLPMRE1_MLPME8_MASK (0x7 << 25) |
| 193 | #define MXC_CRMAP_AMLPMRE1_MLPME7_OFFSET 22 |
| 194 | #define MXC_CRMAP_AMLPMRE1_MLPME7_MASK (0x7 << 22) |
| 195 | #define MXC_CRMAP_AMLPMRE1_MLPME6_OFFSET 19 |
| 196 | #define MXC_CRMAP_AMLPMRE1_MLPME6_MASK (0x7 << 19) |
| 197 | #define MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET 16 |
| 198 | #define MXC_CRMAP_AMLPMRE1_MLPME5_MASK (0x7 << 16) |
| 199 | #define MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET 12 |
| 200 | #define MXC_CRMAP_AMLPMRE1_MLPME4_MASK (0x7 << 12) |
| 201 | #define MXC_CRMAP_AMLPMRE1_MLPME3_OFFSET 9 |
| 202 | #define MXC_CRMAP_AMLPMRE1_MLPME3_MASK (0x7 << 9) |
| 203 | #define MXC_CRMAP_AMLPMRE1_MLPME2_OFFSET 6 |
| 204 | #define MXC_CRMAP_AMLPMRE1_MLPME2_MASK (0x7 << 6) |
| 205 | #define MXC_CRMAP_AMLPMRE1_MLPME1_OFFSET 3 |
| 206 | #define MXC_CRMAP_AMLPMRE1_MLPME1_MASK (0x7 << 3) |
| 207 | #define MXC_CRMAP_AMLPMRE1_MLPME0_OFFSET 0 |
| 208 | #define MXC_CRMAP_AMLPMRE1_MLPME0_MASK 0x7 |
| 209 | |
| 210 | #define MXC_CRMAP_AMLPMRE2_MLPME0_OFFSET 0 |
| 211 | #define MXC_CRMAP_AMLPMRE2_MLPME0_MASK 0x7 |
| 212 | |
| 213 | #define MXC_CRMAP_AMLPMRF_MLPMF6_OFFSET 19 |
| 214 | #define MXC_CRMAP_AMLPMRF_MLPMF6_MASK (0x7 << 19) |
| 215 | #define MXC_CRMAP_AMLPMRF_MLPMF5_OFFSET 16 |
| 216 | #define MXC_CRMAP_AMLPMRF_MLPMF5_MASK (0x7 << 16) |
| 217 | #define MXC_CRMAP_AMLPMRF_MLPMF3_OFFSET 9 |
| 218 | #define MXC_CRMAP_AMLPMRF_MLPMF3_MASK (0x7 << 9) |
| 219 | #define MXC_CRMAP_AMLPMRF_MLPMF2_OFFSET 6 |
| 220 | #define MXC_CRMAP_AMLPMRF_MLPMF2_MASK (0x7 << 6) |
| 221 | #define MXC_CRMAP_AMLPMRF_MLPMF1_OFFSET 3 |
| 222 | #define MXC_CRMAP_AMLPMRF_MLPMF1_MASK (0x7 << 3) |
| 223 | #define MXC_CRMAP_AMLPMRF_MLPMF0_OFFSET 0 |
| 224 | #define MXC_CRMAP_AMLPMRF_MLPMF0_MASK (0x7 << 0) |
| 225 | |
| 226 | #define MXC_CRMAP_AMLPMRG_MLPMG9_OFFSET 28 |
| 227 | #define MXC_CRMAP_AMLPMRG_MLPMG9_MASK (0x7 << 28) |
| 228 | #define MXC_CRMAP_AMLPMRG_MLPMG7_OFFSET 22 |
| 229 | #define MXC_CRMAP_AMLPMRG_MLPMG7_MASK (0x7 << 22) |
| 230 | #define MXC_CRMAP_AMLPMRG_MLPMG6_OFFSET 19 |
| 231 | #define MXC_CRMAP_AMLPMRG_MLPMG6_MASK (0x7 << 19) |
| 232 | #define MXC_CRMAP_AMLPMRG_MLPMG5_OFFSET 16 |
| 233 | #define MXC_CRMAP_AMLPMRG_MLPMG5_MASK (0x7 << 16) |
| 234 | #define MXC_CRMAP_AMLPMRG_MLPMG4_OFFSET 12 |
| 235 | #define MXC_CRMAP_AMLPMRG_MLPMG4_MASK (0x7 << 12) |
| 236 | #define MXC_CRMAP_AMLPMRG_MLPMG3_OFFSET 9 |
| 237 | #define MXC_CRMAP_AMLPMRG_MLPMG3_MASK (0x7 << 9) |
| 238 | #define MXC_CRMAP_AMLPMRG_MLPMG2_OFFSET 6 |
| 239 | #define MXC_CRMAP_AMLPMRG_MLPMG2_MASK (0x7 << 6) |
| 240 | #define MXC_CRMAP_AMLPMRG_MLPMG1_OFFSET 3 |
| 241 | #define MXC_CRMAP_AMLPMRG_MLPMG1_MASK (0x7 << 3) |
| 242 | #define MXC_CRMAP_AMLPMRG_MLPMG0_OFFSET 0 |
| 243 | #define MXC_CRMAP_AMLPMRG_MLPMG0_MASK 0x7 |
| 244 | |
| 245 | #define MXC_CRMAP_AGPR_IPUPAD_OFFSET 20 |
| 246 | #define MXC_CRMAP_AGPR_IPUPAD_MASK (0x7 << 20) |
| 247 | |
| 248 | #define MXC_CRMAP_APRA_EL1TEN_OFFSET 29 |
| 249 | #define MXC_CRMAP_APRA_SIMEN_OFFSET 24 |
| 250 | #define MXC_CRMAP_APRA_UART3DIV_OFFSET 17 |
| 251 | #define MXC_CRMAP_APRA_UART3DIV_MASK (0xF << 17) |
| 252 | #define MXC_CRMAP_APRA_UART3EN_OFFSET 16 |
| 253 | #define MXC_CRMAP_APRA_SAHARA_DIV2_CLKEN_OFFSET 14 |
| 254 | #define MXC_CRMAP_APRA_MQSPIEN_OFFSET 13 |
| 255 | #define MXC_CRMAP_APRA_UART2EN_OFFSET 8 |
| 256 | #define MXC_CRMAP_APRA_UART1EN_OFFSET 0 |
| 257 | |
| 258 | #define MXC_CRMAP_APRB_SDHC2_ISEL_OFFSET 13 |
| 259 | #define MXC_CRMAP_APRB_SDHC2_ISEL_MASK (0x7 << 13) |
| 260 | #define MXC_CRMAP_APRB_SDHC2_DIV_OFFSET 9 |
| 261 | #define MXC_CRMAP_APRB_SDHC2_DIV_MASK (0xF << 9) |
| 262 | #define MXC_CRMAP_APRB_SDHC2EN_OFFSET 8 |
| 263 | #define MXC_CRMAP_APRB_SDHC1_ISEL_OFFSET 5 |
| 264 | #define MXC_CRMAP_APRB_SDHC1_ISEL_MASK (0x7 << 5) |
| 265 | #define MXC_CRMAP_APRB_SDHC1_DIV_OFFSET 1 |
| 266 | #define MXC_CRMAP_APRB_SDHC1_DIV_MASK (0xF << 1) |
| 267 | #define MXC_CRMAP_APRB_SDHC1EN_OFFSET 0 |
| 268 | |
| 269 | #define MXC_CRMAP_ACSR_ADS_OFFSET 8 |
| 270 | #define MXC_CRMAP_ACSR_ADS (0x1 << 8) |
| 271 | #define MXC_CRMAP_ACSR_ACS 0x1 |
| 272 | |
| 273 | #define MXC_CRMAP_ADCR_LFDF_0 (0x0 << 8) |
| 274 | #define MXC_CRMAP_ADCR_LFDF_2 (0x1 << 8) |
| 275 | #define MXC_CRMAP_ADCR_LFDF_4 (0x2 << 8) |
| 276 | #define MXC_CRMAP_ADCR_LFDF_8 (0x3 << 8) |
| 277 | #define MXC_CRMAP_ADCR_LFDF_OFFSET 8 |
| 278 | #define MXC_CRMAP_ADCR_LFDF_MASK (0x3 << 8) |
| 279 | #define MXC_CRMAP_ADCR_ALT_PLL 0x80 |
| 280 | #define MXC_CRMAP_ADCR_DFS_DIVEN 0x20 |
| 281 | #define MXC_CRMAP_ADCR_DIV_BYP 0x2 |
| 282 | #define MXC_CRMAP_ADCR_VSTAT 0x8 |
| 283 | #define MXC_CRMAP_ADCR_TSTAT 0x10 |
| 284 | #define MXC_CRMAP_ADCR_DVFS_VCTRL 0x10 |
| 285 | #define MXC_CRMAP_ADCR_CLK_ON 0x40 |
| 286 | |
| 287 | #define MXC_CRMAP_ADFMR_FC_OFFSET 16 |
| 288 | #define MXC_CRMAP_ADFMR_FC_MASK (0x1F << 16) |
| 289 | #define MXC_CRMAP_ADFMR_MF_OFFSET 1 |
| 290 | #define MXC_CRMAP_ADFMR_MF_MASK (0x3FF << 1) |
| 291 | #define MXC_CRMAP_ADFMR_DFM_CLK_READY 0x1 |
| 292 | #define MXC_CRMAP_ADFMR_DFM_PWR_DOWN 0x8000 |
| 293 | |
| 294 | #define MXC_CRMAP_ACR_CKOHS_HIGH (1 << 18) |
| 295 | #define MXC_CRMAP_ACR_CKOS_HIGH (1 << 16) |
| 296 | #define MXC_CRMAP_ACR_CKOHS_MASK (0x7 << 12) |
| 297 | #define MXC_CRMAP_ACR_CKOHD (1 << 11) |
| 298 | #define MXC_CRMAP_ACR_CKOHDIV_MASK (0xF << 8) |
| 299 | #define MXC_CRMAP_ACR_CKOHDIV_OFFSET 8 |
| 300 | #define MXC_CRMAP_ACR_CKOD (1 << 7) |
| 301 | #define MXC_CRMAP_ACR_CKOS_MASK (0x7 << 4) |
| 302 | |
| 303 | /* AP Warm reset */ |
| 304 | #define MXC_CRMAP_AMCR_SW_AP (1 << 14) |
| 305 | |
| 306 | /* Bit definitions of ACGCR in CRM_AP for tree level clock gating */ |
| 307 | #define MXC_CRMAP_ACGCR_ACG0_STOP_WAIT 0x00000001 |
| 308 | #define MXC_CRMAP_ACGCR_ACG0_STOP 0x00000003 |
| 309 | #define MXC_CRMAP_ACGCR_ACG0_RUN 0x00000007 |
| 310 | #define MXC_CRMAP_ACGCR_ACG0_DISABLED 0x00000000 |
| 311 | |
| 312 | #define MXC_CRMAP_ACGCR_ACG1_STOP_WAIT 0x00000008 |
| 313 | #define MXC_CRMAP_ACGCR_ACG1_STOP 0x00000018 |
| 314 | #define MXC_CRMAP_ACGCR_ACG1_RUN 0x00000038 |
| 315 | #define MXC_CRMAP_ACGCR_ACG1_DISABLED 0x00000000 |
| 316 | |
| 317 | #define MXC_CRMAP_ACGCR_ACG2_STOP_WAIT 0x00000040 |
| 318 | #define MXC_CRMAP_ACGCR_ACG2_STOP 0x000000C0 |
| 319 | #define MXC_CRMAP_ACGCR_ACG2_RUN 0x000001C0 |
| 320 | #define MXC_CRMAP_ACGCR_ACG2_DISABLED 0x00000000 |
| 321 | |
| 322 | #define MXC_CRMAP_ACGCR_ACG3_STOP_WAIT 0x00000200 |
| 323 | #define MXC_CRMAP_ACGCR_ACG3_STOP 0x00000600 |
| 324 | #define MXC_CRMAP_ACGCR_ACG3_RUN 0x00000E00 |
| 325 | #define MXC_CRMAP_ACGCR_ACG3_DISABLED 0x00000000 |
| 326 | |
| 327 | #define MXC_CRMAP_ACGCR_ACG4_STOP_WAIT 0x00001000 |
| 328 | #define MXC_CRMAP_ACGCR_ACG4_STOP 0x00003000 |
| 329 | #define MXC_CRMAP_ACGCR_ACG4_RUN 0x00007000 |
| 330 | #define MXC_CRMAP_ACGCR_ACG4_DISABLED 0x00000000 |
| 331 | |
| 332 | #define MXC_CRMAP_ACGCR_ACG5_STOP_WAIT 0x00010000 |
| 333 | #define MXC_CRMAP_ACGCR_ACG5_STOP 0x00030000 |
| 334 | #define MXC_CRMAP_ACGCR_ACG5_RUN 0x00070000 |
| 335 | #define MXC_CRMAP_ACGCR_ACG5_DISABLED 0x00000000 |
| 336 | |
| 337 | #define MXC_CRMAP_ACGCR_ACG6_STOP_WAIT 0x00080000 |
| 338 | #define MXC_CRMAP_ACGCR_ACG6_STOP 0x00180000 |
| 339 | #define MXC_CRMAP_ACGCR_ACG6_RUN 0x00380000 |
| 340 | #define MXC_CRMAP_ACGCR_ACG6_DISABLED 0x00000000 |
| 341 | |
| 342 | #define NUM_GATE_CTRL 6 |
| 343 | |
| 344 | /* CRM COM Register Offsets */ |
| 345 | #define MXC_CRMCOM_CSCR (MXC_CRM_COM_BASE + 0x0C) |
| 346 | #define MXC_CRMCOM_CCCR (MXC_CRM_COM_BASE + 0x10) |
| 347 | |
| 348 | /* CRM COM Bit Definitions */ |
| 349 | #define MXC_CRMCOM_CSCR_PPD1 0x08000000 |
| 350 | #define MXC_CRMCOM_CSCR_CKOHSEL (1 << 18) |
| 351 | #define MXC_CRMCOM_CSCR_CKOSEL (1 << 17) |
| 352 | #define MXC_CRMCOM_CCCR_CC_DIV_OFFSET 8 |
| 353 | #define MXC_CRMCOM_CCCR_CC_DIV_MASK (0x1F << 8) |
| 354 | #define MXC_CRMCOM_CCCR_CC_SEL_OFFSET 0 |
| 355 | #define MXC_CRMCOM_CCCR_CC_SEL_MASK 0x3 |
| 356 | |
| 357 | /* DSM Register Offsets */ |
| 358 | #define MXC_DSM_SLEEP_TIME (MXC_DSM_BASE + 0x0c) |
| 359 | #define MXC_DSM_CONTROL0 (MXC_DSM_BASE + 0x20) |
| 360 | #define MXC_DSM_CONTROL1 (MXC_DSM_BASE + 0x24) |
| 361 | #define MXC_DSM_CTREN (MXC_DSM_BASE + 0x28) |
| 362 | #define MXC_DSM_WARM_PER (MXC_DSM_BASE + 0x40) |
| 363 | #define MXC_DSM_LOCK_PER (MXC_DSM_BASE + 0x44) |
| 364 | #define MXC_DSM_MGPER (MXC_DSM_BASE + 0x4c) |
| 365 | #define MXC_DSM_CRM_CONTROL (MXC_DSM_BASE + 0x50) |
| 366 | |
| 367 | /* Bit definitions of various registers in DSM */ |
| 368 | #define MXC_DSM_CRM_CTRL_DVFS_BYP 0x00000008 |
| 369 | #define MXC_DSM_CRM_CTRL_DVFS_VCTRL 0x00000004 |
| 370 | #define MXC_DSM_CRM_CTRL_LPMD1 0x00000002 |
| 371 | #define MXC_DSM_CRM_CTRL_LPMD0 0x00000001 |
| 372 | #define MXC_DSM_CRM_CTRL_LPMD_STOP_MODE 0x00000000 |
| 373 | #define MXC_DSM_CRM_CTRL_LPMD_WAIT_MODE 0x00000001 |
| 374 | #define MXC_DSM_CRM_CTRL_LPMD_RUN_MODE 0x00000003 |
| 375 | #define MXC_DSM_CONTROL0_STBY_COMMIT_EN 0x00000200 |
| 376 | #define MXC_DSM_CONTROL0_MSTR_EN 0x00000001 |
| 377 | #define MXC_DSM_CONTROL0_RESTART 0x00000010 |
| 378 | /* Counter Block reset */ |
| 379 | #define MXC_DSM_CONTROL1_CB_RST 0x00000002 |
| 380 | /* State Machine reset */ |
| 381 | #define MXC_DSM_CONTROL1_SM_RST 0x00000004 |
| 382 | /* Bit needed to reset counter block */ |
| 383 | #define MXC_CONTROL1_RST_CNT32 0x00000008 |
| 384 | #define MXC_DSM_CONTROL1_RST_CNT32_EN 0x00000800 |
| 385 | #define MXC_DSM_CONTROL1_SLEEP 0x00000100 |
| 386 | #define MXC_DSM_CONTROL1_WAKEUP_DISABLE 0x00004000 |
| 387 | #define MXC_DSM_CTREN_CNT32 0x00000001 |
| 388 | |
| 389 | /* Magic Fix enable bit */ |
| 390 | #define MXC_DSM_MGPER_EN_MGFX 0x80000000 |
| 391 | #define MXC_DSM_MGPER_PER_MASK 0x000003FF |
| 392 | #define MXC_DSM_MGPER_PER(n) (MXC_DSM_MGPER_PER_MASK & n) |
| 393 | |
| 394 | /* Address offsets of the CLKCTL registers */ |
| 395 | #define MXC_CLKCTL_GP_CTRL (MXC_CLKCTL_BASE + 0x00) |
| 396 | #define MXC_CLKCTL_GP_SER (MXC_CLKCTL_BASE + 0x04) |
| 397 | #define MXC_CLKCTL_GP_CER (MXC_CLKCTL_BASE + 0x08) |
| 398 | |
| 399 | #endif /* _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_ */ |