Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mach-omap2/mcbsp.c |
| 3 | * |
| 4 | * Copyright (C) 2008 Instituto Nokia de Tecnologia |
| 5 | * Contact: Eduardo Valentin <eduardo.valentin@indt.org.br> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | * |
| 11 | * Multichannel mode not supported. |
| 12 | */ |
| 13 | #include <linux/module.h> |
| 14 | #include <linux/init.h> |
| 15 | #include <linux/clk.h> |
| 16 | #include <linux/err.h> |
| 17 | #include <linux/io.h> |
| 18 | #include <linux/platform_device.h> |
| 19 | |
Tony Lindgren | dd7667a | 2009-01-15 13:09:51 +0200 | [diff] [blame] | 20 | #include <mach/irqs.h> |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 21 | #include <mach/dma.h> |
| 22 | #include <mach/mux.h> |
| 23 | #include <mach/cpu.h> |
| 24 | #include <mach/mcbsp.h> |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 25 | |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 26 | static void omap2_mcbsp2_mux_setup(void) |
| 27 | { |
| 28 | omap_cfg_reg(Y15_24XX_MCBSP2_CLKX); |
| 29 | omap_cfg_reg(R14_24XX_MCBSP2_FSX); |
| 30 | omap_cfg_reg(W15_24XX_MCBSP2_DR); |
| 31 | omap_cfg_reg(V15_24XX_MCBSP2_DX); |
| 32 | omap_cfg_reg(V14_24XX_GPIO117); |
| 33 | /* |
| 34 | * TODO: Need to add MUX settings for OMAP 2430 SDP |
| 35 | */ |
| 36 | } |
| 37 | |
| 38 | static void omap2_mcbsp_request(unsigned int id) |
| 39 | { |
| 40 | if (cpu_is_omap2420() && (id == OMAP_MCBSP2)) |
| 41 | omap2_mcbsp2_mux_setup(); |
| 42 | } |
| 43 | |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 44 | static struct omap_mcbsp_ops omap2_mcbsp_ops = { |
| 45 | .request = omap2_mcbsp_request, |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 46 | }; |
| 47 | |
Jarkko Nikula | 05228c3 | 2008-10-08 10:01:40 +0300 | [diff] [blame] | 48 | #ifdef CONFIG_ARCH_OMAP2420 |
| 49 | static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = { |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 50 | { |
Russell King | 6584690 | 2008-09-03 23:46:18 +0100 | [diff] [blame] | 51 | .phys_base = OMAP24XX_MCBSP1_BASE, |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 52 | .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX, |
| 53 | .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, |
| 54 | .rx_irq = INT_24XX_MCBSP1_IRQ_RX, |
| 55 | .tx_irq = INT_24XX_MCBSP1_IRQ_TX, |
| 56 | .ops = &omap2_mcbsp_ops, |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 57 | }, |
| 58 | { |
Russell King | 6584690 | 2008-09-03 23:46:18 +0100 | [diff] [blame] | 59 | .phys_base = OMAP24XX_MCBSP2_BASE, |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 60 | .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX, |
| 61 | .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, |
| 62 | .rx_irq = INT_24XX_MCBSP2_IRQ_RX, |
| 63 | .tx_irq = INT_24XX_MCBSP2_IRQ_TX, |
| 64 | .ops = &omap2_mcbsp_ops, |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 65 | }, |
| 66 | }; |
Jarkko Nikula | 05228c3 | 2008-10-08 10:01:40 +0300 | [diff] [blame] | 67 | #define OMAP2420_MCBSP_PDATA_SZ ARRAY_SIZE(omap2420_mcbsp_pdata) |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 68 | #else |
Jarkko Nikula | 05228c3 | 2008-10-08 10:01:40 +0300 | [diff] [blame] | 69 | #define omap2420_mcbsp_pdata NULL |
| 70 | #define OMAP2420_MCBSP_PDATA_SZ 0 |
| 71 | #endif |
| 72 | |
| 73 | #ifdef CONFIG_ARCH_OMAP2430 |
| 74 | static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { |
| 75 | { |
| 76 | .phys_base = OMAP24XX_MCBSP1_BASE, |
| 77 | .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX, |
| 78 | .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, |
| 79 | .rx_irq = INT_24XX_MCBSP1_IRQ_RX, |
| 80 | .tx_irq = INT_24XX_MCBSP1_IRQ_TX, |
| 81 | .ops = &omap2_mcbsp_ops, |
Jarkko Nikula | 05228c3 | 2008-10-08 10:01:40 +0300 | [diff] [blame] | 82 | }, |
| 83 | { |
| 84 | .phys_base = OMAP24XX_MCBSP2_BASE, |
| 85 | .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX, |
| 86 | .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, |
| 87 | .rx_irq = INT_24XX_MCBSP2_IRQ_RX, |
| 88 | .tx_irq = INT_24XX_MCBSP2_IRQ_TX, |
| 89 | .ops = &omap2_mcbsp_ops, |
Jarkko Nikula | 05228c3 | 2008-10-08 10:01:40 +0300 | [diff] [blame] | 90 | }, |
| 91 | { |
| 92 | .phys_base = OMAP2430_MCBSP3_BASE, |
| 93 | .dma_rx_sync = OMAP24XX_DMA_MCBSP3_RX, |
| 94 | .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX, |
| 95 | .rx_irq = INT_24XX_MCBSP3_IRQ_RX, |
| 96 | .tx_irq = INT_24XX_MCBSP3_IRQ_TX, |
| 97 | .ops = &omap2_mcbsp_ops, |
Jarkko Nikula | 05228c3 | 2008-10-08 10:01:40 +0300 | [diff] [blame] | 98 | }, |
| 99 | { |
| 100 | .phys_base = OMAP2430_MCBSP4_BASE, |
| 101 | .dma_rx_sync = OMAP24XX_DMA_MCBSP4_RX, |
| 102 | .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX, |
| 103 | .rx_irq = INT_24XX_MCBSP4_IRQ_RX, |
| 104 | .tx_irq = INT_24XX_MCBSP4_IRQ_TX, |
| 105 | .ops = &omap2_mcbsp_ops, |
Jarkko Nikula | 05228c3 | 2008-10-08 10:01:40 +0300 | [diff] [blame] | 106 | }, |
| 107 | { |
| 108 | .phys_base = OMAP2430_MCBSP5_BASE, |
| 109 | .dma_rx_sync = OMAP24XX_DMA_MCBSP5_RX, |
| 110 | .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX, |
| 111 | .rx_irq = INT_24XX_MCBSP5_IRQ_RX, |
| 112 | .tx_irq = INT_24XX_MCBSP5_IRQ_TX, |
| 113 | .ops = &omap2_mcbsp_ops, |
Jarkko Nikula | 05228c3 | 2008-10-08 10:01:40 +0300 | [diff] [blame] | 114 | }, |
| 115 | }; |
| 116 | #define OMAP2430_MCBSP_PDATA_SZ ARRAY_SIZE(omap2430_mcbsp_pdata) |
| 117 | #else |
| 118 | #define omap2430_mcbsp_pdata NULL |
| 119 | #define OMAP2430_MCBSP_PDATA_SZ 0 |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 120 | #endif |
| 121 | |
| 122 | #ifdef CONFIG_ARCH_OMAP34XX |
| 123 | static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { |
| 124 | { |
Russell King | 6584690 | 2008-09-03 23:46:18 +0100 | [diff] [blame] | 125 | .phys_base = OMAP34XX_MCBSP1_BASE, |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 126 | .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX, |
| 127 | .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, |
| 128 | .rx_irq = INT_24XX_MCBSP1_IRQ_RX, |
| 129 | .tx_irq = INT_24XX_MCBSP1_IRQ_TX, |
| 130 | .ops = &omap2_mcbsp_ops, |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 131 | }, |
| 132 | { |
Russell King | 6584690 | 2008-09-03 23:46:18 +0100 | [diff] [blame] | 133 | .phys_base = OMAP34XX_MCBSP2_BASE, |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 134 | .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX, |
| 135 | .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, |
| 136 | .rx_irq = INT_24XX_MCBSP2_IRQ_RX, |
| 137 | .tx_irq = INT_24XX_MCBSP2_IRQ_TX, |
| 138 | .ops = &omap2_mcbsp_ops, |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 139 | }, |
Chandra Shekhar | 9c8e3a0 | 2008-10-08 10:01:40 +0300 | [diff] [blame] | 140 | { |
| 141 | .phys_base = OMAP34XX_MCBSP3_BASE, |
| 142 | .dma_rx_sync = OMAP24XX_DMA_MCBSP3_RX, |
| 143 | .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX, |
| 144 | .rx_irq = INT_24XX_MCBSP3_IRQ_RX, |
| 145 | .tx_irq = INT_24XX_MCBSP3_IRQ_TX, |
| 146 | .ops = &omap2_mcbsp_ops, |
Chandra Shekhar | 9c8e3a0 | 2008-10-08 10:01:40 +0300 | [diff] [blame] | 147 | }, |
| 148 | { |
| 149 | .phys_base = OMAP34XX_MCBSP4_BASE, |
| 150 | .dma_rx_sync = OMAP24XX_DMA_MCBSP4_RX, |
| 151 | .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX, |
| 152 | .rx_irq = INT_24XX_MCBSP4_IRQ_RX, |
| 153 | .tx_irq = INT_24XX_MCBSP4_IRQ_TX, |
| 154 | .ops = &omap2_mcbsp_ops, |
Chandra Shekhar | 9c8e3a0 | 2008-10-08 10:01:40 +0300 | [diff] [blame] | 155 | }, |
| 156 | { |
| 157 | .phys_base = OMAP34XX_MCBSP5_BASE, |
| 158 | .dma_rx_sync = OMAP24XX_DMA_MCBSP5_RX, |
| 159 | .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX, |
| 160 | .rx_irq = INT_24XX_MCBSP5_IRQ_RX, |
| 161 | .tx_irq = INT_24XX_MCBSP5_IRQ_TX, |
| 162 | .ops = &omap2_mcbsp_ops, |
Chandra Shekhar | 9c8e3a0 | 2008-10-08 10:01:40 +0300 | [diff] [blame] | 163 | }, |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 164 | }; |
| 165 | #define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata) |
| 166 | #else |
| 167 | #define omap34xx_mcbsp_pdata NULL |
| 168 | #define OMAP34XX_MCBSP_PDATA_SZ 0 |
| 169 | #endif |
| 170 | |
Syed Rafiuddin | a5b92cc | 2009-07-28 18:57:10 +0530 | [diff] [blame] | 171 | static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = { |
| 172 | { |
| 173 | .phys_base = OMAP44XX_MCBSP1_BASE, |
| 174 | .dma_rx_sync = OMAP44XX_DMA_MCBSP1_RX, |
| 175 | .dma_tx_sync = OMAP44XX_DMA_MCBSP1_TX, |
| 176 | .rx_irq = INT_24XX_MCBSP1_IRQ_RX, |
| 177 | .tx_irq = INT_24XX_MCBSP1_IRQ_TX, |
| 178 | .ops = &omap2_mcbsp_ops, |
| 179 | }, |
| 180 | { |
| 181 | .phys_base = OMAP44XX_MCBSP2_BASE, |
| 182 | .dma_rx_sync = OMAP44XX_DMA_MCBSP2_RX, |
| 183 | .dma_tx_sync = OMAP44XX_DMA_MCBSP2_TX, |
| 184 | .rx_irq = INT_24XX_MCBSP2_IRQ_RX, |
| 185 | .tx_irq = INT_24XX_MCBSP2_IRQ_TX, |
| 186 | .ops = &omap2_mcbsp_ops, |
| 187 | }, |
| 188 | { |
| 189 | .phys_base = OMAP44XX_MCBSP3_BASE, |
| 190 | .dma_rx_sync = OMAP44XX_DMA_MCBSP3_RX, |
| 191 | .dma_tx_sync = OMAP44XX_DMA_MCBSP3_TX, |
| 192 | .rx_irq = INT_24XX_MCBSP3_IRQ_RX, |
| 193 | .tx_irq = INT_24XX_MCBSP3_IRQ_TX, |
| 194 | .ops = &omap2_mcbsp_ops, |
| 195 | }, |
| 196 | { |
| 197 | .phys_base = OMAP44XX_MCBSP4_BASE, |
| 198 | .dma_rx_sync = OMAP44XX_DMA_MCBSP4_RX, |
| 199 | .dma_tx_sync = OMAP44XX_DMA_MCBSP4_TX, |
| 200 | .rx_irq = INT_24XX_MCBSP4_IRQ_RX, |
| 201 | .tx_irq = INT_24XX_MCBSP4_IRQ_TX, |
| 202 | .ops = &omap2_mcbsp_ops, |
| 203 | }, |
| 204 | }; |
| 205 | #define OMAP44XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap44xx_mcbsp_pdata) |
| 206 | |
Chandra Shekhar | b4b58f5 | 2008-10-08 10:01:39 +0300 | [diff] [blame] | 207 | static int __init omap2_mcbsp_init(void) |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 208 | { |
Jarkko Nikula | 05228c3 | 2008-10-08 10:01:40 +0300 | [diff] [blame] | 209 | if (cpu_is_omap2420()) |
| 210 | omap_mcbsp_count = OMAP2420_MCBSP_PDATA_SZ; |
| 211 | if (cpu_is_omap2430()) |
| 212 | omap_mcbsp_count = OMAP2430_MCBSP_PDATA_SZ; |
Chandra Shekhar | b4b58f5 | 2008-10-08 10:01:39 +0300 | [diff] [blame] | 213 | if (cpu_is_omap34xx()) |
| 214 | omap_mcbsp_count = OMAP34XX_MCBSP_PDATA_SZ; |
Syed Rafiuddin | a5b92cc | 2009-07-28 18:57:10 +0530 | [diff] [blame] | 215 | if (cpu_is_omap44xx()) |
| 216 | omap_mcbsp_count = OMAP44XX_MCBSP_PDATA_SZ; |
Chandra Shekhar | b4b58f5 | 2008-10-08 10:01:39 +0300 | [diff] [blame] | 217 | |
| 218 | mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *), |
| 219 | GFP_KERNEL); |
| 220 | if (!mcbsp_ptr) |
| 221 | return -ENOMEM; |
| 222 | |
Jarkko Nikula | 05228c3 | 2008-10-08 10:01:40 +0300 | [diff] [blame] | 223 | if (cpu_is_omap2420()) |
| 224 | omap_mcbsp_register_board_cfg(omap2420_mcbsp_pdata, |
| 225 | OMAP2420_MCBSP_PDATA_SZ); |
| 226 | if (cpu_is_omap2430()) |
| 227 | omap_mcbsp_register_board_cfg(omap2430_mcbsp_pdata, |
| 228 | OMAP2430_MCBSP_PDATA_SZ); |
Chandra Shekhar | 9c8e3a0 | 2008-10-08 10:01:40 +0300 | [diff] [blame] | 229 | if (cpu_is_omap34xx()) |
| 230 | omap_mcbsp_register_board_cfg(omap34xx_mcbsp_pdata, |
| 231 | OMAP34XX_MCBSP_PDATA_SZ); |
Syed Rafiuddin | a5b92cc | 2009-07-28 18:57:10 +0530 | [diff] [blame] | 232 | if (cpu_is_omap44xx()) |
| 233 | omap_mcbsp_register_board_cfg(omap44xx_mcbsp_pdata, |
| 234 | OMAP44XX_MCBSP_PDATA_SZ); |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 235 | |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 236 | return omap_mcbsp_init(); |
| 237 | } |
| 238 | arch_initcall(omap2_mcbsp_init); |