Ben Dooks | a24c091 | 2009-07-30 23:23:27 +0100 | [diff] [blame] | 1 | /* linux/arch/arm/mach-s3c2410/cpu-freq.c |
| 2 | * |
| 3 | * Copyright (c) 2006,2008 Simtec Electronics |
| 4 | * http://armlinux.simtec.co.uk/ |
| 5 | * Ben Dooks <ben@simtec.co.uk> |
| 6 | * |
| 7 | * S3C2410 CPU Frequency scaling |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License version 2 as |
| 11 | * published by the Free Software Foundation. |
| 12 | */ |
| 13 | |
| 14 | #include <linux/init.h> |
| 15 | #include <linux/module.h> |
| 16 | #include <linux/interrupt.h> |
| 17 | #include <linux/ioport.h> |
| 18 | #include <linux/cpufreq.h> |
| 19 | #include <linux/sysdev.h> |
| 20 | #include <linux/clk.h> |
| 21 | #include <linux/err.h> |
| 22 | #include <linux/io.h> |
| 23 | |
| 24 | #include <asm/mach/arch.h> |
| 25 | #include <asm/mach/map.h> |
| 26 | |
| 27 | #include <mach/regs-clock.h> |
| 28 | |
| 29 | #include <plat/cpu.h> |
| 30 | #include <plat/clock.h> |
| 31 | #include <plat/cpu-freq-core.h> |
| 32 | |
| 33 | /* Note, 2410A has an extra mode for 1:4:4 ratio, bit 2 of CLKDIV */ |
| 34 | |
| 35 | static void s3c2410_cpufreq_setdivs(struct s3c_cpufreq_config *cfg) |
| 36 | { |
| 37 | u32 clkdiv = 0; |
| 38 | |
| 39 | if (cfg->divs.h_divisor == 2) |
| 40 | clkdiv |= S3C2410_CLKDIVN_HDIVN; |
| 41 | |
| 42 | if (cfg->divs.p_divisor != cfg->divs.h_divisor) |
| 43 | clkdiv |= S3C2410_CLKDIVN_PDIVN; |
| 44 | |
| 45 | __raw_writel(clkdiv, S3C2410_CLKDIVN); |
| 46 | } |
| 47 | |
| 48 | static int s3c2410_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg) |
| 49 | { |
| 50 | unsigned long hclk, fclk, pclk; |
| 51 | unsigned int hdiv, pdiv; |
| 52 | unsigned long hclk_max; |
| 53 | |
| 54 | fclk = cfg->freq.fclk; |
| 55 | hclk_max = cfg->max.hclk; |
| 56 | |
| 57 | cfg->freq.armclk = fclk; |
| 58 | |
| 59 | s3c_freq_dbg("%s: fclk is %lu, max hclk %lu\n", |
| 60 | __func__, fclk, hclk_max); |
| 61 | |
| 62 | hdiv = (fclk > cfg->max.hclk) ? 2 : 1; |
| 63 | hclk = fclk / hdiv; |
| 64 | |
| 65 | if (hclk > cfg->max.hclk) { |
| 66 | s3c_freq_dbg("%s: hclk too big\n", __func__); |
| 67 | return -EINVAL; |
| 68 | } |
| 69 | |
| 70 | pdiv = (hclk > cfg->max.pclk) ? 2 : 1; |
| 71 | pclk = hclk / pdiv; |
| 72 | |
| 73 | if (pclk > cfg->max.pclk) { |
| 74 | s3c_freq_dbg("%s: pclk too big\n", __func__); |
| 75 | return -EINVAL; |
| 76 | } |
| 77 | |
| 78 | pdiv *= hdiv; |
| 79 | |
| 80 | /* record the result */ |
| 81 | cfg->divs.p_divisor = pdiv; |
| 82 | cfg->divs.h_divisor = hdiv; |
| 83 | |
| 84 | return 0 ; |
| 85 | } |
| 86 | |
| 87 | static struct s3c_cpufreq_info s3c2410_cpufreq_info = { |
| 88 | .max = { |
| 89 | .fclk = 200000000, |
| 90 | .hclk = 100000000, |
| 91 | .pclk = 50000000, |
| 92 | }, |
| 93 | |
| 94 | /* transition latency is about 5ms worst-case, so |
| 95 | * set 10ms to be sure */ |
| 96 | .latency = 10000000, |
| 97 | |
| 98 | .locktime_m = 150, |
| 99 | .locktime_u = 150, |
| 100 | .locktime_bits = 12, |
| 101 | |
| 102 | .need_pll = 1, |
| 103 | |
| 104 | .name = "s3c2410", |
| 105 | .calc_iotiming = s3c2410_iotiming_calc, |
| 106 | .set_iotiming = s3c2410_iotiming_set, |
| 107 | .get_iotiming = s3c2410_iotiming_get, |
| 108 | .resume_clocks = s3c2410_setup_clocks, |
| 109 | |
| 110 | .set_fvco = s3c2410_set_fvco, |
| 111 | .set_refresh = s3c2410_cpufreq_setrefresh, |
| 112 | .set_divs = s3c2410_cpufreq_setdivs, |
| 113 | .calc_divs = s3c2410_cpufreq_calcdivs, |
Ben Dooks | e6d197a | 2009-07-30 23:23:42 +0100 | [diff] [blame] | 114 | |
| 115 | .debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs), |
Ben Dooks | a24c091 | 2009-07-30 23:23:27 +0100 | [diff] [blame] | 116 | }; |
| 117 | |
| 118 | static int s3c2410_cpufreq_add(struct sys_device *sysdev) |
| 119 | { |
| 120 | return s3c_cpufreq_register(&s3c2410_cpufreq_info); |
| 121 | } |
| 122 | |
| 123 | static struct sysdev_driver s3c2410_cpufreq_driver = { |
| 124 | .add = s3c2410_cpufreq_add, |
| 125 | }; |
| 126 | |
| 127 | static int __init s3c2410_cpufreq_init(void) |
| 128 | { |
| 129 | return sysdev_driver_register(&s3c2410_sysclass, |
| 130 | &s3c2410_cpufreq_driver); |
| 131 | } |
| 132 | |
| 133 | arch_initcall(s3c2410_cpufreq_init); |
| 134 | |
| 135 | static int s3c2410a_cpufreq_add(struct sys_device *sysdev) |
| 136 | { |
| 137 | /* alter the maximum freq settings for S3C2410A. If a board knows |
| 138 | * it only has a maximum of 200, then it should register its own |
| 139 | * limits. */ |
| 140 | |
| 141 | s3c2410_cpufreq_info.max.fclk = 266000000; |
| 142 | s3c2410_cpufreq_info.max.hclk = 133000000; |
| 143 | s3c2410_cpufreq_info.max.pclk = 66500000; |
| 144 | s3c2410_cpufreq_info.name = "s3c2410a"; |
| 145 | |
| 146 | return s3c2410_cpufreq_add(sysdev); |
| 147 | } |
| 148 | |
| 149 | static struct sysdev_driver s3c2410a_cpufreq_driver = { |
| 150 | .add = s3c2410a_cpufreq_add, |
| 151 | }; |
| 152 | |
| 153 | static int __init s3c2410a_cpufreq_init(void) |
| 154 | { |
| 155 | return sysdev_driver_register(&s3c2410a_sysclass, |
| 156 | &s3c2410a_cpufreq_driver); |
| 157 | } |
| 158 | |
| 159 | arch_initcall(s3c2410a_cpufreq_init); |