| Holger Schurig | 260a1fd | 2009-01-26 16:34:53 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. |
| 3 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de |
| 4 | * |
| 5 | * This contains hardware definitions that are common between i.MX21 and |
| 6 | * i.MX27. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License |
| 10 | * as published by the Free Software Foundation; either version 2 |
| 11 | * of the License, or (at your option) any later version. |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
| 20 | * MA 02110-1301, USA. |
| 21 | */ |
| 22 | |
| 23 | #ifndef __ASM_ARCH_MXC_MX2x_H__ |
| 24 | #define __ASM_ARCH_MXC_MX2x_H__ |
| 25 | |
| Holger Schurig | 260a1fd | 2009-01-26 16:34:53 +0100 | [diff] [blame] | 26 | /* The following addresses are common between i.MX21 and i.MX27 */ |
| 27 | |
| 28 | /* Register offests */ |
| 29 | #define AIPI_BASE_ADDR 0x10000000 |
| 30 | #define AIPI_BASE_ADDR_VIRT 0xF4000000 |
| 31 | #define AIPI_SIZE SZ_1M |
| 32 | |
| 33 | #define DMA_BASE_ADDR (AIPI_BASE_ADDR + 0x01000) |
| 34 | #define WDOG_BASE_ADDR (AIPI_BASE_ADDR + 0x02000) |
| 35 | #define GPT1_BASE_ADDR (AIPI_BASE_ADDR + 0x03000) |
| 36 | #define GPT2_BASE_ADDR (AIPI_BASE_ADDR + 0x04000) |
| 37 | #define GPT3_BASE_ADDR (AIPI_BASE_ADDR + 0x05000) |
| 38 | #define PWM_BASE_ADDR (AIPI_BASE_ADDR + 0x06000) |
| 39 | #define RTC_BASE_ADDR (AIPI_BASE_ADDR + 0x07000) |
| 40 | #define KPP_BASE_ADDR (AIPI_BASE_ADDR + 0x08000) |
| 41 | #define OWIRE_BASE_ADDR (AIPI_BASE_ADDR + 0x09000) |
| 42 | #define UART1_BASE_ADDR (AIPI_BASE_ADDR + 0x0A000) |
| 43 | #define UART2_BASE_ADDR (AIPI_BASE_ADDR + 0x0B000) |
| 44 | #define UART3_BASE_ADDR (AIPI_BASE_ADDR + 0x0C000) |
| 45 | #define UART4_BASE_ADDR (AIPI_BASE_ADDR + 0x0D000) |
| 46 | #define CSPI1_BASE_ADDR (AIPI_BASE_ADDR + 0x0E000) |
| 47 | #define CSPI2_BASE_ADDR (AIPI_BASE_ADDR + 0x0F000) |
| 48 | #define SSI1_BASE_ADDR (AIPI_BASE_ADDR + 0x10000) |
| 49 | #define SSI2_BASE_ADDR (AIPI_BASE_ADDR + 0x11000) |
| 50 | #define I2C_BASE_ADDR (AIPI_BASE_ADDR + 0x12000) |
| 51 | #define SDHC1_BASE_ADDR (AIPI_BASE_ADDR + 0x13000) |
| 52 | #define SDHC2_BASE_ADDR (AIPI_BASE_ADDR + 0x14000) |
| 53 | #define GPIO_BASE_ADDR (AIPI_BASE_ADDR + 0x15000) |
| 54 | #define AUDMUX_BASE_ADDR (AIPI_BASE_ADDR + 0x16000) |
| 55 | #define CSPI3_BASE_ADDR (AIPI_BASE_ADDR + 0x17000) |
| 56 | #define LCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x21000) |
| 57 | #define SLCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x22000) |
| 58 | #define USBOTG_BASE_ADDR (AIPI_BASE_ADDR + 0x24000) |
| 59 | #define EMMA_PP_BASE_ADDR (AIPI_BASE_ADDR + 0x26000) |
| 60 | #define EMMA_PRP_BASE_ADDR (AIPI_BASE_ADDR + 0x26400) |
| 61 | #define CCM_BASE_ADDR (AIPI_BASE_ADDR + 0x27000) |
| 62 | #define SYSCTRL_BASE_ADDR (AIPI_BASE_ADDR + 0x27800) |
| 63 | #define JAM_BASE_ADDR (AIPI_BASE_ADDR + 0x3E000) |
| 64 | #define MAX_BASE_ADDR (AIPI_BASE_ADDR + 0x3F000) |
| 65 | |
| 66 | #define AVIC_BASE_ADDR 0x10040000 |
| 67 | |
| 68 | #define SAHB1_BASE_ADDR 0x80000000 |
| 69 | #define SAHB1_BASE_ADDR_VIRT 0xF4100000 |
| 70 | #define SAHB1_SIZE SZ_1M |
| 71 | |
| 72 | #define CSI_BASE_ADDR (SAHB1_BASE_ADDR + 0x0000) |
| 73 | |
| 74 | /* |
| 75 | * This macro defines the physical to virtual address mapping for all the |
| 76 | * peripheral modules. It is used by passing in the physical address as x |
| 77 | * and returning the virtual address. If the physical address is not mapped, |
| 78 | * it returns 0xDEADBEEF |
| 79 | */ |
| 80 | #define IO_ADDRESS(x) \ |
| 81 | (void __force __iomem *) \ |
| 82 | (((x >= AIPI_BASE_ADDR) && (x < (AIPI_BASE_ADDR + AIPI_SIZE))) ? \ |
| 83 | AIPI_IO_ADDRESS(x) : \ |
| 84 | ((x >= SAHB1_BASE_ADDR) && (x < (SAHB1_BASE_ADDR + SAHB1_SIZE))) ? \ |
| 85 | SAHB1_IO_ADDRESS(x) : \ |
| 86 | ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? \ |
| 87 | X_MEMC_IO_ADDRESS(x) : 0xDEADBEEF) |
| 88 | |
| 89 | /* define the address mapping macros: in physical address order */ |
| 90 | #define AIPI_IO_ADDRESS(x) \ |
| 91 | (((x) - AIPI_BASE_ADDR) + AIPI_BASE_ADDR_VIRT) |
| 92 | |
| 93 | #define AVIC_IO_ADDRESS(x) AIPI_IO_ADDRESS(x) |
| 94 | |
| 95 | #define SAHB1_IO_ADDRESS(x) \ |
| 96 | (((x) - SAHB1_BASE_ADDR) + SAHB1_BASE_ADDR_VIRT) |
| 97 | |
| 98 | #define CS4_IO_ADDRESS(x) \ |
| 99 | (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT) |
| 100 | |
| 101 | #define X_MEMC_IO_ADDRESS(x) \ |
| 102 | (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) |
| 103 | |
| 104 | #define PCMCIA_IO_ADDRESS(x) \ |
| 105 | (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) |
| 106 | |
| 107 | /* fixed interrupt numbers */ |
| 108 | #define MXC_INT_LCDC 61 |
| 109 | #define MXC_INT_SLCDC 60 |
| 110 | #define MXC_INT_EMMAPP 52 |
| 111 | #define MXC_INT_EMMAPRP 51 |
| 112 | #define MXC_INT_DMACH15 47 |
| 113 | #define MXC_INT_DMACH14 46 |
| 114 | #define MXC_INT_DMACH13 45 |
| 115 | #define MXC_INT_DMACH12 44 |
| 116 | #define MXC_INT_DMACH11 43 |
| 117 | #define MXC_INT_DMACH10 42 |
| 118 | #define MXC_INT_DMACH9 41 |
| 119 | #define MXC_INT_DMACH8 40 |
| 120 | #define MXC_INT_DMACH7 39 |
| 121 | #define MXC_INT_DMACH6 38 |
| 122 | #define MXC_INT_DMACH5 37 |
| 123 | #define MXC_INT_DMACH4 36 |
| 124 | #define MXC_INT_DMACH3 35 |
| 125 | #define MXC_INT_DMACH2 34 |
| 126 | #define MXC_INT_DMACH1 33 |
| 127 | #define MXC_INT_DMACH0 32 |
| 128 | #define MXC_INT_CSI 31 |
| 129 | #define MXC_INT_NANDFC 29 |
| 130 | #define MXC_INT_PCMCIA 28 |
| 131 | #define MXC_INT_WDOG 27 |
| 132 | #define MXC_INT_GPT1 26 |
| 133 | #define MXC_INT_GPT2 25 |
| 134 | #define MXC_INT_GPT3 24 |
| 135 | #define MXC_INT_GPT INT_GPT1 |
| 136 | #define MXC_INT_PWM 23 |
| 137 | #define MXC_INT_RTC 22 |
| 138 | #define MXC_INT_KPP 21 |
| 139 | #define MXC_INT_UART1 20 |
| 140 | #define MXC_INT_UART2 19 |
| 141 | #define MXC_INT_UART3 18 |
| 142 | #define MXC_INT_UART4 17 |
| 143 | #define MXC_INT_CSPI1 16 |
| 144 | #define MXC_INT_CSPI2 15 |
| 145 | #define MXC_INT_SSI1 14 |
| 146 | #define MXC_INT_SSI2 13 |
| 147 | #define MXC_INT_I2C 12 |
| 148 | #define MXC_INT_SDHC1 11 |
| 149 | #define MXC_INT_SDHC2 10 |
| 150 | #define MXC_INT_GPIO 8 |
| 151 | #define MXC_INT_CSPI3 6 |
| 152 | |
| Holger Schurig | 260a1fd | 2009-01-26 16:34:53 +0100 | [diff] [blame] | 153 | /* fixed DMA request numbers */ |
| 154 | #define DMA_REQ_CSI_RX 31 |
| 155 | #define DMA_REQ_CSI_STAT 30 |
| 156 | #define DMA_REQ_UART1_TX 27 |
| 157 | #define DMA_REQ_UART1_RX 26 |
| 158 | #define DMA_REQ_UART2_TX 25 |
| 159 | #define DMA_REQ_UART2_RX 24 |
| 160 | #define DMA_REQ_UART3_TX 23 |
| 161 | #define DMA_REQ_UART3_RX 22 |
| 162 | #define DMA_REQ_UART4_TX 21 |
| 163 | #define DMA_REQ_UART4_RX 20 |
| 164 | #define DMA_REQ_CSPI1_TX 19 |
| 165 | #define DMA_REQ_CSPI1_RX 18 |
| 166 | #define DMA_REQ_CSPI2_TX 17 |
| 167 | #define DMA_REQ_CSPI2_RX 16 |
| 168 | #define DMA_REQ_SSI1_TX1 15 |
| 169 | #define DMA_REQ_SSI1_RX1 14 |
| 170 | #define DMA_REQ_SSI1_TX0 13 |
| 171 | #define DMA_REQ_SSI1_RX0 12 |
| 172 | #define DMA_REQ_SSI2_TX1 11 |
| 173 | #define DMA_REQ_SSI2_RX1 10 |
| 174 | #define DMA_REQ_SSI2_TX0 9 |
| 175 | #define DMA_REQ_SSI2_RX0 8 |
| 176 | #define DMA_REQ_SDHC1 7 |
| 177 | #define DMA_REQ_SDHC2 6 |
| 178 | #define DMA_REQ_EXT 3 |
| 179 | #define DMA_REQ_CSPI3_TX 2 |
| 180 | #define DMA_REQ_CSPI3_RX 1 |
| 181 | |
| 182 | #endif /* __ASM_ARCH_MXC_MX2x_H__ */ |