| Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 1 | /* arch/arm/plat-omap/include/mach/omap16xx.h |
| 2 | * |
| 3 | * Hardware definitions for TI OMAP1610/5912/1710 processors. |
| 4 | * |
| 5 | * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it |
| 8 | * under the terms of the GNU General Public License as published by the |
| 9 | * Free Software Foundation; either version 2 of the License, or (at your |
| 10 | * option) any later version. |
| 11 | * |
| 12 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED |
| 13 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 14 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN |
| 15 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 16 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 17 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF |
| 18 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| 19 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 20 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 21 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 22 | * |
| 23 | * You should have received a copy of the GNU General Public License along |
| 24 | * with this program; if not, write to the Free Software Foundation, Inc., |
| 25 | * 675 Mass Ave, Cambridge, MA 02139, USA. |
| 26 | */ |
| 27 | |
| 28 | #ifndef __ASM_ARCH_OMAP16XX_H |
| 29 | #define __ASM_ARCH_OMAP16XX_H |
| 30 | |
| 31 | /* |
| 32 | * ---------------------------------------------------------------------------- |
| 33 | * Base addresses |
| 34 | * ---------------------------------------------------------------------------- |
| 35 | */ |
| 36 | |
| 37 | /* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */ |
| 38 | |
| 39 | #define OMAP16XX_DSP_BASE 0xE0000000 |
| 40 | #define OMAP16XX_DSP_SIZE 0x28000 |
| 41 | #define OMAP16XX_DSP_START 0xE0000000 |
| 42 | |
| 43 | #define OMAP16XX_DSPREG_BASE 0xE1000000 |
| 44 | #define OMAP16XX_DSPREG_SIZE SZ_128K |
| 45 | #define OMAP16XX_DSPREG_START 0xE1000000 |
| 46 | |
| Tony Lindgren | 646e3ed | 2008-10-06 15:49:36 +0300 | [diff] [blame] | 47 | #define OMAP16XX_SEC_BASE 0xFFFE4000 |
| 48 | #define OMAP16XX_SEC_DES (OMAP16XX_SEC_BASE + 0x0000) |
| 49 | #define OMAP16XX_SEC_SHA1MD5 (OMAP16XX_SEC_BASE + 0x0800) |
| 50 | #define OMAP16XX_SEC_RNG (OMAP16XX_SEC_BASE + 0x1000) |
| 51 | |
| Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 52 | /* |
| 53 | * --------------------------------------------------------------------------- |
| 54 | * Interrupts |
| 55 | * --------------------------------------------------------------------------- |
| 56 | */ |
| 57 | #define OMAP_IH2_0_BASE (0xfffe0000) |
| 58 | #define OMAP_IH2_1_BASE (0xfffe0100) |
| 59 | #define OMAP_IH2_2_BASE (0xfffe0200) |
| 60 | #define OMAP_IH2_3_BASE (0xfffe0300) |
| 61 | |
| 62 | #define OMAP_IH2_0_ITR (OMAP_IH2_0_BASE + 0x00) |
| 63 | #define OMAP_IH2_0_MIR (OMAP_IH2_0_BASE + 0x04) |
| 64 | #define OMAP_IH2_0_SIR_IRQ (OMAP_IH2_0_BASE + 0x10) |
| 65 | #define OMAP_IH2_0_SIR_FIQ (OMAP_IH2_0_BASE + 0x14) |
| 66 | #define OMAP_IH2_0_CONTROL (OMAP_IH2_0_BASE + 0x18) |
| 67 | #define OMAP_IH2_0_ILR0 (OMAP_IH2_0_BASE + 0x1c) |
| 68 | #define OMAP_IH2_0_ISR (OMAP_IH2_0_BASE + 0x9c) |
| 69 | |
| 70 | #define OMAP_IH2_1_ITR (OMAP_IH2_1_BASE + 0x00) |
| 71 | #define OMAP_IH2_1_MIR (OMAP_IH2_1_BASE + 0x04) |
| 72 | #define OMAP_IH2_1_SIR_IRQ (OMAP_IH2_1_BASE + 0x10) |
| 73 | #define OMAP_IH2_1_SIR_FIQ (OMAP_IH2_1_BASE + 0x14) |
| 74 | #define OMAP_IH2_1_CONTROL (OMAP_IH2_1_BASE + 0x18) |
| 75 | #define OMAP_IH2_1_ILR1 (OMAP_IH2_1_BASE + 0x1c) |
| 76 | #define OMAP_IH2_1_ISR (OMAP_IH2_1_BASE + 0x9c) |
| 77 | |
| 78 | #define OMAP_IH2_2_ITR (OMAP_IH2_2_BASE + 0x00) |
| 79 | #define OMAP_IH2_2_MIR (OMAP_IH2_2_BASE + 0x04) |
| 80 | #define OMAP_IH2_2_SIR_IRQ (OMAP_IH2_2_BASE + 0x10) |
| 81 | #define OMAP_IH2_2_SIR_FIQ (OMAP_IH2_2_BASE + 0x14) |
| 82 | #define OMAP_IH2_2_CONTROL (OMAP_IH2_2_BASE + 0x18) |
| 83 | #define OMAP_IH2_2_ILR2 (OMAP_IH2_2_BASE + 0x1c) |
| 84 | #define OMAP_IH2_2_ISR (OMAP_IH2_2_BASE + 0x9c) |
| 85 | |
| 86 | #define OMAP_IH2_3_ITR (OMAP_IH2_3_BASE + 0x00) |
| 87 | #define OMAP_IH2_3_MIR (OMAP_IH2_3_BASE + 0x04) |
| 88 | #define OMAP_IH2_3_SIR_IRQ (OMAP_IH2_3_BASE + 0x10) |
| 89 | #define OMAP_IH2_3_SIR_FIQ (OMAP_IH2_3_BASE + 0x14) |
| 90 | #define OMAP_IH2_3_CONTROL (OMAP_IH2_3_BASE + 0x18) |
| 91 | #define OMAP_IH2_3_ILR3 (OMAP_IH2_3_BASE + 0x1c) |
| 92 | #define OMAP_IH2_3_ISR (OMAP_IH2_3_BASE + 0x9c) |
| 93 | |
| 94 | /* |
| 95 | * ---------------------------------------------------------------------------- |
| 96 | * Clocks |
| 97 | * ---------------------------------------------------------------------------- |
| 98 | */ |
| 99 | #define OMAP16XX_ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24) |
| 100 | |
| 101 | /* |
| 102 | * ---------------------------------------------------------------------------- |
| 103 | * Pin configuration registers |
| 104 | * ---------------------------------------------------------------------------- |
| 105 | */ |
| 106 | #define OMAP16XX_CONF_VOLTAGE_VDDSHV6 (1 << 8) |
| 107 | #define OMAP16XX_CONF_VOLTAGE_VDDSHV7 (1 << 9) |
| 108 | #define OMAP16XX_CONF_VOLTAGE_VDDSHV8 (1 << 10) |
| 109 | #define OMAP16XX_CONF_VOLTAGE_VDDSHV9 (1 << 11) |
| 110 | #define OMAP16XX_SUBLVDS_CONF_VALID (1 << 13) |
| 111 | |
| 112 | /* |
| 113 | * ---------------------------------------------------------------------------- |
| 114 | * System control registers |
| 115 | * ---------------------------------------------------------------------------- |
| 116 | */ |
| 117 | #define OMAP1610_RESET_CONTROL 0xfffe1140 |
| 118 | |
| 119 | /* |
| 120 | * --------------------------------------------------------------------------- |
| 121 | * TIPB bus interface |
| 122 | * --------------------------------------------------------------------------- |
| 123 | */ |
| 124 | #define TIPB_SWITCH_BASE (0xfffbc800) |
| 125 | #define OMAP16XX_MMCSD2_SSW_MPU_CONF (TIPB_SWITCH_BASE + 0x160) |
| 126 | |
| 127 | /* UART3 Registers Maping through MPU bus */ |
| 128 | #define UART3_RHR (OMAP_UART3_BASE + 0) |
| 129 | #define UART3_THR (OMAP_UART3_BASE + 0) |
| 130 | #define UART3_DLL (OMAP_UART3_BASE + 0) |
| 131 | #define UART3_IER (OMAP_UART3_BASE + 4) |
| 132 | #define UART3_DLH (OMAP_UART3_BASE + 4) |
| 133 | #define UART3_IIR (OMAP_UART3_BASE + 8) |
| 134 | #define UART3_FCR (OMAP_UART3_BASE + 8) |
| 135 | #define UART3_EFR (OMAP_UART3_BASE + 8) |
| 136 | #define UART3_LCR (OMAP_UART3_BASE + 0x0C) |
| 137 | #define UART3_MCR (OMAP_UART3_BASE + 0x10) |
| 138 | #define UART3_XON1_ADDR1 (OMAP_UART3_BASE + 0x10) |
| 139 | #define UART3_XON2_ADDR2 (OMAP_UART3_BASE + 0x14) |
| 140 | #define UART3_LSR (OMAP_UART3_BASE + 0x14) |
| 141 | #define UART3_TCR (OMAP_UART3_BASE + 0x18) |
| 142 | #define UART3_MSR (OMAP_UART3_BASE + 0x18) |
| 143 | #define UART3_XOFF1 (OMAP_UART3_BASE + 0x18) |
| 144 | #define UART3_XOFF2 (OMAP_UART3_BASE + 0x1C) |
| 145 | #define UART3_SPR (OMAP_UART3_BASE + 0x1C) |
| 146 | #define UART3_TLR (OMAP_UART3_BASE + 0x1C) |
| 147 | #define UART3_MDR1 (OMAP_UART3_BASE + 0x20) |
| 148 | #define UART3_MDR2 (OMAP_UART3_BASE + 0x24) |
| 149 | #define UART3_SFLSR (OMAP_UART3_BASE + 0x28) |
| 150 | #define UART3_TXFLL (OMAP_UART3_BASE + 0x28) |
| 151 | #define UART3_RESUME (OMAP_UART3_BASE + 0x2C) |
| 152 | #define UART3_TXFLH (OMAP_UART3_BASE + 0x2C) |
| 153 | #define UART3_SFREGL (OMAP_UART3_BASE + 0x30) |
| 154 | #define UART3_RXFLL (OMAP_UART3_BASE + 0x30) |
| 155 | #define UART3_SFREGH (OMAP_UART3_BASE + 0x34) |
| 156 | #define UART3_RXFLH (OMAP_UART3_BASE + 0x34) |
| 157 | #define UART3_BLR (OMAP_UART3_BASE + 0x38) |
| 158 | #define UART3_ACREG (OMAP_UART3_BASE + 0x3C) |
| 159 | #define UART3_DIV16 (OMAP_UART3_BASE + 0x3C) |
| 160 | #define UART3_SCR (OMAP_UART3_BASE + 0x40) |
| 161 | #define UART3_SSR (OMAP_UART3_BASE + 0x44) |
| 162 | #define UART3_EBLR (OMAP_UART3_BASE + 0x48) |
| 163 | #define UART3_OSC_12M_SEL (OMAP_UART3_BASE + 0x4C) |
| 164 | #define UART3_MVR (OMAP_UART3_BASE + 0x50) |
| 165 | |
| 166 | /* |
| 167 | * --------------------------------------------------------------------------- |
| 168 | * Watchdog timer |
| 169 | * --------------------------------------------------------------------------- |
| 170 | */ |
| 171 | |
| 172 | /* 32-bit Watchdog timer in OMAP 16XX */ |
| 173 | #define OMAP_16XX_WATCHDOG_BASE (0xfffeb000) |
| 174 | #define OMAP_16XX_WIDR (OMAP_16XX_WATCHDOG_BASE + 0x00) |
| 175 | #define OMAP_16XX_WD_SYSCONFIG (OMAP_16XX_WATCHDOG_BASE + 0x10) |
| 176 | #define OMAP_16XX_WD_SYSSTATUS (OMAP_16XX_WATCHDOG_BASE + 0x14) |
| 177 | #define OMAP_16XX_WCLR (OMAP_16XX_WATCHDOG_BASE + 0x24) |
| 178 | #define OMAP_16XX_WCRR (OMAP_16XX_WATCHDOG_BASE + 0x28) |
| 179 | #define OMAP_16XX_WLDR (OMAP_16XX_WATCHDOG_BASE + 0x2c) |
| 180 | #define OMAP_16XX_WTGR (OMAP_16XX_WATCHDOG_BASE + 0x30) |
| 181 | #define OMAP_16XX_WWPS (OMAP_16XX_WATCHDOG_BASE + 0x34) |
| 182 | #define OMAP_16XX_WSPR (OMAP_16XX_WATCHDOG_BASE + 0x48) |
| 183 | |
| 184 | #define WCLR_PRE_SHIFT 5 |
| 185 | #define WCLR_PTV_SHIFT 2 |
| 186 | |
| 187 | #define WWPS_W_PEND_WSPR (1 << 4) |
| 188 | #define WWPS_W_PEND_WTGR (1 << 3) |
| 189 | #define WWPS_W_PEND_WLDR (1 << 2) |
| 190 | #define WWPS_W_PEND_WCRR (1 << 1) |
| 191 | #define WWPS_W_PEND_WCLR (1 << 0) |
| 192 | |
| 193 | #define WSPR_ENABLE_0 (0x0000bbbb) |
| 194 | #define WSPR_ENABLE_1 (0x00004444) |
| 195 | #define WSPR_DISABLE_0 (0x0000aaaa) |
| 196 | #define WSPR_DISABLE_1 (0x00005555) |
| 197 | |
| Tony Lindgren | 646e3ed | 2008-10-06 15:49:36 +0300 | [diff] [blame] | 198 | #define OMAP16XX_DSP_MMU_BASE (0xfffed200) |
| Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 199 | #define OMAP16XX_MAILBOX_BASE (0xfffcf000) |
| 200 | |
| 201 | #endif /* __ASM_ARCH_OMAP16XX_H */ |
| 202 | |