| Byungho Min | 8acd1ad | 2009-06-23 21:40:15 +0900 | [diff] [blame] | 1 | /* linux/arch/arm/plat-s5pc1xx/cpu.c |
| 2 | * |
| 3 | * Copyright 2009 Samsung Electronics Co. |
| 4 | * Byungho Min <bhmin@samsung.com> |
| 5 | * |
| 6 | * S5PC1XX CPU Support |
| 7 | * |
| 8 | * Based on plat-s3c64xx/cpu.c |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License version 2 as |
| 12 | * published by the Free Software Foundation. |
| 13 | */ |
| 14 | |
| 15 | #include <linux/init.h> |
| 16 | #include <linux/module.h> |
| 17 | #include <linux/interrupt.h> |
| 18 | #include <linux/ioport.h> |
| 19 | #include <linux/serial_core.h> |
| 20 | #include <linux/platform_device.h> |
| 21 | #include <linux/io.h> |
| 22 | |
| 23 | #include <mach/hardware.h> |
| 24 | #include <mach/map.h> |
| 25 | |
| 26 | #include <asm/mach/map.h> |
| 27 | |
| 28 | #include <plat/regs-serial.h> |
| 29 | |
| 30 | #include <plat/cpu.h> |
| 31 | #include <plat/devs.h> |
| 32 | #include <plat/clock.h> |
| 33 | |
| 34 | #include <plat/s5pc100.h> |
| 35 | |
| 36 | /* table of supported CPUs */ |
| 37 | |
| 38 | static const char name_s5pc100[] = "S5PC100"; |
| 39 | |
| 40 | static struct cpu_table cpu_ids[] __initdata = { |
| 41 | { |
| 42 | .idcode = 0x43100000, |
| 43 | .idmask = 0xfffff000, |
| 44 | .map_io = s5pc100_map_io, |
| 45 | .init_clocks = s5pc100_init_clocks, |
| 46 | .init_uarts = s5pc100_init_uarts, |
| 47 | .init = s5pc100_init, |
| 48 | .name = name_s5pc100, |
| 49 | }, |
| 50 | }; |
| 51 | /* minimal IO mapping */ |
| 52 | |
| 53 | /* see notes on uart map in arch/arm/mach-s5pc100/include/mach/debug-macro.S */ |
| 54 | #define UART_OFFS (S3C_PA_UART & 0xffff) |
| 55 | |
| 56 | static struct map_desc s5pc1xx_iodesc[] __initdata = { |
| 57 | { |
| 58 | .virtual = (unsigned long)S5PC1XX_VA_CHIPID, |
| 59 | .pfn = __phys_to_pfn(S5PC1XX_PA_CHIPID), |
| 60 | .length = SZ_16, |
| 61 | .type = MT_DEVICE, |
| 62 | }, { |
| 63 | .virtual = (unsigned long)S5PC1XX_VA_CLK, |
| 64 | .pfn = __phys_to_pfn(S5PC1XX_PA_CLK), |
| 65 | .length = SZ_4K, |
| 66 | .type = MT_DEVICE, |
| 67 | }, { |
| 68 | .virtual = (unsigned long)S5PC1XX_VA_PWR, |
| 69 | .pfn = __phys_to_pfn(S5PC1XX_PA_PWR), |
| 70 | .length = SZ_4K, |
| 71 | .type = MT_DEVICE, |
| 72 | }, { |
| 73 | .virtual = (unsigned long)(S5PC1XX_VA_UART), |
| 74 | .pfn = __phys_to_pfn(S5PC1XX_PA_UART), |
| 75 | .length = SZ_4K, |
| 76 | .type = MT_DEVICE, |
| 77 | }, { |
| 78 | .virtual = (unsigned long)S5PC1XX_VA_VIC(0), |
| 79 | .pfn = __phys_to_pfn(S5PC1XX_PA_VIC(0)), |
| 80 | .length = SZ_4K, |
| 81 | .type = MT_DEVICE, |
| 82 | }, { |
| 83 | .virtual = (unsigned long)S5PC1XX_VA_VIC(1), |
| 84 | .pfn = __phys_to_pfn(S5PC1XX_PA_VIC(1)), |
| 85 | .length = SZ_4K, |
| 86 | .type = MT_DEVICE, |
| 87 | }, { |
| 88 | .virtual = (unsigned long)S5PC1XX_VA_VIC(2), |
| 89 | .pfn = __phys_to_pfn(S5PC1XX_PA_VIC(2)), |
| 90 | .length = SZ_4K, |
| 91 | .type = MT_DEVICE, |
| 92 | }, { |
| 93 | .virtual = (unsigned long)S5PC1XX_VA_TIMER, |
| 94 | .pfn = __phys_to_pfn(S5PC1XX_PA_TIMER), |
| 95 | .length = SZ_256, |
| 96 | .type = MT_DEVICE, |
| 97 | }, |
| 98 | }; |
| 99 | |
| 100 | /* read cpu identification code */ |
| 101 | |
| 102 | void __init s5pc1xx_init_io(struct map_desc *mach_desc, int size) |
| 103 | { |
| 104 | unsigned long idcode; |
| 105 | |
| 106 | /* initialise the io descriptors we need for initialisation */ |
| 107 | iotable_init(s5pc1xx_iodesc, ARRAY_SIZE(s5pc1xx_iodesc)); |
| 108 | iotable_init(mach_desc, size); |
| 109 | |
| 110 | idcode = __raw_readl(S5PC1XX_VA_CHIPID); |
| 111 | s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids)); |
| 112 | } |