| Byungho Min | c1cc3db | 2009-06-23 21:39:56 +0900 | [diff] [blame] | 1 | /* arch/arm/plat-s5pc1xx/include/plat/regs-clock.h |
| 2 | * |
| 3 | * Copyright 2009 Samsung Electronics Co. |
| 4 | * Byungho Min <bhmin@samsung.com> |
| 5 | * |
| 6 | * S5PC1XX clock register definitions |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | */ |
| 12 | |
| 13 | #ifndef __PLAT_REGS_CLOCK_H |
| 14 | #define __PLAT_REGS_CLOCK_H __FILE__ |
| 15 | |
| 16 | #define S5PC1XX_CLKREG(x) (S5PC1XX_VA_CLK + (x)) |
| 17 | |
| 18 | #define S5PC1XX_APLL_LOCK S5PC1XX_CLKREG(0x00) |
| 19 | #define S5PC1XX_MPLL_LOCK S5PC1XX_CLKREG(0x04) |
| 20 | #define S5PC1XX_EPLL_LOCK S5PC1XX_CLKREG(0x08) |
| 21 | #define S5PC100_HPLL_LOCK S5PC1XX_CLKREG(0x0C) |
| 22 | |
| 23 | #define S5PC1XX_APLL_CON S5PC1XX_CLKREG(0x100) |
| 24 | #define S5PC1XX_MPLL_CON S5PC1XX_CLKREG(0x104) |
| 25 | #define S5PC1XX_EPLL_CON S5PC1XX_CLKREG(0x108) |
| 26 | #define S5PC100_HPLL_CON S5PC1XX_CLKREG(0x10C) |
| 27 | |
| 28 | #define S5PC1XX_CLK_SRC0 S5PC1XX_CLKREG(0x200) |
| 29 | #define S5PC1XX_CLK_SRC1 S5PC1XX_CLKREG(0x204) |
| 30 | #define S5PC1XX_CLK_SRC2 S5PC1XX_CLKREG(0x208) |
| 31 | #define S5PC1XX_CLK_SRC3 S5PC1XX_CLKREG(0x20C) |
| 32 | |
| 33 | #define S5PC1XX_CLK_DIV0 S5PC1XX_CLKREG(0x300) |
| 34 | #define S5PC1XX_CLK_DIV1 S5PC1XX_CLKREG(0x304) |
| 35 | #define S5PC1XX_CLK_DIV2 S5PC1XX_CLKREG(0x308) |
| 36 | #define S5PC1XX_CLK_DIV3 S5PC1XX_CLKREG(0x30C) |
| 37 | #define S5PC1XX_CLK_DIV4 S5PC1XX_CLKREG(0x310) |
| 38 | |
| 39 | #define S5PC100_CLK_OUT S5PC1XX_CLKREG(0x400) |
| 40 | |
| 41 | #define S5PC100_CLKGATE_D00 S5PC1XX_CLKREG(0x500) |
| 42 | #define S5PC100_CLKGATE_D01 S5PC1XX_CLKREG(0x504) |
| 43 | #define S5PC100_CLKGATE_D02 S5PC1XX_CLKREG(0x508) |
| 44 | |
| 45 | #define S5PC100_CLKGATE_D10 S5PC1XX_CLKREG(0x520) |
| 46 | #define S5PC100_CLKGATE_D11 S5PC1XX_CLKREG(0x524) |
| 47 | #define S5PC100_CLKGATE_D12 S5PC1XX_CLKREG(0x528) |
| 48 | #define S5PC100_CLKGATE_D13 S5PC1XX_CLKREG(0x52C) |
| 49 | #define S5PC100_CLKGATE_D14 S5PC1XX_CLKREG(0x530) |
| 50 | #define S5PC100_CLKGATE_D15 S5PC1XX_CLKREG(0x534) |
| 51 | |
| 52 | #define S5PC100_CLKGATE_D20 S5PC1XX_CLKREG(0x540) |
| 53 | |
| 54 | #define S5PC100_SCLKGATE0 S5PC1XX_CLKREG(0x560) |
| 55 | #define S5PC100_SCLKGATE1 S5PC1XX_CLKREG(0x564) |
| 56 | |
| 57 | #define S5PC100_OTHERS S5PC1XX_CLKREG(0x8200) |
| 58 | |
| 59 | #define S5PC1XX_EPLL_EN (1<<31) |
| 60 | #define S5PC1XX_EPLL_MASK 0xffffffff |
| 61 | #define S5PC1XX_EPLLVAL(_m, _p, _s) ((_m) << 16 | ((_p) << 8) | ((_s))) |
| 62 | |
| 63 | /* CLKSRC0 */ |
| 64 | #define S5PC1XX_CLKSRC0_APLL_MASK (0x1<<0) |
| 65 | #define S5PC1XX_CLKSRC0_APLL_SHIFT (0) |
| 66 | #define S5PC1XX_CLKSRC0_MPLL_MASK (0x1<<4) |
| 67 | #define S5PC1XX_CLKSRC0_MPLL_SHIFT (4) |
| 68 | #define S5PC1XX_CLKSRC0_EPLL_MASK (0x1<<8) |
| 69 | #define S5PC1XX_CLKSRC0_EPLL_SHIFT (8) |
| 70 | #define S5PC100_CLKSRC0_HPLL_MASK (0x1<<12) |
| 71 | #define S5PC100_CLKSRC0_HPLL_SHIFT (12) |
| 72 | #define S5PC100_CLKSRC0_AMMUX_MASK (0x1<<16) |
| 73 | #define S5PC100_CLKSRC0_AMMUX_SHIFT (16) |
| 74 | #define S5PC100_CLKSRC0_HREF_MASK (0x1<<20) |
| 75 | #define S5PC100_CLKSRC0_HREF_SHIFT (20) |
| 76 | #define S5PC1XX_CLKSRC0_ONENAND_MASK (0x1<<24) |
| 77 | #define S5PC1XX_CLKSRC0_ONENAND_SHIFT (24) |
| 78 | |
| 79 | |
| 80 | /* CLKSRC1 */ |
| 81 | #define S5PC100_CLKSRC1_UART_MASK (0x1<<0) |
| 82 | #define S5PC100_CLKSRC1_UART_SHIFT (0) |
| 83 | #define S5PC100_CLKSRC1_SPI0_MASK (0x3<<4) |
| 84 | #define S5PC100_CLKSRC1_SPI0_SHIFT (4) |
| 85 | #define S5PC100_CLKSRC1_SPI1_MASK (0x3<<8) |
| 86 | #define S5PC100_CLKSRC1_SPI1_SHIFT (8) |
| 87 | #define S5PC100_CLKSRC1_SPI2_MASK (0x3<<12) |
| 88 | #define S5PC100_CLKSRC1_SPI2_SHIFT (12) |
| 89 | #define S5PC100_CLKSRC1_IRDA_MASK (0x3<<16) |
| 90 | #define S5PC100_CLKSRC1_IRDA_SHIFT (16) |
| 91 | #define S5PC100_CLKSRC1_UHOST_MASK (0x3<<20) |
| 92 | #define S5PC100_CLKSRC1_UHOST_SHIFT (20) |
| 93 | #define S5PC100_CLKSRC1_CLK48M_MASK (0x1<<24) |
| 94 | #define S5PC100_CLKSRC1_CLK48M_SHIFT (24) |
| 95 | |
| 96 | /* CLKSRC2 */ |
| 97 | #define S5PC100_CLKSRC2_MMC0_MASK (0x3<<0) |
| 98 | #define S5PC100_CLKSRC2_MMC0_SHIFT (0) |
| 99 | #define S5PC100_CLKSRC2_MMC1_MASK (0x3<<4) |
| 100 | #define S5PC100_CLKSRC2_MMC1_SHIFT (4) |
| 101 | #define S5PC100_CLKSRC2_MMC2_MASK (0x3<<8) |
| 102 | #define S5PC100_CLKSRC2_MMC2_SHIFT (8) |
| 103 | #define S5PC100_CLKSRC2_LCD_MASK (0x3<<12) |
| 104 | #define S5PC100_CLKSRC2_LCD_SHIFT (12) |
| 105 | #define S5PC100_CLKSRC2_FIMC0_MASK (0x3<<16) |
| 106 | #define S5PC100_CLKSRC2_FIMC0_SHIFT (16) |
| 107 | #define S5PC100_CLKSRC2_FIMC1_MASK (0x3<<20) |
| 108 | #define S5PC100_CLKSRC2_FIMC1_SHIFT (20) |
| 109 | #define S5PC100_CLKSRC2_FIMC2_MASK (0x3<<24) |
| 110 | #define S5PC100_CLKSRC2_FIMC2_SHIFT (24) |
| 111 | #define S5PC100_CLKSRC2_MIXER_MASK (0x3<<28) |
| 112 | #define S5PC100_CLKSRC2_MIXER_SHIFT (28) |
| 113 | |
| 114 | /* CLKSRC3 */ |
| 115 | #define S5PC100_CLKSRC3_PWI_MASK (0x3<<0) |
| 116 | #define S5PC100_CLKSRC3_PWI_SHIFT (0) |
| 117 | #define S5PC100_CLKSRC3_HCLKD2_MASK (0x1<<4) |
| 118 | #define S5PC100_CLKSRC3_HCLKD2_SHIFT (4) |
| 119 | #define S5PC100_CLKSRC3_I2SD2_MASK (0x3<<8) |
| 120 | #define S5PC100_CLKSRC3_I2SD2_SHIFT (8) |
| 121 | #define S5PC100_CLKSRC3_AUDIO0_MASK (0x7<<12) |
| 122 | #define S5PC100_CLKSRC3_AUDIO0_SHIFT (12) |
| 123 | #define S5PC100_CLKSRC3_AUDIO1_MASK (0x7<<16) |
| 124 | #define S5PC100_CLKSRC3_AUDIO1_SHIFT (16) |
| 125 | #define S5PC100_CLKSRC3_AUDIO2_MASK (0x7<<20) |
| 126 | #define S5PC100_CLKSRC3_AUDIO2_SHIFT (20) |
| 127 | #define S5PC100_CLKSRC3_SPDIF_MASK (0x3<<24) |
| 128 | #define S5PC100_CLKSRC3_SPDIF_SHIFT (24) |
| 129 | |
| 130 | |
| 131 | /* CLKDIV0 */ |
| 132 | #define S5PC1XX_CLKDIV0_APLL_MASK (0x1<<0) |
| 133 | #define S5PC1XX_CLKDIV0_APLL_SHIFT (0) |
| 134 | #define S5PC100_CLKDIV0_ARM_MASK (0x7<<4) |
| 135 | #define S5PC100_CLKDIV0_ARM_SHIFT (4) |
| 136 | #define S5PC100_CLKDIV0_D0_MASK (0x7<<8) |
| 137 | #define S5PC100_CLKDIV0_D0_SHIFT (8) |
| 138 | #define S5PC100_CLKDIV0_PCLKD0_MASK (0x7<<12) |
| 139 | #define S5PC100_CLKDIV0_PCLKD0_SHIFT (12) |
| 140 | #define S5PC100_CLKDIV0_SECSS_MASK (0x7<<16) |
| 141 | #define S5PC100_CLKDIV0_SECSS_SHIFT (16) |
| 142 | |
| 143 | /* CLKDIV1 */ |
| 144 | #define S5PC100_CLKDIV1_AM_MASK (0x7<<0) |
| 145 | #define S5PC100_CLKDIV1_AM_SHIFT (0) |
| 146 | #define S5PC100_CLKDIV1_MPLL_MASK (0x3<<4) |
| 147 | #define S5PC100_CLKDIV1_MPLL_SHIFT (4) |
| 148 | #define S5PC100_CLKDIV1_MPLL2_MASK (0x1<<8) |
| 149 | #define S5PC100_CLKDIV1_MPLL2_SHIFT (8) |
| 150 | #define S5PC100_CLKDIV1_D1_MASK (0x7<<12) |
| 151 | #define S5PC100_CLKDIV1_D1_SHIFT (12) |
| 152 | #define S5PC100_CLKDIV1_PCLKD1_MASK (0x7<<16) |
| 153 | #define S5PC100_CLKDIV1_PCLKD1_SHIFT (16) |
| 154 | #define S5PC100_CLKDIV1_ONENAND_MASK (0x3<<20) |
| 155 | #define S5PC100_CLKDIV1_ONENAND_SHIFT (20) |
| 156 | #define S5PC100_CLKDIV1_CAM_MASK (0x1F<<24) |
| 157 | #define S5PC100_CLKDIV1_CAM_SHIFT (24) |
| 158 | |
| 159 | /* CLKDIV2 */ |
| 160 | #define S5PC100_CLKDIV2_UART_MASK (0x7<<0) |
| 161 | #define S5PC100_CLKDIV2_UART_SHIFT (0) |
| 162 | #define S5PC100_CLKDIV2_SPI0_MASK (0xf<<4) |
| 163 | #define S5PC100_CLKDIV2_SPI0_SHIFT (4) |
| 164 | #define S5PC100_CLKDIV2_SPI1_MASK (0xf<<8) |
| 165 | #define S5PC100_CLKDIV2_SPI1_SHIFT (8) |
| 166 | #define S5PC100_CLKDIV2_SPI2_MASK (0xf<<12) |
| 167 | #define S5PC100_CLKDIV2_SPI2_SHIFT (12) |
| 168 | #define S5PC100_CLKDIV2_IRDA_MASK (0xf<<16) |
| 169 | #define S5PC100_CLKDIV2_IRDA_SHIFT (16) |
| 170 | #define S5PC100_CLKDIV2_UHOST_MASK (0xf<<20) |
| 171 | #define S5PC100_CLKDIV2_UHOST_SHIFT (20) |
| 172 | |
| 173 | /* CLKDIV3 */ |
| 174 | #define S5PC100_CLKDIV3_MMC0_MASK (0xf<<0) |
| 175 | #define S5PC100_CLKDIV3_MMC0_SHIFT (0) |
| 176 | #define S5PC100_CLKDIV3_MMC1_MASK (0xf<<4) |
| 177 | #define S5PC100_CLKDIV3_MMC1_SHIFT (4) |
| 178 | #define S5PC100_CLKDIV3_MMC2_MASK (0xf<<8) |
| 179 | #define S5PC100_CLKDIV3_MMC2_SHIFT (8) |
| 180 | #define S5PC100_CLKDIV3_LCD_MASK (0xf<<12) |
| 181 | #define S5PC100_CLKDIV3_LCD_SHIFT (12) |
| 182 | #define S5PC100_CLKDIV3_FIMC0_MASK (0xf<<16) |
| 183 | #define S5PC100_CLKDIV3_FIMC0_SHIFT (16) |
| 184 | #define S5PC100_CLKDIV3_FIMC1_MASK (0xf<<20) |
| 185 | #define S5PC100_CLKDIV3_FIMC1_SHIFT (20) |
| 186 | #define S5PC100_CLKDIV3_FIMC2_MASK (0xf<<24) |
| 187 | #define S5PC100_CLKDIV3_FIMC2_SHIFT (24) |
| 188 | #define S5PC100_CLKDIV3_HDMI_MASK (0xf<<28) |
| 189 | #define S5PC100_CLKDIV3_HDMI_SHIFT (28) |
| 190 | |
| 191 | /* CLKDIV4 */ |
| 192 | #define S5PC100_CLKDIV4_PWI_MASK (0x7<<0) |
| 193 | #define S5PC100_CLKDIV4_PWI_SHIFT (0) |
| 194 | #define S5PC100_CLKDIV4_HCLKD2_MASK (0x7<<4) |
| 195 | #define S5PC100_CLKDIV4_HCLKD2_SHIFT (4) |
| 196 | #define S5PC100_CLKDIV4_I2SD2_MASK (0xf<<8) |
| 197 | #define S5PC100_CLKDIV4_I2SD2_SHIFT (8) |
| 198 | #define S5PC100_CLKDIV4_AUDIO0_MASK (0xf<<12) |
| 199 | #define S5PC100_CLKDIV4_AUDIO0_SHIFT (12) |
| 200 | #define S5PC100_CLKDIV4_AUDIO1_MASK (0xf<<16) |
| 201 | #define S5PC100_CLKDIV4_AUDIO1_SHIFT (16) |
| 202 | #define S5PC100_CLKDIV4_AUDIO2_MASK (0xf<<20) |
| 203 | #define S5PC100_CLKDIV4_AUDIO2_SHIFT (20) |
| 204 | |
| 205 | |
| 206 | /* HCLKD0/PCLKD0 Clock Gate 0 Registers */ |
| 207 | #define S5PC100_CLKGATE_D00_INTC (1<<0) |
| 208 | #define S5PC100_CLKGATE_D00_TZIC (1<<1) |
| 209 | #define S5PC100_CLKGATE_D00_CFCON (1<<2) |
| 210 | #define S5PC100_CLKGATE_D00_MDMA (1<<3) |
| 211 | #define S5PC100_CLKGATE_D00_G2D (1<<4) |
| 212 | #define S5PC100_CLKGATE_D00_SECSS (1<<5) |
| 213 | #define S5PC100_CLKGATE_D00_CSSYS (1<<6) |
| 214 | |
| 215 | /* HCLKD0/PCLKD0 Clock Gate 1 Registers */ |
| 216 | #define S5PC100_CLKGATE_D01_DMC (1<<0) |
| 217 | #define S5PC100_CLKGATE_D01_SROMC (1<<1) |
| 218 | #define S5PC100_CLKGATE_D01_ONENAND (1<<2) |
| 219 | #define S5PC100_CLKGATE_D01_NFCON (1<<3) |
| 220 | #define S5PC100_CLKGATE_D01_INTMEM (1<<4) |
| 221 | #define S5PC100_CLKGATE_D01_EBI (1<<5) |
| 222 | |
| 223 | /* PCLKD0 Clock Gate 2 Registers */ |
| 224 | #define S5PC100_CLKGATE_D02_SECKEY (1<<1) |
| 225 | #define S5PC100_CLKGATE_D02_SDM (1<<2) |
| 226 | |
| 227 | /* HCLKD1/PCLKD1 Clock Gate 0 Registers */ |
| 228 | #define S5PC100_CLKGATE_D10_PDMA0 (1<<0) |
| 229 | #define S5PC100_CLKGATE_D10_PDMA1 (1<<1) |
| 230 | #define S5PC100_CLKGATE_D10_USBHOST (1<<2) |
| 231 | #define S5PC100_CLKGATE_D10_USBOTG (1<<3) |
| 232 | #define S5PC100_CLKGATE_D10_MODEMIF (1<<4) |
| 233 | #define S5PC100_CLKGATE_D10_HSMMC0 (1<<5) |
| 234 | #define S5PC100_CLKGATE_D10_HSMMC1 (1<<6) |
| 235 | #define S5PC100_CLKGATE_D10_HSMMC2 (1<<7) |
| 236 | |
| 237 | /* HCLKD1/PCLKD1 Clock Gate 1 Registers */ |
| 238 | #define S5PC100_CLKGATE_D11_LCD (1<<0) |
| 239 | #define S5PC100_CLKGATE_D11_ROTATOR (1<<1) |
| 240 | #define S5PC100_CLKGATE_D11_FIMC0 (1<<2) |
| 241 | #define S5PC100_CLKGATE_D11_FIMC1 (1<<3) |
| 242 | #define S5PC100_CLKGATE_D11_FIMC2 (1<<4) |
| 243 | #define S5PC100_CLKGATE_D11_JPEG (1<<5) |
| 244 | #define S5PC100_CLKGATE_D11_DSI (1<<6) |
| 245 | #define S5PC100_CLKGATE_D11_CSI (1<<7) |
| 246 | #define S5PC100_CLKGATE_D11_G3D (1<<8) |
| 247 | |
| 248 | /* HCLKD1/PCLKD1 Clock Gate 2 Registers */ |
| 249 | #define S5PC100_CLKGATE_D12_TV (1<<0) |
| 250 | #define S5PC100_CLKGATE_D12_VP (1<<1) |
| 251 | #define S5PC100_CLKGATE_D12_MIXER (1<<2) |
| 252 | #define S5PC100_CLKGATE_D12_HDMI (1<<3) |
| 253 | #define S5PC100_CLKGATE_D12_MFC (1<<4) |
| 254 | |
| 255 | /* HCLKD1/PCLKD1 Clock Gate 3 Registers */ |
| 256 | #define S5PC100_CLKGATE_D13_CHIPID (1<<0) |
| 257 | #define S5PC100_CLKGATE_D13_GPIO (1<<1) |
| 258 | #define S5PC100_CLKGATE_D13_APC (1<<2) |
| 259 | #define S5PC100_CLKGATE_D13_IEC (1<<3) |
| 260 | #define S5PC100_CLKGATE_D13_PWM (1<<6) |
| 261 | #define S5PC100_CLKGATE_D13_SYSTIMER (1<<7) |
| 262 | #define S5PC100_CLKGATE_D13_WDT (1<<8) |
| 263 | #define S5PC100_CLKGATE_D13_RTC (1<<9) |
| 264 | |
| 265 | /* HCLKD1/PCLKD1 Clock Gate 4 Registers */ |
| 266 | #define S5PC100_CLKGATE_D14_UART0 (1<<0) |
| 267 | #define S5PC100_CLKGATE_D14_UART1 (1<<1) |
| 268 | #define S5PC100_CLKGATE_D14_UART2 (1<<2) |
| 269 | #define S5PC100_CLKGATE_D14_UART3 (1<<3) |
| 270 | #define S5PC100_CLKGATE_D14_IIC (1<<4) |
| 271 | #define S5PC100_CLKGATE_D14_HDMI_IIC (1<<5) |
| 272 | #define S5PC100_CLKGATE_D14_SPI0 (1<<6) |
| 273 | #define S5PC100_CLKGATE_D14_SPI1 (1<<7) |
| 274 | #define S5PC100_CLKGATE_D14_SPI2 (1<<8) |
| 275 | #define S5PC100_CLKGATE_D14_IRDA (1<<9) |
| 276 | #define S5PC100_CLKGATE_D14_CCAN0 (1<<10) |
| 277 | #define S5PC100_CLKGATE_D14_CCAN1 (1<<11) |
| 278 | #define S5PC100_CLKGATE_D14_HSITX (1<<12) |
| 279 | #define S5PC100_CLKGATE_D14_HSIRX (1<<13) |
| 280 | |
| 281 | /* HCLKD1/PCLKD1 Clock Gate 5 Registers */ |
| 282 | #define S5PC100_CLKGATE_D15_IIS0 (1<<0) |
| 283 | #define S5PC100_CLKGATE_D15_IIS1 (1<<1) |
| 284 | #define S5PC100_CLKGATE_D15_IIS2 (1<<2) |
| 285 | #define S5PC100_CLKGATE_D15_AC97 (1<<3) |
| 286 | #define S5PC100_CLKGATE_D15_PCM0 (1<<4) |
| 287 | #define S5PC100_CLKGATE_D15_PCM1 (1<<5) |
| 288 | #define S5PC100_CLKGATE_D15_SPDIF (1<<6) |
| 289 | #define S5PC100_CLKGATE_D15_TSADC (1<<7) |
| 290 | #define S5PC100_CLKGATE_D15_KEYIF (1<<8) |
| 291 | #define S5PC100_CLKGATE_D15_CG (1<<9) |
| 292 | |
| 293 | /* HCLKD2 Clock Gate 0 Registers */ |
| 294 | #define S5PC100_CLKGATE_D20_HCLKD2 (1<<0) |
| 295 | #define S5PC100_CLKGATE_D20_I2SD2 (1<<1) |
| 296 | |
| 297 | /* Special Clock Gate 0 Registers */ |
| 298 | #define S5PC1XX_CLKGATE_SCLK0_HPM (1<<0) |
| 299 | #define S5PC1XX_CLKGATE_SCLK0_PWI (1<<1) |
| 300 | #define S5PC100_CLKGATE_SCLK0_ONENAND (1<<2) |
| 301 | #define S5PC100_CLKGATE_SCLK0_UART (1<<3) |
| 302 | #define S5PC100_CLKGATE_SCLK0_SPI0 (1<<4) |
| 303 | #define S5PC100_CLKGATE_SCLK0_SPI1 (1<<5) |
| 304 | #define S5PC100_CLKGATE_SCLK0_SPI2 (1<<6) |
| 305 | #define S5PC100_CLKGATE_SCLK0_SPI0_48 (1<<7) |
| 306 | #define S5PC100_CLKGATE_SCLK0_SPI1_48 (1<<8) |
| 307 | #define S5PC100_CLKGATE_SCLK0_SPI2_48 (1<<9) |
| 308 | #define S5PC100_CLKGATE_SCLK0_IRDA (1<<10) |
| 309 | #define S5PC100_CLKGATE_SCLK0_USBHOST (1<<11) |
| 310 | #define S5PC100_CLKGATE_SCLK0_MMC0 (1<<12) |
| 311 | #define S5PC100_CLKGATE_SCLK0_MMC1 (1<<13) |
| 312 | #define S5PC100_CLKGATE_SCLK0_MMC2 (1<<14) |
| 313 | #define S5PC100_CLKGATE_SCLK0_MMC0_48 (1<<15) |
| 314 | #define S5PC100_CLKGATE_SCLK0_MMC1_48 (1<<16) |
| 315 | #define S5PC100_CLKGATE_SCLK0_MMC2_48 (1<<17) |
| 316 | |
| 317 | /* Special Clock Gate 1 Registers */ |
| 318 | #define S5PC100_CLKGATE_SCLK1_LCD (1<<0) |
| 319 | #define S5PC100_CLKGATE_SCLK1_FIMC0 (1<<1) |
| 320 | #define S5PC100_CLKGATE_SCLK1_FIMC1 (1<<2) |
| 321 | #define S5PC100_CLKGATE_SCLK1_FIMC2 (1<<3) |
| 322 | #define S5PC100_CLKGATE_SCLK1_TV54 (1<<4) |
| 323 | #define S5PC100_CLKGATE_SCLK1_VDAC54 (1<<5) |
| 324 | #define S5PC100_CLKGATE_SCLK1_MIXER (1<<6) |
| 325 | #define S5PC100_CLKGATE_SCLK1_HDMI (1<<7) |
| 326 | #define S5PC100_CLKGATE_SCLK1_AUDIO0 (1<<8) |
| 327 | #define S5PC100_CLKGATE_SCLK1_AUDIO1 (1<<9) |
| 328 | #define S5PC100_CLKGATE_SCLK1_AUDIO2 (1<<10) |
| 329 | #define S5PC100_CLKGATE_SCLK1_SPDIF (1<<11) |
| 330 | #define S5PC100_CLKGATE_SCLK1_CAM (1<<12) |
| 331 | |
| 332 | /* register for power management */ |
| 333 | #define S5PC100_PWR_CFG S5PC1XX_CLKREG(0x8000) |
| 334 | #define S5PC100_EINT_WAKEUP_MASK S5PC1XX_CLKREG(0x8004) |
| 335 | #define S5PC100_NORMAL_CFG S5PC1XX_CLKREG(0x8010) |
| 336 | #define S5PC100_STOP_CFG S5PC1XX_CLKREG(0x8014) |
| 337 | #define S5PC100_SLEEP_CFG S5PC1XX_CLKREG(0x8018) |
| 338 | #define S5PC100_STOP_MEM_CFG S5PC1XX_CLKREG(0x801C) |
| 339 | #define S5PC100_OSC_FREQ S5PC1XX_CLKREG(0x8100) |
| 340 | #define S5PC100_OSC_STABLE S5PC1XX_CLKREG(0x8104) |
| 341 | #define S5PC100_PWR_STABLE S5PC1XX_CLKREG(0x8108) |
| 342 | #define S5PC100_MTC_STABLE S5PC1XX_CLKREG(0x8110) |
| 343 | #define S5PC100_CLAMP_STABLE S5PC1XX_CLKREG(0x8114) |
| 344 | #define S5PC100_OTHERS S5PC1XX_CLKREG(0x8200) |
| 345 | #define S5PC100_RST_STAT S5PC1XX_CLKREG(0x8300) |
| 346 | #define S5PC100_WAKEUP_STAT S5PC1XX_CLKREG(0x8304) |
| 347 | #define S5PC100_BLK_PWR_STAT S5PC1XX_CLKREG(0x8308) |
| 348 | #define S5PC100_INFORM0 S5PC1XX_CLKREG(0x8400) |
| 349 | #define S5PC100_INFORM1 S5PC1XX_CLKREG(0x8404) |
| 350 | #define S5PC100_INFORM2 S5PC1XX_CLKREG(0x8408) |
| 351 | #define S5PC100_INFORM3 S5PC1XX_CLKREG(0x840C) |
| 352 | #define S5PC100_INFORM4 S5PC1XX_CLKREG(0x8410) |
| 353 | #define S5PC100_INFORM5 S5PC1XX_CLKREG(0x8414) |
| 354 | #define S5PC100_INFORM6 S5PC1XX_CLKREG(0x8418) |
| 355 | #define S5PC100_INFORM7 S5PC1XX_CLKREG(0x841C) |
| 356 | #define S5PC100_DCGIDX_MAP0 S5PC1XX_CLKREG(0x8500) |
| 357 | #define S5PC100_DCGIDX_MAP1 S5PC1XX_CLKREG(0x8504) |
| 358 | #define S5PC100_DCGIDX_MAP2 S5PC1XX_CLKREG(0x8508) |
| 359 | #define S5PC100_DCGPERF_MAP0 S5PC1XX_CLKREG(0x850C) |
| 360 | #define S5PC100_DCGPERF_MAP1 S5PC1XX_CLKREG(0x8510) |
| 361 | #define S5PC100_DVCIDX_MAP S5PC1XX_CLKREG(0x8514) |
| 362 | #define S5PC100_FREQ_CPU S5PC1XX_CLKREG(0x8518) |
| 363 | #define S5PC100_FREQ_DPM S5PC1XX_CLKREG(0x851C) |
| 364 | #define S5PC100_DVSEMCLK_EN S5PC1XX_CLKREG(0x8520) |
| 365 | #define S5PC100_APLL_CON_L8 S5PC1XX_CLKREG(0x8600) |
| 366 | #define S5PC100_APLL_CON_L7 S5PC1XX_CLKREG(0x8604) |
| 367 | #define S5PC100_APLL_CON_L6 S5PC1XX_CLKREG(0x8608) |
| 368 | #define S5PC100_APLL_CON_L5 S5PC1XX_CLKREG(0x860C) |
| 369 | #define S5PC100_APLL_CON_L4 S5PC1XX_CLKREG(0x8610) |
| 370 | #define S5PC100_APLL_CON_L3 S5PC1XX_CLKREG(0x8614) |
| 371 | #define S5PC100_APLL_CON_L2 S5PC1XX_CLKREG(0x8618) |
| 372 | #define S5PC100_APLL_CON_L1 S5PC1XX_CLKREG(0x861C) |
| 373 | #define S5PC100_IEM_CONTROL S5PC1XX_CLKREG(0x8620) |
| 374 | #define S5PC100_CLKDIV_IEM_L8 S5PC1XX_CLKREG(0x8700) |
| 375 | #define S5PC100_CLKDIV_IEM_L7 S5PC1XX_CLKREG(0x8704) |
| 376 | #define S5PC100_CLKDIV_IEM_L6 S5PC1XX_CLKREG(0x8708) |
| 377 | #define S5PC100_CLKDIV_IEM_L5 S5PC1XX_CLKREG(0x870C) |
| 378 | #define S5PC100_CLKDIV_IEM_L4 S5PC1XX_CLKREG(0x8710) |
| 379 | #define S5PC100_CLKDIV_IEM_L3 S5PC1XX_CLKREG(0x8714) |
| 380 | #define S5PC100_CLKDIV_IEM_L2 S5PC1XX_CLKREG(0x8718) |
| 381 | #define S5PC100_CLKDIV_IEM_L1 S5PC1XX_CLKREG(0x871C) |
| 382 | #define S5PC100_IEM_HPMCLK_DIV S5PC1XX_CLKREG(0x8724) |
| 383 | |
| 384 | #define S5PC100_SWRESET S5PC1XX_CLKREG(0x100000) |
| 385 | #define S5PC100_OND_SWRESET S5PC1XX_CLKREG(0x100008) |
| 386 | #define S5PC100_GEN_CTRL S5PC1XX_CLKREG(0x100100) |
| 387 | #define S5PC100_GEN_STATUS S5PC1XX_CLKREG(0x100104) |
| 388 | #define S5PC100_MEM_SYS_CFG S5PC1XX_CLKREG(0x100200) |
| 389 | #define S5PC100_CAM_MUX_SEL S5PC1XX_CLKREG(0x100300) |
| 390 | #define S5PC100_MIXER_OUT_SEL S5PC1XX_CLKREG(0x100304) |
| 391 | #define S5PC100_LPMP_MODE_SEL S5PC1XX_CLKREG(0x100308) |
| 392 | #define S5PC100_MIPI_PHY_CON0 S5PC1XX_CLKREG(0x100400) |
| 393 | #define S5PC100_MIPI_PHY_CON1 S5PC1XX_CLKREG(0x100414) |
| 394 | #define S5PC100_HDMI_PHY_CON0 S5PC1XX_CLKREG(0x100420) |
| 395 | |
| 396 | #define S5PC100_CFG_WFI_CLEAN (~(3<<5)) |
| 397 | #define S5PC100_CFG_WFI_IDLE (1<<5) |
| 398 | #define S5PC100_CFG_WFI_STOP (2<<5) |
| 399 | #define S5PC100_CFG_WFI_SLEEP (3<<5) |
| 400 | |
| 401 | #define S5PC100_OTHER_SYS_INT 24 |
| 402 | #define S5PC100_OTHER_STA_TYPE 23 |
| 403 | #define STA_TYPE_EXPON 0 |
| 404 | #define STA_TYPE_SFR 1 |
| 405 | |
| 406 | #define S5PC100_PWR_STA_EXP_SCALE 0 |
| 407 | #define S5PC100_PWR_STA_CNT 4 |
| 408 | |
| 409 | #define S5PC100_PWR_STABLE_COUNT 85500 |
| 410 | |
| 411 | #define S5PC100_SLEEP_CFG_OSC_EN 0 |
| 412 | |
| 413 | /* OTHERS Resgister */ |
| 414 | #define S5PC100_OTHERS_USB_SIG_MASK (1 << 16) |
| 415 | #define S5PC100_OTHERS_MIPI_DPHY_EN (1 << 28) |
| 416 | |
| 417 | /* MIPI D-PHY Control Register 0 */ |
| 418 | #define S5PC100_MIPI_PHY_CON0_M_RESETN (1 << 1) |
| 419 | #define S5PC100_MIPI_PHY_CON0_S_RESETN (1 << 0) |
| 420 | |
| 421 | #endif /* _PLAT_REGS_CLOCK_H */ |