Mike Frysinger | bc8c84c | 2007-08-05 17:32:25 +0800 | [diff] [blame] | 1 | /* |
| 2 | * File: include/asm-blackfin/mach-bf527/anomaly.h |
| 3 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ |
| 4 | * |
Mike Frysinger | c18e99c | 2009-03-04 17:36:49 +0800 | [diff] [blame] | 5 | * Copyright (C) 2004-2009 Analog Devices Inc. |
Mike Frysinger | bc8c84c | 2007-08-05 17:32:25 +0800 | [diff] [blame] | 6 | * Licensed under the GPL-2 or later. |
| 7 | */ |
| 8 | |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 9 | /* This file should be up to date with: |
| 10 | * - Revision C, 03/13/2009; ADSP-BF526 Blackfin Processor Anomaly List |
| 11 | * - Revision F, 03/03/2009; ADSP-BF527 Blackfin Processor Anomaly List |
Mike Frysinger | bc8c84c | 2007-08-05 17:32:25 +0800 | [diff] [blame] | 12 | */ |
| 13 | |
| 14 | #ifndef _MACH_ANOMALY_H_ |
| 15 | #define _MACH_ANOMALY_H_ |
| 16 | |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 17 | /* We do not support old silicon - sorry */ |
| 18 | #if __SILICON_REVISION__ < 0 |
| 19 | # error will not work on BF526/BF527 silicon version |
| 20 | #endif |
| 21 | |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 22 | #if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__) |
| 23 | # define ANOMALY_BF526 1 |
| 24 | #else |
| 25 | # define ANOMALY_BF526 0 |
| 26 | #endif |
| 27 | #if defined(__ADSPBF523__) || defined(__ADSPBF525__) || defined(__ADSPBF527__) |
| 28 | # define ANOMALY_BF527 1 |
| 29 | #else |
| 30 | # define ANOMALY_BF527 0 |
| 31 | #endif |
| 32 | |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 33 | #define _ANOMALY_BF526(rev526) (ANOMALY_BF526 && __SILICON_REVISION__ rev526) |
| 34 | #define _ANOMALY_BF527(rev527) (ANOMALY_BF527 && __SILICON_REVISION__ rev527) |
| 35 | #define _ANOMALY_BF526_BF527(rev526, rev527) (_ANOMALY_BF526(rev526) || _ANOMALY_BF527(rev527)) |
| 36 | |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 37 | /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ |
Mike Frysinger | bc8c84c | 2007-08-05 17:32:25 +0800 | [diff] [blame] | 38 | #define ANOMALY_05000074 (1) |
Mike Frysinger | a70ce07 | 2008-05-31 15:47:17 +0800 | [diff] [blame] | 39 | /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ |
Mike Frysinger | 3529e041 | 2008-10-28 16:22:41 +0800 | [diff] [blame] | 40 | #define ANOMALY_05000119 (1) /* note: brokenness is noted in documentation, not anomaly sheet */ |
Mike Frysinger | bc8c84c | 2007-08-05 17:32:25 +0800 | [diff] [blame] | 41 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ |
| 42 | #define ANOMALY_05000122 (1) |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 43 | /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ |
Mike Frysinger | bc8c84c | 2007-08-05 17:32:25 +0800 | [diff] [blame] | 44 | #define ANOMALY_05000245 (1) |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 45 | /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ |
| 46 | #define ANOMALY_05000254 (1) |
Mike Frysinger | bc8c84c | 2007-08-05 17:32:25 +0800 | [diff] [blame] | 47 | /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ |
| 48 | #define ANOMALY_05000265 (1) |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 49 | /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ |
| 50 | #define ANOMALY_05000310 (1) |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 51 | /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 52 | #define ANOMALY_05000313 (_ANOMALY_BF526_BF527(< 1, < 2)) |
Mike Frysinger | bc8c84c | 2007-08-05 17:32:25 +0800 | [diff] [blame] | 53 | /* Incorrect Access of OTP_STATUS During otp_write() Function */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 54 | #define ANOMALY_05000328 (_ANOMALY_BF527(< 2)) |
| 55 | /* Host DMA Boot Modes Are Not Functional */ |
| 56 | #define ANOMALY_05000330 (__SILICON_REVISION__ < 2) |
Mike Frysinger | bc8c84c | 2007-08-05 17:32:25 +0800 | [diff] [blame] | 57 | /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 58 | #define ANOMALY_05000337 (_ANOMALY_BF527(< 2)) |
Sonic Zhang | 4d55563 | 2008-04-25 03:28:10 +0800 | [diff] [blame] | 59 | /* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 60 | #define ANOMALY_05000341 (_ANOMALY_BF527(< 2)) |
Sonic Zhang | 4d55563 | 2008-04-25 03:28:10 +0800 | [diff] [blame] | 61 | /* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 62 | #define ANOMALY_05000342 (_ANOMALY_BF527(< 2)) |
Sonic Zhang | 4d55563 | 2008-04-25 03:28:10 +0800 | [diff] [blame] | 63 | /* USB Calibration Value Is Not Initialized */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 64 | #define ANOMALY_05000346 (_ANOMALY_BF526_BF527(< 1, < 2)) |
Robin Getz | 202d7bd | 2008-10-09 11:59:46 +0800 | [diff] [blame] | 65 | /* USB Calibration Value to use */ |
| 66 | #define ANOMALY_05000346_value 0xE510 |
Sonic Zhang | 4d55563 | 2008-04-25 03:28:10 +0800 | [diff] [blame] | 67 | /* Preboot Routine Incorrectly Alters Reset Value of USB Register */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 68 | #define ANOMALY_05000347 (_ANOMALY_BF527(< 2)) |
Sonic Zhang | 4d55563 | 2008-04-25 03:28:10 +0800 | [diff] [blame] | 69 | /* Security Features Are Not Functional */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 70 | #define ANOMALY_05000348 (_ANOMALY_BF527(< 1)) |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 71 | /* bfrom_SysControl() Firmware Function Performs Improper System Reset */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 72 | #define ANOMALY_05000353 (_ANOMALY_BF526(< 1)) |
Sonic Zhang | 4d55563 | 2008-04-25 03:28:10 +0800 | [diff] [blame] | 73 | /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 74 | #define ANOMALY_05000355 (_ANOMALY_BF527(< 2)) |
Sonic Zhang | 4d55563 | 2008-04-25 03:28:10 +0800 | [diff] [blame] | 75 | /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 76 | #define ANOMALY_05000357 (_ANOMALY_BF527(< 2)) |
Sonic Zhang | 4d55563 | 2008-04-25 03:28:10 +0800 | [diff] [blame] | 77 | /* Incorrect Revision Number in DSPID Register */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 78 | #define ANOMALY_05000364 (_ANOMALY_BF527(== 1)) |
Sonic Zhang | 4d55563 | 2008-04-25 03:28:10 +0800 | [diff] [blame] | 79 | /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ |
| 80 | #define ANOMALY_05000366 (1) |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 81 | /* Incorrect Default CSEL Value in PLL_DIV */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 82 | #define ANOMALY_05000368 (_ANOMALY_BF527(< 2)) |
Sonic Zhang | 4d55563 | 2008-04-25 03:28:10 +0800 | [diff] [blame] | 83 | /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 84 | #define ANOMALY_05000371 (_ANOMALY_BF527(< 2)) |
Sonic Zhang | 4d55563 | 2008-04-25 03:28:10 +0800 | [diff] [blame] | 85 | /* Authentication Fails To Initiate */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 86 | #define ANOMALY_05000376 (_ANOMALY_BF527(< 2)) |
Sonic Zhang | 4d55563 | 2008-04-25 03:28:10 +0800 | [diff] [blame] | 87 | /* Data Read From L3 Memory by USB DMA May be Corrupted */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 88 | #define ANOMALY_05000380 (_ANOMALY_BF527(< 2)) |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 89 | /* 8-Bit NAND Flash Boot Mode Not Functional */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 90 | #define ANOMALY_05000382 (_ANOMALY_BF526_BF527(< 1, < 2)) |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 91 | /* Boot from OTP Memory Not Functional */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 92 | #define ANOMALY_05000385 (_ANOMALY_BF527(< 2)) |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 93 | /* bfrom_SysControl() Firmware Routine Not Functional */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 94 | #define ANOMALY_05000386 (_ANOMALY_BF527(< 2)) |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 95 | /* Programmable Preboot Settings Not Functional */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 96 | #define ANOMALY_05000387 (_ANOMALY_BF527(< 2)) |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 97 | /* CRC32 Checksum Support Not Functional */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 98 | #define ANOMALY_05000388 (_ANOMALY_BF526_BF527(< 1, < 2)) |
Sonic Zhang | 4d55563 | 2008-04-25 03:28:10 +0800 | [diff] [blame] | 99 | /* Reset Vector Must Not Be in SDRAM Memory Space */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 100 | #define ANOMALY_05000389 (_ANOMALY_BF527(< 2)) |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 101 | /* pTempCurrent Not Present in ADI_BOOT_DATA Structure */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 102 | #define ANOMALY_05000392 (_ANOMALY_BF527(< 2)) |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 103 | /* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 104 | #define ANOMALY_05000393 (_ANOMALY_BF527(< 2)) |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 105 | /* Log Buffer Not Functional */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 106 | #define ANOMALY_05000394 (_ANOMALY_BF527(< 2)) |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 107 | /* Hook Routine Not Functional */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 108 | #define ANOMALY_05000395 (_ANOMALY_BF527(< 2)) |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 109 | /* Header Indirect Bit Not Functional */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 110 | #define ANOMALY_05000396 (_ANOMALY_BF527(< 2)) |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 111 | /* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 112 | #define ANOMALY_05000397 (_ANOMALY_BF527(< 2)) |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 113 | /* SWRESET, DFRESET and WDRESET Bits in the SYSCR Register Not Functional */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 114 | #define ANOMALY_05000398 (_ANOMALY_BF527(< 2)) |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 115 | /* BCODE_NOBOOT in BCODE Field of SYSCR Register Not Functional */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 116 | #define ANOMALY_05000399 (_ANOMALY_BF527(< 2)) |
Sonic Zhang | 4d55563 | 2008-04-25 03:28:10 +0800 | [diff] [blame] | 117 | /* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 118 | #define ANOMALY_05000401 (_ANOMALY_BF526_BF527(< 1, < 2)) |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 119 | /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 120 | #define ANOMALY_05000403 (_ANOMALY_BF526_BF527(< 1, < 2)) |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 121 | /* Lockbox SESR Disallows Certain User Interrupts */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 122 | #define ANOMALY_05000404 (_ANOMALY_BF526_BF527(< 1, < 2)) |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 123 | /* Lockbox SESR Firmware Does Not Save/Restore Full Context */ |
| 124 | #define ANOMALY_05000405 (1) |
| 125 | /* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 126 | #define ANOMALY_05000407 (_ANOMALY_BF526_BF527(< 1, < 2)) |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 127 | /* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */ |
| 128 | #define ANOMALY_05000408 (1) |
| 129 | /* Lockbox firmware leaves MDMA0 channel enabled */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 130 | #define ANOMALY_05000409 (_ANOMALY_BF526_BF527(< 1, < 2)) |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 131 | /* Incorrect Default Internal Voltage Regulator Setting */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 132 | #define ANOMALY_05000410 (_ANOMALY_BF527(< 2)) |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 133 | /* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 134 | #define ANOMALY_05000411 (_ANOMALY_BF526_BF527(< 1, < 2)) |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 135 | /* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 136 | #define ANOMALY_05000414 (_ANOMALY_BF526_BF527(< 1, < 2)) |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 137 | /* DEB2_URGENT Bit Not Functional */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 138 | #define ANOMALY_05000415 (_ANOMALY_BF526_BF527(< 1, < 2)) |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 139 | /* Speculative Fetches Can Cause Undesired External FIFO Operations */ |
| 140 | #define ANOMALY_05000416 (1) |
| 141 | /* SPORT0 Ignores External TSCLK0 on PG14 When TMR6 is an Output */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 142 | #define ANOMALY_05000417 (_ANOMALY_BF527(< 2)) |
| 143 | /* PPI Timing Requirements tSFSPE and tHFSPE Do Not Meet Data Sheet Specifications */ |
| 144 | #define ANOMALY_05000418 (_ANOMALY_BF526_BF527(< 1, < 2)) |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 145 | /* USB PLL_STABLE Bit May Not Accurately Reflect the USB PLL's Status */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 146 | #define ANOMALY_05000420 (_ANOMALY_BF526_BF527(< 1, < 2)) |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 147 | /* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */ |
| 148 | #define ANOMALY_05000421 (1) |
| 149 | /* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 150 | #define ANOMALY_05000422 (_ANOMALY_BF526_BF527(> 0, > 1)) |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 151 | /* Certain Ethernet Frames With Errors are Misclassified in RMII Mode */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 152 | #define ANOMALY_05000423 (_ANOMALY_BF526_BF527(< 1, < 2)) |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 153 | /* Internal Voltage Regulator Not Trimmed */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 154 | #define ANOMALY_05000424 (_ANOMALY_BF527(< 2)) |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 155 | /* Multichannel SPORT Channel Misalignment Under Specific Configuration */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 156 | #define ANOMALY_05000425 (_ANOMALY_BF526_BF527(< 1, < 2)) |
| 157 | /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 158 | #define ANOMALY_05000426 (1) |
| 159 | /* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 160 | #define ANOMALY_05000429 (_ANOMALY_BF526_BF527(< 1, < 2)) |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 161 | /* Software System Reset Corrupts PLL_LOCKCNT Register */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 162 | #define ANOMALY_05000430 (_ANOMALY_BF527(> 1)) |
| 163 | /* Incorrect Use of Stack in Lockbox Firmware During Authentication */ |
| 164 | #define ANOMALY_05000431 (1) |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 165 | /* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 166 | #define ANOMALY_05000432 (_ANOMALY_BF526(< 1)) |
Mike Frysinger | 94b2821 | 2008-11-18 17:48:21 +0800 | [diff] [blame] | 167 | /* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 168 | #define ANOMALY_05000435 (_ANOMALY_BF526_BF527(< 1, >= 0)) |
| 169 | /* Preboot Cannot be Used to Alter the PLL_DIV Register */ |
| 170 | #define ANOMALY_05000439 (_ANOMALY_BF526_BF527(< 1, >= 0)) |
| 171 | /* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */ |
| 172 | #define ANOMALY_05000440 (_ANOMALY_BF526_BF527(< 1, >= 0)) |
| 173 | /* OTP Write Accesses Not Supported */ |
| 174 | #define ANOMALY_05000442 (_ANOMALY_BF527(< 1)) |
Mike Frysinger | 3529e041 | 2008-10-28 16:22:41 +0800 | [diff] [blame] | 175 | /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ |
| 176 | #define ANOMALY_05000443 (1) |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 177 | /* The WURESET Bit in the SYSCR Register is not Functional */ |
| 178 | #define ANOMALY_05000445 (1) |
Graf Yang | 976119b | 2009-07-01 07:05:40 +0000 | [diff] [blame] | 179 | /* USB DMA Short Packet Data Corruption */ |
| 180 | #define ANOMALY_05000450 (1) |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 181 | /* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */ |
| 182 | #define ANOMALY_05000451 (1) |
| 183 | /* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */ |
| 184 | #define ANOMALY_05000452 (_ANOMALY_BF526_BF527(< 1, >= 0)) |
| 185 | /* USB Receive Interrupt Is Not Generated in DMA Mode 1 */ |
| 186 | #define ANOMALY_05000456 (1) |
| 187 | /* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */ |
| 188 | #define ANOMALY_05000457 (1) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 189 | /* False Hardware Error when RETI Points to Invalid Memory */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 190 | #define ANOMALY_05000461 (1) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 191 | /* USB Rx DMA hang */ |
| 192 | #define ANOMALY_05000465 (1) |
| 193 | /* Possible RX data corruption when control & data EP FIFOs are accessed via the core */ |
| 194 | #define ANOMALY_05000467 (1) |
Mike Frysinger | bc8c84c | 2007-08-05 17:32:25 +0800 | [diff] [blame] | 195 | |
Michael Hennerich | 2b39331 | 2007-10-10 16:58:49 +0800 | [diff] [blame] | 196 | /* Anomalies that don't exist on this proc */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 197 | #define ANOMALY_05000099 (0) |
| 198 | #define ANOMALY_05000120 (0) |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 199 | #define ANOMALY_05000125 (0) |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 200 | #define ANOMALY_05000149 (0) |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 201 | #define ANOMALY_05000158 (0) |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 202 | #define ANOMALY_05000171 (0) |
| 203 | #define ANOMALY_05000179 (0) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 204 | #define ANOMALY_05000182 (0) |
Sonic Zhang | 4d55563 | 2008-04-25 03:28:10 +0800 | [diff] [blame] | 205 | #define ANOMALY_05000183 (0) |
Graf Yang | 976119b | 2009-07-01 07:05:40 +0000 | [diff] [blame] | 206 | #define ANOMALY_05000189 (0) |
Sonic Zhang | 4d55563 | 2008-04-25 03:28:10 +0800 | [diff] [blame] | 207 | #define ANOMALY_05000198 (0) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 208 | #define ANOMALY_05000202 (0) |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 209 | #define ANOMALY_05000215 (0) |
| 210 | #define ANOMALY_05000220 (0) |
| 211 | #define ANOMALY_05000227 (0) |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 212 | #define ANOMALY_05000230 (0) |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 213 | #define ANOMALY_05000231 (0) |
| 214 | #define ANOMALY_05000233 (0) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 215 | #define ANOMALY_05000234 (0) |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 216 | #define ANOMALY_05000242 (0) |
Sonic Zhang | 4d55563 | 2008-04-25 03:28:10 +0800 | [diff] [blame] | 217 | #define ANOMALY_05000244 (0) |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 218 | #define ANOMALY_05000248 (0) |
| 219 | #define ANOMALY_05000250 (0) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 220 | #define ANOMALY_05000257 (0) |
Sonic Zhang | 4d55563 | 2008-04-25 03:28:10 +0800 | [diff] [blame] | 221 | #define ANOMALY_05000261 (0) |
| 222 | #define ANOMALY_05000263 (0) |
| 223 | #define ANOMALY_05000266 (0) |
| 224 | #define ANOMALY_05000273 (0) |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 225 | #define ANOMALY_05000274 (0) |
Mike Frysinger | ee554be | 2009-03-03 16:52:55 +0800 | [diff] [blame] | 226 | #define ANOMALY_05000278 (0) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 227 | #define ANOMALY_05000281 (0) |
| 228 | #define ANOMALY_05000283 (0) |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 229 | #define ANOMALY_05000285 (0) |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 230 | #define ANOMALY_05000287 (0) |
| 231 | #define ANOMALY_05000301 (0) |
Mike Frysinger | c18e99c | 2009-03-04 17:36:49 +0800 | [diff] [blame] | 232 | #define ANOMALY_05000305 (0) |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 233 | #define ANOMALY_05000307 (0) |
Sonic Zhang | 4d55563 | 2008-04-25 03:28:10 +0800 | [diff] [blame] | 234 | #define ANOMALY_05000311 (0) |
Mike Frysinger | 3529e041 | 2008-10-28 16:22:41 +0800 | [diff] [blame] | 235 | #define ANOMALY_05000312 (0) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 236 | #define ANOMALY_05000315 (0) |
Sonic Zhang | 4d55563 | 2008-04-25 03:28:10 +0800 | [diff] [blame] | 237 | #define ANOMALY_05000323 (0) |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 238 | #define ANOMALY_05000362 (1) |
Sonic Zhang | 4d55563 | 2008-04-25 03:28:10 +0800 | [diff] [blame] | 239 | #define ANOMALY_05000363 (0) |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 240 | #define ANOMALY_05000400 (0) |
Mike Frysinger | 6651ece | 2009-01-07 23:14:38 +0800 | [diff] [blame] | 241 | #define ANOMALY_05000412 (0) |
Mike Frysinger | 7dbc3f6 | 2009-03-06 00:20:49 +0800 | [diff] [blame] | 242 | #define ANOMALY_05000447 (0) |
| 243 | #define ANOMALY_05000448 (0) |
Sonic Zhang | 4d55563 | 2008-04-25 03:28:10 +0800 | [diff] [blame] | 244 | |
Mike Frysinger | bc8c84c | 2007-08-05 17:32:25 +0800 | [diff] [blame] | 245 | #endif |