Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1 | /* |
Dhananjay Phadke | 5d242f1 | 2009-02-25 15:57:56 +0000 | [diff] [blame] | 2 | * Copyright (C) 2003 - 2009 NetXen, Inc. |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 3 | * All rights reserved. |
Amit S. Kale | 80922fb | 2006-12-04 09:18:00 -0800 | [diff] [blame] | 4 | * |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 5 | * This program is free software; you can redistribute it and/or |
| 6 | * modify it under the terms of the GNU General Public License |
| 7 | * as published by the Free Software Foundation; either version 2 |
| 8 | * of the License, or (at your option) any later version. |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 9 | * |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 10 | * This program is distributed in the hope that it will be useful, but |
| 11 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 14 | * |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, |
| 18 | * MA 02111-1307, USA. |
Amit S. Kale | 80922fb | 2006-12-04 09:18:00 -0800 | [diff] [blame] | 19 | * |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 20 | * The full GNU General Public License is included in this distribution |
| 21 | * in the file called LICENSE. |
Amit S. Kale | 80922fb | 2006-12-04 09:18:00 -0800 | [diff] [blame] | 22 | * |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 23 | * Contact Information: |
| 24 | * info@netxen.com |
Dhananjay Phadke | 5d242f1 | 2009-02-25 15:57:56 +0000 | [diff] [blame] | 25 | * NetXen Inc, |
| 26 | * 18922 Forge Drive |
| 27 | * Cupertino, CA 95014-0701 |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 28 | * |
| 29 | */ |
| 30 | |
| 31 | #include "netxen_nic.h" |
| 32 | #include "netxen_nic_hw.h" |
| 33 | #include "netxen_nic_phan_reg.h" |
| 34 | |
Arnaldo Carvalho de Melo | c9bdd4b | 2007-03-12 20:09:15 -0300 | [diff] [blame] | 35 | #include <net/ip.h> |
| 36 | |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 37 | #define MASK(n) ((1ULL<<(n))-1) |
| 38 | #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff)) |
| 39 | #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff)) |
| 40 | #define MS_WIN(addr) (addr & 0x0ffc0000) |
| 41 | |
| 42 | #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) |
| 43 | |
| 44 | #define CRB_BLK(off) ((off >> 20) & 0x3f) |
| 45 | #define CRB_SUBBLK(off) ((off >> 16) & 0xf) |
| 46 | #define CRB_WINDOW_2M (0x130060) |
| 47 | #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000)) |
| 48 | #define CRB_INDIRECT_2M (0x1e0000UL) |
| 49 | |
Dhananjay Phadke | e98e335 | 2009-04-07 22:50:38 +0000 | [diff] [blame] | 50 | #ifndef readq |
| 51 | static inline u64 readq(void __iomem *addr) |
| 52 | { |
| 53 | return readl(addr) | (((u64) readl(addr + 4)) << 32LL); |
| 54 | } |
| 55 | #endif |
| 56 | |
| 57 | #ifndef writeq |
| 58 | static inline void writeq(u64 val, void __iomem *addr) |
| 59 | { |
| 60 | writel(((u32) (val)), (addr)); |
| 61 | writel(((u32) (val >> 32)), (addr + 4)); |
| 62 | } |
| 63 | #endif |
| 64 | |
Dhananjay Phadke | 1fbe632 | 2009-04-07 22:50:44 +0000 | [diff] [blame] | 65 | #define ADDR_IN_RANGE(addr, low, high) \ |
| 66 | (((addr) < (high)) && ((addr) >= (low))) |
| 67 | |
| 68 | #define PCI_OFFSET_FIRST_RANGE(adapter, off) \ |
| 69 | ((adapter)->ahw.pci_base0 + (off)) |
| 70 | #define PCI_OFFSET_SECOND_RANGE(adapter, off) \ |
| 71 | ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START) |
| 72 | #define PCI_OFFSET_THIRD_RANGE(adapter, off) \ |
| 73 | ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START) |
| 74 | |
| 75 | static void __iomem *pci_base_offset(struct netxen_adapter *adapter, |
| 76 | unsigned long off) |
| 77 | { |
| 78 | if (ADDR_IN_RANGE(off, FIRST_PAGE_GROUP_START, FIRST_PAGE_GROUP_END)) |
| 79 | return PCI_OFFSET_FIRST_RANGE(adapter, off); |
| 80 | |
| 81 | if (ADDR_IN_RANGE(off, SECOND_PAGE_GROUP_START, SECOND_PAGE_GROUP_END)) |
| 82 | return PCI_OFFSET_SECOND_RANGE(adapter, off); |
| 83 | |
| 84 | if (ADDR_IN_RANGE(off, THIRD_PAGE_GROUP_START, THIRD_PAGE_GROUP_END)) |
| 85 | return PCI_OFFSET_THIRD_RANGE(adapter, off); |
| 86 | |
| 87 | return NULL; |
| 88 | } |
| 89 | |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 90 | #define CRB_WIN_LOCK_TIMEOUT 100000000 |
Dhananjay Phadke | ea7eaa3 | 2009-04-07 22:50:48 +0000 | [diff] [blame] | 91 | static crb_128M_2M_block_map_t |
| 92 | crb_128M_2M_map[64] __cacheline_aligned_in_smp = { |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 93 | {{{0, 0, 0, 0} } }, /* 0: PCI */ |
| 94 | {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */ |
| 95 | {1, 0x0110000, 0x0120000, 0x130000}, |
| 96 | {1, 0x0120000, 0x0122000, 0x124000}, |
| 97 | {1, 0x0130000, 0x0132000, 0x126000}, |
| 98 | {1, 0x0140000, 0x0142000, 0x128000}, |
| 99 | {1, 0x0150000, 0x0152000, 0x12a000}, |
| 100 | {1, 0x0160000, 0x0170000, 0x110000}, |
| 101 | {1, 0x0170000, 0x0172000, 0x12e000}, |
| 102 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 103 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 104 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 105 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 106 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 107 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 108 | {1, 0x01e0000, 0x01e0800, 0x122000}, |
| 109 | {0, 0x0000000, 0x0000000, 0x000000} } }, |
| 110 | {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */ |
| 111 | {{{0, 0, 0, 0} } }, /* 3: */ |
| 112 | {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */ |
| 113 | {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */ |
| 114 | {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */ |
| 115 | {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */ |
| 116 | {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */ |
| 117 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 118 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 119 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 120 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 121 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 122 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 123 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 124 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 125 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 126 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 127 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 128 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 129 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 130 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 131 | {1, 0x08f0000, 0x08f2000, 0x172000} } }, |
| 132 | {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/ |
| 133 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 134 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 135 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 136 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 137 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 138 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 139 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 140 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 141 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 142 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 143 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 144 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 145 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 146 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 147 | {1, 0x09f0000, 0x09f2000, 0x176000} } }, |
| 148 | {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/ |
| 149 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 150 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 151 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 152 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 153 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 154 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 155 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 156 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 157 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 158 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 159 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 160 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 161 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 162 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 163 | {1, 0x0af0000, 0x0af2000, 0x17a000} } }, |
| 164 | {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/ |
| 165 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 166 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 167 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 168 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 169 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 170 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 171 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 172 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 173 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 174 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 175 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 176 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 177 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 178 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 179 | {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, |
| 180 | {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */ |
| 181 | {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */ |
| 182 | {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */ |
| 183 | {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */ |
| 184 | {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */ |
| 185 | {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */ |
| 186 | {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */ |
| 187 | {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */ |
| 188 | {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */ |
| 189 | {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */ |
| 190 | {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */ |
| 191 | {{{0, 0, 0, 0} } }, /* 23: */ |
| 192 | {{{0, 0, 0, 0} } }, /* 24: */ |
| 193 | {{{0, 0, 0, 0} } }, /* 25: */ |
| 194 | {{{0, 0, 0, 0} } }, /* 26: */ |
| 195 | {{{0, 0, 0, 0} } }, /* 27: */ |
| 196 | {{{0, 0, 0, 0} } }, /* 28: */ |
| 197 | {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */ |
| 198 | {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */ |
| 199 | {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */ |
| 200 | {{{0} } }, /* 32: PCI */ |
| 201 | {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */ |
| 202 | {1, 0x2110000, 0x2120000, 0x130000}, |
| 203 | {1, 0x2120000, 0x2122000, 0x124000}, |
| 204 | {1, 0x2130000, 0x2132000, 0x126000}, |
| 205 | {1, 0x2140000, 0x2142000, 0x128000}, |
| 206 | {1, 0x2150000, 0x2152000, 0x12a000}, |
| 207 | {1, 0x2160000, 0x2170000, 0x110000}, |
| 208 | {1, 0x2170000, 0x2172000, 0x12e000}, |
| 209 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 210 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 211 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 212 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 213 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 214 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 215 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 216 | {0, 0x0000000, 0x0000000, 0x000000} } }, |
| 217 | {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */ |
| 218 | {{{0} } }, /* 35: */ |
| 219 | {{{0} } }, /* 36: */ |
| 220 | {{{0} } }, /* 37: */ |
| 221 | {{{0} } }, /* 38: */ |
| 222 | {{{0} } }, /* 39: */ |
| 223 | {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */ |
| 224 | {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */ |
| 225 | {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */ |
| 226 | {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */ |
| 227 | {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */ |
| 228 | {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */ |
| 229 | {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */ |
| 230 | {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */ |
| 231 | {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */ |
| 232 | {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */ |
| 233 | {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */ |
| 234 | {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */ |
| 235 | {{{0} } }, /* 52: */ |
| 236 | {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */ |
| 237 | {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */ |
| 238 | {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */ |
| 239 | {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */ |
| 240 | {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */ |
| 241 | {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */ |
| 242 | {{{0} } }, /* 59: I2C0 */ |
| 243 | {{{0} } }, /* 60: I2C1 */ |
| 244 | {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */ |
| 245 | {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */ |
| 246 | {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */ |
| 247 | }; |
| 248 | |
| 249 | /* |
| 250 | * top 12 bits of crb internal address (hub, agent) |
| 251 | */ |
| 252 | static unsigned crb_hub_agt[64] = |
| 253 | { |
| 254 | 0, |
| 255 | NETXEN_HW_CRB_HUB_AGT_ADR_PS, |
| 256 | NETXEN_HW_CRB_HUB_AGT_ADR_MN, |
| 257 | NETXEN_HW_CRB_HUB_AGT_ADR_MS, |
| 258 | 0, |
| 259 | NETXEN_HW_CRB_HUB_AGT_ADR_SRE, |
| 260 | NETXEN_HW_CRB_HUB_AGT_ADR_NIU, |
| 261 | NETXEN_HW_CRB_HUB_AGT_ADR_QMN, |
| 262 | NETXEN_HW_CRB_HUB_AGT_ADR_SQN0, |
| 263 | NETXEN_HW_CRB_HUB_AGT_ADR_SQN1, |
| 264 | NETXEN_HW_CRB_HUB_AGT_ADR_SQN2, |
| 265 | NETXEN_HW_CRB_HUB_AGT_ADR_SQN3, |
| 266 | NETXEN_HW_CRB_HUB_AGT_ADR_I2Q, |
| 267 | NETXEN_HW_CRB_HUB_AGT_ADR_TIMR, |
| 268 | NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB, |
| 269 | NETXEN_HW_CRB_HUB_AGT_ADR_PGN4, |
| 270 | NETXEN_HW_CRB_HUB_AGT_ADR_XDMA, |
| 271 | NETXEN_HW_CRB_HUB_AGT_ADR_PGN0, |
| 272 | NETXEN_HW_CRB_HUB_AGT_ADR_PGN1, |
| 273 | NETXEN_HW_CRB_HUB_AGT_ADR_PGN2, |
| 274 | NETXEN_HW_CRB_HUB_AGT_ADR_PGN3, |
| 275 | NETXEN_HW_CRB_HUB_AGT_ADR_PGND, |
| 276 | NETXEN_HW_CRB_HUB_AGT_ADR_PGNI, |
| 277 | NETXEN_HW_CRB_HUB_AGT_ADR_PGS0, |
| 278 | NETXEN_HW_CRB_HUB_AGT_ADR_PGS1, |
| 279 | NETXEN_HW_CRB_HUB_AGT_ADR_PGS2, |
| 280 | NETXEN_HW_CRB_HUB_AGT_ADR_PGS3, |
| 281 | 0, |
| 282 | NETXEN_HW_CRB_HUB_AGT_ADR_PGSI, |
| 283 | NETXEN_HW_CRB_HUB_AGT_ADR_SN, |
| 284 | 0, |
| 285 | NETXEN_HW_CRB_HUB_AGT_ADR_EG, |
| 286 | 0, |
| 287 | NETXEN_HW_CRB_HUB_AGT_ADR_PS, |
| 288 | NETXEN_HW_CRB_HUB_AGT_ADR_CAM, |
| 289 | 0, |
| 290 | 0, |
| 291 | 0, |
| 292 | 0, |
| 293 | 0, |
| 294 | NETXEN_HW_CRB_HUB_AGT_ADR_TIMR, |
| 295 | 0, |
| 296 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1, |
| 297 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2, |
| 298 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3, |
| 299 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4, |
| 300 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5, |
| 301 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6, |
| 302 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7, |
| 303 | NETXEN_HW_CRB_HUB_AGT_ADR_XDMA, |
| 304 | NETXEN_HW_CRB_HUB_AGT_ADR_I2Q, |
| 305 | NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB, |
| 306 | 0, |
| 307 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0, |
| 308 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8, |
| 309 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9, |
| 310 | NETXEN_HW_CRB_HUB_AGT_ADR_OCM0, |
| 311 | 0, |
| 312 | NETXEN_HW_CRB_HUB_AGT_ADR_SMB, |
| 313 | NETXEN_HW_CRB_HUB_AGT_ADR_I2C0, |
| 314 | NETXEN_HW_CRB_HUB_AGT_ADR_I2C1, |
| 315 | 0, |
| 316 | NETXEN_HW_CRB_HUB_AGT_ADR_PGNC, |
| 317 | 0, |
| 318 | }; |
| 319 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 320 | /* PCI Windowing for DDR regions. */ |
| 321 | |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 322 | #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */ |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 323 | |
Dhananjay Phadke | 623621b | 2008-07-21 19:44:01 -0700 | [diff] [blame] | 324 | #define NETXEN_UNICAST_ADDR(port, index) \ |
| 325 | (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8)) |
| 326 | #define NETXEN_MCAST_ADDR(port, index) \ |
| 327 | (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8)) |
| 328 | #define MAC_HI(addr) \ |
| 329 | ((addr[2] << 16) | (addr[1] << 8) | (addr[0])) |
| 330 | #define MAC_LO(addr) \ |
| 331 | ((addr[5] << 16) | (addr[4] << 8) | (addr[3])) |
| 332 | |
| 333 | static int |
| 334 | netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter) |
| 335 | { |
| 336 | u32 val = 0; |
| 337 | u16 port = adapter->physical_port; |
| 338 | u8 *addr = adapter->netdev->dev_addr; |
| 339 | |
| 340 | if (adapter->mc_enabled) |
| 341 | return 0; |
| 342 | |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 343 | val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG); |
Dhananjay Phadke | 623621b | 2008-07-21 19:44:01 -0700 | [diff] [blame] | 344 | val |= (1UL << (28+port)); |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 345 | NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val); |
Dhananjay Phadke | 623621b | 2008-07-21 19:44:01 -0700 | [diff] [blame] | 346 | |
| 347 | /* add broadcast addr to filter */ |
| 348 | val = 0xffffff; |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 349 | NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val); |
| 350 | NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val); |
Dhananjay Phadke | 623621b | 2008-07-21 19:44:01 -0700 | [diff] [blame] | 351 | |
| 352 | /* add station addr to filter */ |
| 353 | val = MAC_HI(addr); |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 354 | NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), val); |
Dhananjay Phadke | 623621b | 2008-07-21 19:44:01 -0700 | [diff] [blame] | 355 | val = MAC_LO(addr); |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 356 | NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, val); |
Dhananjay Phadke | 623621b | 2008-07-21 19:44:01 -0700 | [diff] [blame] | 357 | |
| 358 | adapter->mc_enabled = 1; |
| 359 | return 0; |
| 360 | } |
| 361 | |
| 362 | static int |
| 363 | netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter) |
| 364 | { |
| 365 | u32 val = 0; |
| 366 | u16 port = adapter->physical_port; |
| 367 | u8 *addr = adapter->netdev->dev_addr; |
| 368 | |
| 369 | if (!adapter->mc_enabled) |
| 370 | return 0; |
| 371 | |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 372 | val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG); |
Dhananjay Phadke | 623621b | 2008-07-21 19:44:01 -0700 | [diff] [blame] | 373 | val &= ~(1UL << (28+port)); |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 374 | NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val); |
Dhananjay Phadke | 623621b | 2008-07-21 19:44:01 -0700 | [diff] [blame] | 375 | |
| 376 | val = MAC_HI(addr); |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 377 | NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val); |
Dhananjay Phadke | 623621b | 2008-07-21 19:44:01 -0700 | [diff] [blame] | 378 | val = MAC_LO(addr); |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 379 | NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val); |
Dhananjay Phadke | 623621b | 2008-07-21 19:44:01 -0700 | [diff] [blame] | 380 | |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 381 | NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), 0); |
| 382 | NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0); |
Dhananjay Phadke | 623621b | 2008-07-21 19:44:01 -0700 | [diff] [blame] | 383 | |
| 384 | adapter->mc_enabled = 0; |
| 385 | return 0; |
| 386 | } |
| 387 | |
| 388 | static int |
| 389 | netxen_nic_set_mcast_addr(struct netxen_adapter *adapter, |
| 390 | int index, u8 *addr) |
| 391 | { |
| 392 | u32 hi = 0, lo = 0; |
| 393 | u16 port = adapter->physical_port; |
| 394 | |
| 395 | lo = MAC_LO(addr); |
| 396 | hi = MAC_HI(addr); |
| 397 | |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 398 | NXWR32(adapter, NETXEN_MCAST_ADDR(port, index), hi); |
| 399 | NXWR32(adapter, NETXEN_MCAST_ADDR(port, index)+4, lo); |
Dhananjay Phadke | 623621b | 2008-07-21 19:44:01 -0700 | [diff] [blame] | 400 | |
| 401 | return 0; |
| 402 | } |
| 403 | |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 404 | void netxen_p2_nic_set_multi(struct net_device *netdev) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 405 | { |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 406 | struct netxen_adapter *adapter = netdev_priv(netdev); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 407 | struct dev_mc_list *mc_ptr; |
Dhananjay Phadke | 623621b | 2008-07-21 19:44:01 -0700 | [diff] [blame] | 408 | u8 null_addr[6]; |
| 409 | int index = 0; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 410 | |
Dhananjay Phadke | 623621b | 2008-07-21 19:44:01 -0700 | [diff] [blame] | 411 | memset(null_addr, 0, 6); |
| 412 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 413 | if (netdev->flags & IFF_PROMISC) { |
Dhananjay Phadke | 623621b | 2008-07-21 19:44:01 -0700 | [diff] [blame] | 414 | |
| 415 | adapter->set_promisc(adapter, |
| 416 | NETXEN_NIU_PROMISC_MODE); |
| 417 | |
| 418 | /* Full promiscuous mode */ |
| 419 | netxen_nic_disable_mcast_filter(adapter); |
| 420 | |
| 421 | return; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 422 | } |
Dhananjay Phadke | 623621b | 2008-07-21 19:44:01 -0700 | [diff] [blame] | 423 | |
| 424 | if (netdev->mc_count == 0) { |
| 425 | adapter->set_promisc(adapter, |
| 426 | NETXEN_NIU_NON_PROMISC_MODE); |
| 427 | netxen_nic_disable_mcast_filter(adapter); |
| 428 | return; |
| 429 | } |
| 430 | |
| 431 | adapter->set_promisc(adapter, NETXEN_NIU_ALLMULTI_MODE); |
| 432 | if (netdev->flags & IFF_ALLMULTI || |
| 433 | netdev->mc_count > adapter->max_mc_count) { |
| 434 | netxen_nic_disable_mcast_filter(adapter); |
| 435 | return; |
| 436 | } |
| 437 | |
| 438 | netxen_nic_enable_mcast_filter(adapter); |
| 439 | |
| 440 | for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next, index++) |
| 441 | netxen_nic_set_mcast_addr(adapter, index, mc_ptr->dmi_addr); |
| 442 | |
| 443 | if (index != netdev->mc_count) |
| 444 | printk(KERN_WARNING "%s: %s multicast address count mismatch\n", |
| 445 | netxen_nic_driver_name, netdev->name); |
| 446 | |
| 447 | /* Clear out remaining addresses */ |
| 448 | for (; index < adapter->max_mc_count; index++) |
| 449 | netxen_nic_set_mcast_addr(adapter, index, null_addr); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 450 | } |
| 451 | |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 452 | static int |
| 453 | netxen_send_cmd_descs(struct netxen_adapter *adapter, |
Dhananjay Phadke | d877f1e | 2009-04-07 22:50:40 +0000 | [diff] [blame] | 454 | struct cmd_desc_type0 *cmd_desc_arr, int nr_desc) |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 455 | { |
Dhananjay Phadke | d877f1e | 2009-04-07 22:50:40 +0000 | [diff] [blame] | 456 | u32 i, producer, consumer; |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 457 | struct netxen_cmd_buffer *pbuf; |
| 458 | struct cmd_desc_type0 *cmd_desc; |
Dhananjay Phadke | d877f1e | 2009-04-07 22:50:40 +0000 | [diff] [blame] | 459 | struct nx_host_tx_ring *tx_ring; |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 460 | |
| 461 | i = 0; |
| 462 | |
Dhananjay Phadke | 4ea528a | 2009-04-28 15:29:10 +0000 | [diff] [blame] | 463 | tx_ring = adapter->tx_ring; |
Dhananjay Phadke | b2af9cb | 2009-07-17 15:27:07 +0000 | [diff] [blame] | 464 | __netif_tx_lock_bh(tx_ring->txq); |
Dhananjay Phadke | 03e678e | 2009-01-14 20:49:43 -0800 | [diff] [blame] | 465 | |
Dhananjay Phadke | d877f1e | 2009-04-07 22:50:40 +0000 | [diff] [blame] | 466 | producer = tx_ring->producer; |
| 467 | consumer = tx_ring->sw_consumer; |
| 468 | |
Dhananjay Phadke | b2af9cb | 2009-07-17 15:27:07 +0000 | [diff] [blame] | 469 | if (nr_desc >= netxen_tx_avail(tx_ring)) { |
| 470 | netif_tx_stop_queue(tx_ring->txq); |
| 471 | __netif_tx_unlock_bh(tx_ring->txq); |
Dhananjay Phadke | d877f1e | 2009-04-07 22:50:40 +0000 | [diff] [blame] | 472 | return -EBUSY; |
| 473 | } |
| 474 | |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 475 | do { |
| 476 | cmd_desc = &cmd_desc_arr[i]; |
| 477 | |
Dhananjay Phadke | d877f1e | 2009-04-07 22:50:40 +0000 | [diff] [blame] | 478 | pbuf = &tx_ring->cmd_buf_arr[producer]; |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 479 | pbuf->skb = NULL; |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 480 | pbuf->frag_count = 0; |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 481 | |
Dhananjay Phadke | d877f1e | 2009-04-07 22:50:40 +0000 | [diff] [blame] | 482 | memcpy(&tx_ring->desc_head[producer], |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 483 | &cmd_desc_arr[i], sizeof(struct cmd_desc_type0)); |
| 484 | |
Dhananjay Phadke | d877f1e | 2009-04-07 22:50:40 +0000 | [diff] [blame] | 485 | producer = get_next_index(producer, tx_ring->num_desc); |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 486 | i++; |
| 487 | |
Dhananjay Phadke | d877f1e | 2009-04-07 22:50:40 +0000 | [diff] [blame] | 488 | } while (i != nr_desc); |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 489 | |
Dhananjay Phadke | d877f1e | 2009-04-07 22:50:40 +0000 | [diff] [blame] | 490 | tx_ring->producer = producer; |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 491 | |
Dhananjay Phadke | cb2107b | 2009-06-17 17:27:25 +0000 | [diff] [blame] | 492 | netxen_nic_update_cmd_producer(adapter, tx_ring); |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 493 | |
Dhananjay Phadke | b2af9cb | 2009-07-17 15:27:07 +0000 | [diff] [blame] | 494 | __netif_tx_unlock_bh(tx_ring->txq); |
Dhananjay Phadke | 03e678e | 2009-01-14 20:49:43 -0800 | [diff] [blame] | 495 | |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 496 | return 0; |
| 497 | } |
| 498 | |
Dhananjay Phadke | 5cf4d32 | 2009-05-05 19:05:07 +0000 | [diff] [blame] | 499 | static int |
| 500 | nx_p3_sre_macaddr_change(struct netxen_adapter *adapter, u8 *addr, unsigned op) |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 501 | { |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 502 | nx_nic_req_t req; |
Dhananjay Phadke | 2edbb45 | 2009-01-14 20:47:30 -0800 | [diff] [blame] | 503 | nx_mac_req_t *mac_req; |
| 504 | u64 word; |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 505 | |
| 506 | memset(&req, 0, sizeof(nx_nic_req_t)); |
Dhananjay Phadke | 2edbb45 | 2009-01-14 20:47:30 -0800 | [diff] [blame] | 507 | req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23); |
| 508 | |
| 509 | word = NX_MAC_EVENT | ((u64)adapter->portnum << 16); |
| 510 | req.req_hdr = cpu_to_le64(word); |
| 511 | |
| 512 | mac_req = (nx_mac_req_t *)&req.words[0]; |
| 513 | mac_req->op = op; |
| 514 | memcpy(mac_req->mac_addr, addr, 6); |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 515 | |
Dhananjay Phadke | 5cf4d32 | 2009-05-05 19:05:07 +0000 | [diff] [blame] | 516 | return netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); |
| 517 | } |
| 518 | |
| 519 | static int nx_p3_nic_add_mac(struct netxen_adapter *adapter, |
| 520 | u8 *addr, struct list_head *del_list) |
| 521 | { |
| 522 | struct list_head *head; |
| 523 | nx_mac_list_t *cur; |
| 524 | |
| 525 | /* look up if already exists */ |
| 526 | list_for_each(head, del_list) { |
| 527 | cur = list_entry(head, nx_mac_list_t, list); |
| 528 | |
| 529 | if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) { |
| 530 | list_move_tail(head, &adapter->mac_list); |
| 531 | return 0; |
| 532 | } |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 533 | } |
| 534 | |
Dhananjay Phadke | 5cf4d32 | 2009-05-05 19:05:07 +0000 | [diff] [blame] | 535 | cur = kzalloc(sizeof(nx_mac_list_t), GFP_ATOMIC); |
| 536 | if (cur == NULL) { |
| 537 | printk(KERN_ERR "%s: failed to add mac address filter\n", |
| 538 | adapter->netdev->name); |
| 539 | return -ENOMEM; |
| 540 | } |
| 541 | memcpy(cur->mac_addr, addr, ETH_ALEN); |
| 542 | list_add_tail(&cur->list, &adapter->mac_list); |
| 543 | return nx_p3_sre_macaddr_change(adapter, |
| 544 | cur->mac_addr, NETXEN_MAC_ADD); |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 545 | } |
| 546 | |
| 547 | void netxen_p3_nic_set_multi(struct net_device *netdev) |
| 548 | { |
| 549 | struct netxen_adapter *adapter = netdev_priv(netdev); |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 550 | struct dev_mc_list *mc_ptr; |
| 551 | u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; |
Dhananjay Phadke | 9ad2764 | 2008-08-01 03:14:59 -0700 | [diff] [blame] | 552 | u32 mode = VPORT_MISS_MODE_DROP; |
Dhananjay Phadke | 5cf4d32 | 2009-05-05 19:05:07 +0000 | [diff] [blame] | 553 | LIST_HEAD(del_list); |
| 554 | struct list_head *head; |
| 555 | nx_mac_list_t *cur; |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 556 | |
Dhananjay Phadke | 5cf4d32 | 2009-05-05 19:05:07 +0000 | [diff] [blame] | 557 | list_splice_tail_init(&adapter->mac_list, &del_list); |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 558 | |
Dhananjay Phadke | 5cf4d32 | 2009-05-05 19:05:07 +0000 | [diff] [blame] | 559 | nx_p3_nic_add_mac(adapter, netdev->dev_addr, &del_list); |
| 560 | nx_p3_nic_add_mac(adapter, bcast_addr, &del_list); |
Dhananjay Phadke | 9ad2764 | 2008-08-01 03:14:59 -0700 | [diff] [blame] | 561 | |
| 562 | if (netdev->flags & IFF_PROMISC) { |
| 563 | mode = VPORT_MISS_MODE_ACCEPT_ALL; |
| 564 | goto send_fw_cmd; |
| 565 | } |
| 566 | |
| 567 | if ((netdev->flags & IFF_ALLMULTI) || |
| 568 | (netdev->mc_count > adapter->max_mc_count)) { |
| 569 | mode = VPORT_MISS_MODE_ACCEPT_MULTI; |
| 570 | goto send_fw_cmd; |
| 571 | } |
| 572 | |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 573 | if (netdev->mc_count > 0) { |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 574 | for (mc_ptr = netdev->mc_list; mc_ptr; |
| 575 | mc_ptr = mc_ptr->next) { |
Dhananjay Phadke | 5cf4d32 | 2009-05-05 19:05:07 +0000 | [diff] [blame] | 576 | nx_p3_nic_add_mac(adapter, mc_ptr->dmi_addr, &del_list); |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 577 | } |
| 578 | } |
Dhananjay Phadke | 9ad2764 | 2008-08-01 03:14:59 -0700 | [diff] [blame] | 579 | |
| 580 | send_fw_cmd: |
| 581 | adapter->set_promisc(adapter, mode); |
Dhananjay Phadke | 5cf4d32 | 2009-05-05 19:05:07 +0000 | [diff] [blame] | 582 | head = &del_list; |
| 583 | while (!list_empty(head)) { |
| 584 | cur = list_entry(head->next, nx_mac_list_t, list); |
| 585 | |
| 586 | nx_p3_sre_macaddr_change(adapter, |
| 587 | cur->mac_addr, NETXEN_MAC_DEL); |
| 588 | list_del(&cur->list); |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 589 | kfree(cur); |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 590 | } |
| 591 | } |
| 592 | |
Dhananjay Phadke | 9ad2764 | 2008-08-01 03:14:59 -0700 | [diff] [blame] | 593 | int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32 mode) |
| 594 | { |
| 595 | nx_nic_req_t req; |
Dhananjay Phadke | 2edbb45 | 2009-01-14 20:47:30 -0800 | [diff] [blame] | 596 | u64 word; |
Dhananjay Phadke | 9ad2764 | 2008-08-01 03:14:59 -0700 | [diff] [blame] | 597 | |
| 598 | memset(&req, 0, sizeof(nx_nic_req_t)); |
| 599 | |
Dhananjay Phadke | 2edbb45 | 2009-01-14 20:47:30 -0800 | [diff] [blame] | 600 | req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); |
| 601 | |
| 602 | word = NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE | |
| 603 | ((u64)adapter->portnum << 16); |
| 604 | req.req_hdr = cpu_to_le64(word); |
| 605 | |
Dhananjay Phadke | 9ad2764 | 2008-08-01 03:14:59 -0700 | [diff] [blame] | 606 | req.words[0] = cpu_to_le64(mode); |
| 607 | |
| 608 | return netxen_send_cmd_descs(adapter, |
| 609 | (struct cmd_desc_type0 *)&req, 1); |
| 610 | } |
| 611 | |
Dhananjay Phadke | 06e9d9f | 2009-01-14 20:49:22 -0800 | [diff] [blame] | 612 | void netxen_p3_free_mac_list(struct netxen_adapter *adapter) |
| 613 | { |
Dhananjay Phadke | 5cf4d32 | 2009-05-05 19:05:07 +0000 | [diff] [blame] | 614 | nx_mac_list_t *cur; |
| 615 | struct list_head *head = &adapter->mac_list; |
Dhananjay Phadke | 06e9d9f | 2009-01-14 20:49:22 -0800 | [diff] [blame] | 616 | |
Dhananjay Phadke | 5cf4d32 | 2009-05-05 19:05:07 +0000 | [diff] [blame] | 617 | while (!list_empty(head)) { |
| 618 | cur = list_entry(head->next, nx_mac_list_t, list); |
| 619 | nx_p3_sre_macaddr_change(adapter, |
| 620 | cur->mac_addr, NETXEN_MAC_DEL); |
| 621 | list_del(&cur->list); |
Dhananjay Phadke | 06e9d9f | 2009-01-14 20:49:22 -0800 | [diff] [blame] | 622 | kfree(cur); |
Dhananjay Phadke | 06e9d9f | 2009-01-14 20:49:22 -0800 | [diff] [blame] | 623 | } |
| 624 | } |
| 625 | |
Dhananjay Phadke | 3d0a3cc | 2009-05-05 19:05:08 +0000 | [diff] [blame] | 626 | int netxen_p3_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr) |
| 627 | { |
| 628 | /* assuming caller has already copied new addr to netdev */ |
| 629 | netxen_p3_nic_set_multi(adapter->netdev); |
| 630 | return 0; |
| 631 | } |
| 632 | |
Dhananjay Phadke | cd1f816 | 2008-07-21 19:44:09 -0700 | [diff] [blame] | 633 | #define NETXEN_CONFIG_INTR_COALESCE 3 |
| 634 | |
| 635 | /* |
| 636 | * Send the interrupt coalescing parameter set by ethtool to the card. |
| 637 | */ |
| 638 | int netxen_config_intr_coalesce(struct netxen_adapter *adapter) |
| 639 | { |
| 640 | nx_nic_req_t req; |
Dhananjay Phadke | 2edbb45 | 2009-01-14 20:47:30 -0800 | [diff] [blame] | 641 | u64 word; |
Dhananjay Phadke | cd1f816 | 2008-07-21 19:44:09 -0700 | [diff] [blame] | 642 | int rv; |
| 643 | |
| 644 | memset(&req, 0, sizeof(nx_nic_req_t)); |
| 645 | |
Dhananjay Phadke | 2edbb45 | 2009-01-14 20:47:30 -0800 | [diff] [blame] | 646 | req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23); |
| 647 | |
| 648 | word = NETXEN_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16); |
| 649 | req.req_hdr = cpu_to_le64(word); |
Dhananjay Phadke | cd1f816 | 2008-07-21 19:44:09 -0700 | [diff] [blame] | 650 | |
| 651 | memcpy(&req.words[0], &adapter->coal, sizeof(adapter->coal)); |
| 652 | |
| 653 | rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); |
| 654 | if (rv != 0) { |
| 655 | printk(KERN_ERR "ERROR. Could not send " |
| 656 | "interrupt coalescing parameters\n"); |
| 657 | } |
| 658 | |
| 659 | return rv; |
| 660 | } |
| 661 | |
Dhananjay Phadke | d8b100c | 2009-03-13 14:52:05 +0000 | [diff] [blame] | 662 | #define RSS_HASHTYPE_IP_TCP 0x3 |
| 663 | |
| 664 | int netxen_config_rss(struct netxen_adapter *adapter, int enable) |
| 665 | { |
| 666 | nx_nic_req_t req; |
| 667 | u64 word; |
| 668 | int i, rv; |
| 669 | |
| 670 | u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL, |
| 671 | 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL, |
| 672 | 0x255b0ec26d5a56daULL }; |
| 673 | |
| 674 | |
| 675 | memset(&req, 0, sizeof(nx_nic_req_t)); |
| 676 | req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); |
| 677 | |
| 678 | word = NX_NIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16); |
| 679 | req.req_hdr = cpu_to_le64(word); |
| 680 | |
| 681 | /* |
| 682 | * RSS request: |
| 683 | * bits 3-0: hash_method |
| 684 | * 5-4: hash_type_ipv4 |
| 685 | * 7-6: hash_type_ipv6 |
| 686 | * 8: enable |
| 687 | * 9: use indirection table |
| 688 | * 47-10: reserved |
| 689 | * 63-48: indirection table mask |
| 690 | */ |
| 691 | word = ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) | |
| 692 | ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) | |
| 693 | ((u64)(enable & 0x1) << 8) | |
| 694 | ((0x7ULL) << 48); |
| 695 | req.words[0] = cpu_to_le64(word); |
| 696 | for (i = 0; i < 5; i++) |
| 697 | req.words[i+1] = cpu_to_le64(key[i]); |
| 698 | |
| 699 | |
| 700 | rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); |
| 701 | if (rv != 0) { |
| 702 | printk(KERN_ERR "%s: could not configure RSS\n", |
| 703 | adapter->netdev->name); |
| 704 | } |
| 705 | |
| 706 | return rv; |
| 707 | } |
| 708 | |
Dhananjay Phadke | 3bf26ce | 2009-04-07 22:50:42 +0000 | [diff] [blame] | 709 | int netxen_linkevent_request(struct netxen_adapter *adapter, int enable) |
| 710 | { |
| 711 | nx_nic_req_t req; |
| 712 | u64 word; |
| 713 | int rv; |
| 714 | |
| 715 | memset(&req, 0, sizeof(nx_nic_req_t)); |
| 716 | req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); |
| 717 | |
| 718 | word = NX_NIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16); |
| 719 | req.req_hdr = cpu_to_le64(word); |
Dhananjay Phadke | 2252786 | 2009-05-05 19:05:06 +0000 | [diff] [blame] | 720 | req.words[0] = cpu_to_le64(enable | (enable << 8)); |
Dhananjay Phadke | 3bf26ce | 2009-04-07 22:50:42 +0000 | [diff] [blame] | 721 | |
| 722 | rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); |
| 723 | if (rv != 0) { |
| 724 | printk(KERN_ERR "%s: could not configure link notification\n", |
| 725 | adapter->netdev->name); |
| 726 | } |
| 727 | |
| 728 | return rv; |
| 729 | } |
| 730 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 731 | /* |
| 732 | * netxen_nic_change_mtu - Change the Maximum Transfer Unit |
| 733 | * @returns 0 on success, negative on failure |
| 734 | */ |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 735 | |
| 736 | #define MTU_FUDGE_FACTOR 100 |
| 737 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 738 | int netxen_nic_change_mtu(struct net_device *netdev, int mtu) |
| 739 | { |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 740 | struct netxen_adapter *adapter = netdev_priv(netdev); |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 741 | int max_mtu; |
Dhananjay Phadke | 9ad2764 | 2008-08-01 03:14:59 -0700 | [diff] [blame] | 742 | int rc = 0; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 743 | |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 744 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) |
| 745 | max_mtu = P3_MAX_MTU; |
| 746 | else |
| 747 | max_mtu = P2_MAX_MTU; |
| 748 | |
| 749 | if (mtu > max_mtu) { |
| 750 | printk(KERN_ERR "%s: mtu > %d bytes unsupported\n", |
| 751 | netdev->name, max_mtu); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 752 | return -EINVAL; |
| 753 | } |
| 754 | |
Amit S. Kale | 80922fb | 2006-12-04 09:18:00 -0800 | [diff] [blame] | 755 | if (adapter->set_mtu) |
Dhananjay Phadke | 9ad2764 | 2008-08-01 03:14:59 -0700 | [diff] [blame] | 756 | rc = adapter->set_mtu(adapter, mtu); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 757 | |
Dhananjay Phadke | 9ad2764 | 2008-08-01 03:14:59 -0700 | [diff] [blame] | 758 | if (!rc) |
| 759 | netdev->mtu = mtu; |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 760 | |
Dhananjay Phadke | 9ad2764 | 2008-08-01 03:14:59 -0700 | [diff] [blame] | 761 | return rc; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 762 | } |
| 763 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 764 | static int netxen_get_flash_block(struct netxen_adapter *adapter, int base, |
Al Viro | f305f78 | 2007-12-22 19:44:00 +0000 | [diff] [blame] | 765 | int size, __le32 * buf) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 766 | { |
Dhananjay Phadke | 1e2d005 | 2009-03-09 08:50:56 +0000 | [diff] [blame] | 767 | int i, v, addr; |
Al Viro | f305f78 | 2007-12-22 19:44:00 +0000 | [diff] [blame] | 768 | __le32 *ptr32; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 769 | |
| 770 | addr = base; |
| 771 | ptr32 = buf; |
| 772 | for (i = 0; i < size / sizeof(u32); i++) { |
Al Viro | f305f78 | 2007-12-22 19:44:00 +0000 | [diff] [blame] | 773 | if (netxen_rom_fast_read(adapter, addr, &v) == -1) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 774 | return -1; |
Al Viro | f305f78 | 2007-12-22 19:44:00 +0000 | [diff] [blame] | 775 | *ptr32 = cpu_to_le32(v); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 776 | ptr32++; |
| 777 | addr += sizeof(u32); |
| 778 | } |
| 779 | if ((char *)buf + size > (char *)ptr32) { |
Al Viro | f305f78 | 2007-12-22 19:44:00 +0000 | [diff] [blame] | 780 | __le32 local; |
| 781 | if (netxen_rom_fast_read(adapter, addr, &v) == -1) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 782 | return -1; |
Al Viro | f305f78 | 2007-12-22 19:44:00 +0000 | [diff] [blame] | 783 | local = cpu_to_le32(v); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 784 | memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32); |
| 785 | } |
| 786 | |
| 787 | return 0; |
| 788 | } |
| 789 | |
Dhananjay Phadke | 9dc28ef | 2008-08-08 00:08:39 -0700 | [diff] [blame] | 790 | int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 791 | { |
Dhananjay Phadke | 9dc28ef | 2008-08-08 00:08:39 -0700 | [diff] [blame] | 792 | __le32 *pmac = (__le32 *) mac; |
| 793 | u32 offset; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 794 | |
Dhananjay Phadke | 9dc28ef | 2008-08-08 00:08:39 -0700 | [diff] [blame] | 795 | offset = NETXEN_USER_START + |
| 796 | offsetof(struct netxen_new_user_info, mac_addr) + |
| 797 | adapter->portnum * sizeof(u64); |
| 798 | |
| 799 | if (netxen_get_flash_block(adapter, offset, sizeof(u64), pmac) == -1) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 800 | return -1; |
Dhananjay Phadke | 9dc28ef | 2008-08-08 00:08:39 -0700 | [diff] [blame] | 801 | |
Al Viro | f305f78 | 2007-12-22 19:44:00 +0000 | [diff] [blame] | 802 | if (*mac == cpu_to_le64(~0ULL)) { |
Dhananjay Phadke | 9dc28ef | 2008-08-08 00:08:39 -0700 | [diff] [blame] | 803 | |
| 804 | offset = NETXEN_USER_START_OLD + |
| 805 | offsetof(struct netxen_user_old_info, mac_addr) + |
| 806 | adapter->portnum * sizeof(u64); |
| 807 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 808 | if (netxen_get_flash_block(adapter, |
Dhananjay Phadke | 9dc28ef | 2008-08-08 00:08:39 -0700 | [diff] [blame] | 809 | offset, sizeof(u64), pmac) == -1) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 810 | return -1; |
Dhananjay Phadke | 9dc28ef | 2008-08-08 00:08:39 -0700 | [diff] [blame] | 811 | |
Al Viro | f305f78 | 2007-12-22 19:44:00 +0000 | [diff] [blame] | 812 | if (*mac == cpu_to_le64(~0ULL)) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 813 | return -1; |
| 814 | } |
| 815 | return 0; |
| 816 | } |
| 817 | |
Dhananjay Phadke | 9dc28ef | 2008-08-08 00:08:39 -0700 | [diff] [blame] | 818 | int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac) |
| 819 | { |
| 820 | uint32_t crbaddr, mac_hi, mac_lo; |
| 821 | int pci_func = adapter->ahw.pci_func; |
| 822 | |
| 823 | crbaddr = CRB_MAC_BLOCK_START + |
| 824 | (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1)); |
| 825 | |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 826 | mac_lo = NXRD32(adapter, crbaddr); |
| 827 | mac_hi = NXRD32(adapter, crbaddr+4); |
Dhananjay Phadke | 9dc28ef | 2008-08-08 00:08:39 -0700 | [diff] [blame] | 828 | |
Dhananjay Phadke | 9dc28ef | 2008-08-08 00:08:39 -0700 | [diff] [blame] | 829 | if (pci_func & 1) |
Dhananjay Phadke | 2edbb45 | 2009-01-14 20:47:30 -0800 | [diff] [blame] | 830 | *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16)); |
Dhananjay Phadke | 9dc28ef | 2008-08-08 00:08:39 -0700 | [diff] [blame] | 831 | else |
Dhananjay Phadke | 2edbb45 | 2009-01-14 20:47:30 -0800 | [diff] [blame] | 832 | *mac = le64_to_cpu((u64)mac_lo | ((u64)mac_hi << 32)); |
Dhananjay Phadke | 9dc28ef | 2008-08-08 00:08:39 -0700 | [diff] [blame] | 833 | |
| 834 | return 0; |
| 835 | } |
| 836 | |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 837 | #define CRB_WIN_LOCK_TIMEOUT 100000000 |
| 838 | |
| 839 | static int crb_win_lock(struct netxen_adapter *adapter) |
| 840 | { |
| 841 | int done = 0, timeout = 0; |
| 842 | |
| 843 | while (!done) { |
| 844 | /* acquire semaphore3 from PCI HW block */ |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 845 | done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM7_LOCK)); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 846 | if (done == 1) |
| 847 | break; |
| 848 | if (timeout >= CRB_WIN_LOCK_TIMEOUT) |
| 849 | return -1; |
| 850 | timeout++; |
| 851 | udelay(1); |
| 852 | } |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 853 | NXWR32(adapter, NETXEN_CRB_WIN_LOCK_ID, adapter->portnum); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 854 | return 0; |
| 855 | } |
| 856 | |
| 857 | static void crb_win_unlock(struct netxen_adapter *adapter) |
| 858 | { |
| 859 | int val; |
| 860 | |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 861 | val = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM7_UNLOCK)); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 862 | } |
| 863 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 864 | /* |
| 865 | * Changes the CRB window to the specified window. |
| 866 | */ |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 867 | void |
| 868 | netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter, u32 wndw) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 869 | { |
| 870 | void __iomem *offset; |
| 871 | u32 tmp; |
| 872 | int count = 0; |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 873 | uint8_t func = adapter->ahw.pci_func; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 874 | |
| 875 | if (adapter->curr_window == wndw) |
| 876 | return; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 877 | /* |
| 878 | * Move the CRB window. |
| 879 | * We need to write to the "direct access" region of PCI |
| 880 | * to avoid a race condition where the window register has |
| 881 | * not been successfully written across CRB before the target |
| 882 | * register address is received by PCI. The direct region bypasses |
| 883 | * the CRB bus. |
| 884 | */ |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 885 | offset = PCI_OFFSET_SECOND_RANGE(adapter, |
| 886 | NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func))); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 887 | |
| 888 | if (wndw & 0x1) |
| 889 | wndw = NETXEN_WINDOW_ONE; |
| 890 | |
| 891 | writel(wndw, offset); |
| 892 | |
| 893 | /* MUST make sure window is set before we forge on... */ |
| 894 | while ((tmp = readl(offset)) != wndw) { |
| 895 | printk(KERN_WARNING "%s: %s WARNING: CRB window value not " |
| 896 | "registered properly: 0x%08x.\n", |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 897 | netxen_nic_driver_name, __func__, tmp); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 898 | mdelay(1); |
| 899 | if (count >= 10) |
| 900 | break; |
| 901 | count++; |
| 902 | } |
| 903 | |
Mithlesh Thukral | 6c80b18 | 2007-04-20 07:55:26 -0700 | [diff] [blame] | 904 | if (wndw == NETXEN_WINDOW_ONE) |
| 905 | adapter->curr_window = 1; |
| 906 | else |
| 907 | adapter->curr_window = 0; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 908 | } |
| 909 | |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 910 | /* |
| 911 | * Return -1 if off is not valid, |
| 912 | * 1 if window access is needed. 'off' is set to offset from |
| 913 | * CRB space in 128M pci map |
| 914 | * 0 if no window access is needed. 'off' is set to 2M addr |
| 915 | * In: 'off' is offset from base in 128M pci map |
| 916 | */ |
| 917 | static int |
Dhananjay Phadke | 23b6cc4 | 2009-05-08 22:02:30 +0000 | [diff] [blame] | 918 | netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter, ulong *off) |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 919 | { |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 920 | crb_128M_2M_sub_block_map_t *m; |
| 921 | |
| 922 | |
| 923 | if (*off >= NETXEN_CRB_MAX) |
| 924 | return -1; |
| 925 | |
Dhananjay Phadke | 23b6cc4 | 2009-05-08 22:02:30 +0000 | [diff] [blame] | 926 | if (*off >= NETXEN_PCI_CAMQM && (*off < NETXEN_PCI_CAMQM_2M_END)) { |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 927 | *off = (*off - NETXEN_PCI_CAMQM) + NETXEN_PCI_CAMQM_2M_BASE + |
| 928 | (ulong)adapter->ahw.pci_base0; |
| 929 | return 0; |
| 930 | } |
| 931 | |
| 932 | if (*off < NETXEN_PCI_CRBSPACE) |
| 933 | return -1; |
| 934 | |
| 935 | *off -= NETXEN_PCI_CRBSPACE; |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 936 | |
| 937 | /* |
| 938 | * Try direct map |
| 939 | */ |
| 940 | m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)]; |
| 941 | |
Dhananjay Phadke | 23b6cc4 | 2009-05-08 22:02:30 +0000 | [diff] [blame] | 942 | if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) { |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 943 | *off = *off + m->start_2M - m->start_128M + |
| 944 | (ulong)adapter->ahw.pci_base0; |
| 945 | return 0; |
| 946 | } |
| 947 | |
| 948 | /* |
| 949 | * Not in direct map, use crb window |
| 950 | */ |
| 951 | return 1; |
| 952 | } |
| 953 | |
| 954 | /* |
| 955 | * In: 'off' is offset from CRB space in 128M pci map |
| 956 | * Out: 'off' is 2M pci map addr |
| 957 | * side effect: lock crb window |
| 958 | */ |
| 959 | static void |
| 960 | netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong *off) |
| 961 | { |
| 962 | u32 win_read; |
| 963 | |
| 964 | adapter->crb_win = CRB_HI(*off); |
Dhananjay Phadke | d8313ce | 2009-02-17 20:26:44 -0800 | [diff] [blame] | 965 | writel(adapter->crb_win, (adapter->ahw.pci_base0 + CRB_WINDOW_2M)); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 966 | /* |
| 967 | * Read back value to make sure write has gone through before trying |
| 968 | * to use it. |
| 969 | */ |
Dhananjay Phadke | d8313ce | 2009-02-17 20:26:44 -0800 | [diff] [blame] | 970 | win_read = readl(adapter->ahw.pci_base0 + CRB_WINDOW_2M); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 971 | if (win_read != adapter->crb_win) { |
| 972 | printk(KERN_ERR "%s: Written crbwin (0x%x) != " |
| 973 | "Read crbwin (0x%x), off=0x%lx\n", |
| 974 | __func__, adapter->crb_win, win_read, *off); |
| 975 | } |
| 976 | *off = (*off & MASK(16)) + CRB_INDIRECT_2M + |
| 977 | (ulong)adapter->ahw.pci_base0; |
| 978 | } |
| 979 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 980 | int |
Dhananjay Phadke | 1fbe632 | 2009-04-07 22:50:44 +0000 | [diff] [blame] | 981 | netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter, ulong off, u32 data) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 982 | { |
| 983 | void __iomem *addr; |
| 984 | |
| 985 | if (ADDR_IN_WINDOW1(off)) { |
| 986 | addr = NETXEN_CRB_NORMALIZE(adapter, off); |
| 987 | } else { /* Window 0 */ |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 988 | addr = pci_base_offset(adapter, off); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 989 | netxen_nic_pci_change_crbwindow_128M(adapter, 0); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 990 | } |
| 991 | |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 992 | if (!addr) { |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 993 | netxen_nic_pci_change_crbwindow_128M(adapter, 1); |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 994 | return 1; |
| 995 | } |
| 996 | |
Dhananjay Phadke | 1fbe632 | 2009-04-07 22:50:44 +0000 | [diff] [blame] | 997 | writel(data, addr); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 998 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 999 | if (!ADDR_IN_WINDOW1(off)) |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1000 | netxen_nic_pci_change_crbwindow_128M(adapter, 1); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1001 | |
| 1002 | return 0; |
| 1003 | } |
| 1004 | |
Dhananjay Phadke | 1fbe632 | 2009-04-07 22:50:44 +0000 | [diff] [blame] | 1005 | u32 |
| 1006 | netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, ulong off) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1007 | { |
| 1008 | void __iomem *addr; |
Dhananjay Phadke | 1fbe632 | 2009-04-07 22:50:44 +0000 | [diff] [blame] | 1009 | u32 data; |
Dhananjay Phadke | d8313ce | 2009-02-17 20:26:44 -0800 | [diff] [blame] | 1010 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1011 | if (ADDR_IN_WINDOW1(off)) { /* Window 1 */ |
| 1012 | addr = NETXEN_CRB_NORMALIZE(adapter, off); |
| 1013 | } else { /* Window 0 */ |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 1014 | addr = pci_base_offset(adapter, off); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1015 | netxen_nic_pci_change_crbwindow_128M(adapter, 0); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1016 | } |
| 1017 | |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 1018 | if (!addr) { |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1019 | netxen_nic_pci_change_crbwindow_128M(adapter, 1); |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 1020 | return 1; |
| 1021 | } |
Dhananjay Phadke | d8313ce | 2009-02-17 20:26:44 -0800 | [diff] [blame] | 1022 | |
Dhananjay Phadke | 1fbe632 | 2009-04-07 22:50:44 +0000 | [diff] [blame] | 1023 | data = readl(addr); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1024 | |
| 1025 | if (!ADDR_IN_WINDOW1(off)) |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1026 | netxen_nic_pci_change_crbwindow_128M(adapter, 1); |
| 1027 | |
Dhananjay Phadke | 1fbe632 | 2009-04-07 22:50:44 +0000 | [diff] [blame] | 1028 | return data; |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1029 | } |
| 1030 | |
| 1031 | int |
Dhananjay Phadke | 1fbe632 | 2009-04-07 22:50:44 +0000 | [diff] [blame] | 1032 | netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter, ulong off, u32 data) |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1033 | { |
| 1034 | unsigned long flags = 0; |
| 1035 | int rv; |
| 1036 | |
Dhananjay Phadke | 23b6cc4 | 2009-05-08 22:02:30 +0000 | [diff] [blame] | 1037 | rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1038 | |
| 1039 | if (rv == -1) { |
| 1040 | printk(KERN_ERR "%s: invalid offset: 0x%016lx\n", |
| 1041 | __func__, off); |
| 1042 | dump_stack(); |
| 1043 | return -1; |
| 1044 | } |
| 1045 | |
| 1046 | if (rv == 1) { |
| 1047 | write_lock_irqsave(&adapter->adapter_lock, flags); |
| 1048 | crb_win_lock(adapter); |
| 1049 | netxen_nic_pci_set_crbwindow_2M(adapter, &off); |
Dhananjay Phadke | 1fbe632 | 2009-04-07 22:50:44 +0000 | [diff] [blame] | 1050 | writel(data, (void __iomem *)off); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1051 | crb_win_unlock(adapter); |
| 1052 | write_unlock_irqrestore(&adapter->adapter_lock, flags); |
Dhananjay Phadke | d8313ce | 2009-02-17 20:26:44 -0800 | [diff] [blame] | 1053 | } else |
Dhananjay Phadke | 1fbe632 | 2009-04-07 22:50:44 +0000 | [diff] [blame] | 1054 | writel(data, (void __iomem *)off); |
Dhananjay Phadke | d8313ce | 2009-02-17 20:26:44 -0800 | [diff] [blame] | 1055 | |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1056 | |
| 1057 | return 0; |
| 1058 | } |
| 1059 | |
Dhananjay Phadke | 1fbe632 | 2009-04-07 22:50:44 +0000 | [diff] [blame] | 1060 | u32 |
| 1061 | netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off) |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1062 | { |
| 1063 | unsigned long flags = 0; |
| 1064 | int rv; |
Dhananjay Phadke | 1fbe632 | 2009-04-07 22:50:44 +0000 | [diff] [blame] | 1065 | u32 data; |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1066 | |
Dhananjay Phadke | 23b6cc4 | 2009-05-08 22:02:30 +0000 | [diff] [blame] | 1067 | rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1068 | |
| 1069 | if (rv == -1) { |
| 1070 | printk(KERN_ERR "%s: invalid offset: 0x%016lx\n", |
| 1071 | __func__, off); |
| 1072 | dump_stack(); |
| 1073 | return -1; |
| 1074 | } |
| 1075 | |
| 1076 | if (rv == 1) { |
| 1077 | write_lock_irqsave(&adapter->adapter_lock, flags); |
| 1078 | crb_win_lock(adapter); |
| 1079 | netxen_nic_pci_set_crbwindow_2M(adapter, &off); |
Dhananjay Phadke | 1fbe632 | 2009-04-07 22:50:44 +0000 | [diff] [blame] | 1080 | data = readl((void __iomem *)off); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1081 | crb_win_unlock(adapter); |
| 1082 | write_unlock_irqrestore(&adapter->adapter_lock, flags); |
Dhananjay Phadke | d8313ce | 2009-02-17 20:26:44 -0800 | [diff] [blame] | 1083 | } else |
Dhananjay Phadke | 1fbe632 | 2009-04-07 22:50:44 +0000 | [diff] [blame] | 1084 | data = readl((void __iomem *)off); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1085 | |
Dhananjay Phadke | 1fbe632 | 2009-04-07 22:50:44 +0000 | [diff] [blame] | 1086 | return data; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1087 | } |
| 1088 | |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1089 | /* |
| 1090 | * check memory access boundary. |
| 1091 | * used by test agent. support ddr access only for now |
| 1092 | */ |
| 1093 | static unsigned long |
| 1094 | netxen_nic_pci_mem_bound_check(struct netxen_adapter *adapter, |
| 1095 | unsigned long long addr, int size) |
| 1096 | { |
| 1097 | if (!ADDR_IN_RANGE(addr, |
| 1098 | NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) || |
| 1099 | !ADDR_IN_RANGE(addr+size-1, |
| 1100 | NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) || |
| 1101 | ((size != 1) && (size != 2) && (size != 4) && (size != 8))) { |
| 1102 | return 0; |
| 1103 | } |
| 1104 | |
| 1105 | return 1; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1106 | } |
| 1107 | |
Jeff Garzik | 4790654 | 2007-11-23 21:23:36 -0500 | [diff] [blame] | 1108 | static int netxen_pci_set_window_warning_count; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1109 | |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1110 | unsigned long |
| 1111 | netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter, |
| 1112 | unsigned long long addr) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1113 | { |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 1114 | void __iomem *offset; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1115 | int window; |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1116 | unsigned long long qdr_max; |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 1117 | uint8_t func = adapter->ahw.pci_func; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1118 | |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1119 | if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { |
| 1120 | qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2; |
| 1121 | } else { |
| 1122 | qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3; |
| 1123 | } |
| 1124 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1125 | if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) { |
| 1126 | /* DDR network side */ |
| 1127 | addr -= NETXEN_ADDR_DDR_NET; |
| 1128 | window = (addr >> 25) & 0x3ff; |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1129 | if (adapter->ahw.ddr_mn_window != window) { |
| 1130 | adapter->ahw.ddr_mn_window = window; |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 1131 | offset = PCI_OFFSET_SECOND_RANGE(adapter, |
| 1132 | NETXEN_PCIX_PH_REG(PCIE_MN_WINDOW_REG(func))); |
| 1133 | writel(window, offset); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1134 | /* MUST make sure window is set before we forge on... */ |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 1135 | readl(offset); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1136 | } |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 1137 | addr -= (window * NETXEN_WINDOW_ONE); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1138 | addr += NETXEN_PCI_DDR_NET; |
| 1139 | } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) { |
| 1140 | addr -= NETXEN_ADDR_OCM0; |
| 1141 | addr += NETXEN_PCI_OCM0; |
| 1142 | } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) { |
| 1143 | addr -= NETXEN_ADDR_OCM1; |
| 1144 | addr += NETXEN_PCI_OCM1; |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1145 | } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) { |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1146 | /* QDR network side */ |
| 1147 | addr -= NETXEN_ADDR_QDR_NET; |
| 1148 | window = (addr >> 22) & 0x3f; |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1149 | if (adapter->ahw.qdr_sn_window != window) { |
| 1150 | adapter->ahw.qdr_sn_window = window; |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 1151 | offset = PCI_OFFSET_SECOND_RANGE(adapter, |
| 1152 | NETXEN_PCIX_PH_REG(PCIE_SN_WINDOW_REG(func))); |
| 1153 | writel((window << 22), offset); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1154 | /* MUST make sure window is set before we forge on... */ |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 1155 | readl(offset); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1156 | } |
| 1157 | addr -= (window * 0x400000); |
| 1158 | addr += NETXEN_PCI_QDR_NET; |
| 1159 | } else { |
| 1160 | /* |
| 1161 | * peg gdb frequently accesses memory that doesn't exist, |
| 1162 | * this limits the chit chat so debugging isn't slowed down. |
| 1163 | */ |
| 1164 | if ((netxen_pci_set_window_warning_count++ < 8) |
| 1165 | || (netxen_pci_set_window_warning_count % 64 == 0)) |
| 1166 | printk("%s: Warning:netxen_nic_pci_set_window()" |
| 1167 | " Unknown address range!\n", |
| 1168 | netxen_nic_driver_name); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1169 | addr = -1UL; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1170 | } |
| 1171 | return addr; |
| 1172 | } |
| 1173 | |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1174 | /* |
| 1175 | * Note : only 32-bit writes! |
| 1176 | */ |
| 1177 | int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter, |
| 1178 | u64 off, u32 data) |
| 1179 | { |
| 1180 | writel(data, (void __iomem *)(PCI_OFFSET_SECOND_RANGE(adapter, off))); |
| 1181 | return 0; |
| 1182 | } |
| 1183 | |
| 1184 | u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off) |
| 1185 | { |
| 1186 | return readl((void __iomem *)(pci_base_offset(adapter, off))); |
| 1187 | } |
| 1188 | |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1189 | unsigned long |
| 1190 | netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter, |
| 1191 | unsigned long long addr) |
| 1192 | { |
| 1193 | int window; |
| 1194 | u32 win_read; |
| 1195 | |
| 1196 | if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) { |
| 1197 | /* DDR network side */ |
| 1198 | window = MN_WIN(addr); |
| 1199 | adapter->ahw.ddr_mn_window = window; |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 1200 | NXWR32(adapter, adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE, |
Dhananjay Phadke | 1fbe632 | 2009-04-07 22:50:44 +0000 | [diff] [blame] | 1201 | window); |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 1202 | win_read = NXRD32(adapter, |
Dhananjay Phadke | 1fbe632 | 2009-04-07 22:50:44 +0000 | [diff] [blame] | 1203 | adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1204 | if ((win_read << 17) != window) { |
| 1205 | printk(KERN_INFO "Written MNwin (0x%x) != " |
| 1206 | "Read MNwin (0x%x)\n", window, win_read); |
| 1207 | } |
| 1208 | addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_DDR_NET; |
| 1209 | } else if (ADDR_IN_RANGE(addr, |
| 1210 | NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) { |
| 1211 | if ((addr & 0x00ff800) == 0xff800) { |
| 1212 | printk("%s: QM access not handled.\n", __func__); |
| 1213 | addr = -1UL; |
| 1214 | } |
| 1215 | |
| 1216 | window = OCM_WIN(addr); |
| 1217 | adapter->ahw.ddr_mn_window = window; |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 1218 | NXWR32(adapter, adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE, |
Dhananjay Phadke | 1fbe632 | 2009-04-07 22:50:44 +0000 | [diff] [blame] | 1219 | window); |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 1220 | win_read = NXRD32(adapter, |
Dhananjay Phadke | 1fbe632 | 2009-04-07 22:50:44 +0000 | [diff] [blame] | 1221 | adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1222 | if ((win_read >> 7) != window) { |
| 1223 | printk(KERN_INFO "%s: Written OCMwin (0x%x) != " |
| 1224 | "Read OCMwin (0x%x)\n", |
| 1225 | __func__, window, win_read); |
| 1226 | } |
| 1227 | addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_OCM0_2M; |
| 1228 | |
| 1229 | } else if (ADDR_IN_RANGE(addr, |
| 1230 | NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX_P3)) { |
| 1231 | /* QDR network side */ |
| 1232 | window = MS_WIN(addr); |
| 1233 | adapter->ahw.qdr_sn_window = window; |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 1234 | NXWR32(adapter, adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE, |
Dhananjay Phadke | 1fbe632 | 2009-04-07 22:50:44 +0000 | [diff] [blame] | 1235 | window); |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 1236 | win_read = NXRD32(adapter, |
Dhananjay Phadke | 1fbe632 | 2009-04-07 22:50:44 +0000 | [diff] [blame] | 1237 | adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1238 | if (win_read != window) { |
| 1239 | printk(KERN_INFO "%s: Written MSwin (0x%x) != " |
| 1240 | "Read MSwin (0x%x)\n", |
| 1241 | __func__, window, win_read); |
| 1242 | } |
| 1243 | addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_QDR_NET; |
| 1244 | |
| 1245 | } else { |
| 1246 | /* |
| 1247 | * peg gdb frequently accesses memory that doesn't exist, |
| 1248 | * this limits the chit chat so debugging isn't slowed down. |
| 1249 | */ |
| 1250 | if ((netxen_pci_set_window_warning_count++ < 8) |
| 1251 | || (netxen_pci_set_window_warning_count%64 == 0)) { |
| 1252 | printk("%s: Warning:%s Unknown address range!\n", |
| 1253 | __func__, netxen_nic_driver_name); |
| 1254 | } |
| 1255 | addr = -1UL; |
| 1256 | } |
| 1257 | return addr; |
| 1258 | } |
| 1259 | |
| 1260 | static int netxen_nic_pci_is_same_window(struct netxen_adapter *adapter, |
| 1261 | unsigned long long addr) |
| 1262 | { |
| 1263 | int window; |
| 1264 | unsigned long long qdr_max; |
| 1265 | |
| 1266 | if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) |
| 1267 | qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2; |
| 1268 | else |
| 1269 | qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3; |
| 1270 | |
| 1271 | if (ADDR_IN_RANGE(addr, |
| 1272 | NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) { |
| 1273 | /* DDR network side */ |
| 1274 | BUG(); /* MN access can not come here */ |
| 1275 | } else if (ADDR_IN_RANGE(addr, |
| 1276 | NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) { |
| 1277 | return 1; |
| 1278 | } else if (ADDR_IN_RANGE(addr, |
| 1279 | NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) { |
| 1280 | return 1; |
| 1281 | } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) { |
| 1282 | /* QDR network side */ |
| 1283 | window = ((addr - NETXEN_ADDR_QDR_NET) >> 22) & 0x3f; |
| 1284 | if (adapter->ahw.qdr_sn_window == window) |
| 1285 | return 1; |
| 1286 | } |
| 1287 | |
| 1288 | return 0; |
| 1289 | } |
| 1290 | |
| 1291 | static int netxen_nic_pci_mem_read_direct(struct netxen_adapter *adapter, |
| 1292 | u64 off, void *data, int size) |
| 1293 | { |
| 1294 | unsigned long flags; |
Dhananjay Phadke | d8313ce | 2009-02-17 20:26:44 -0800 | [diff] [blame] | 1295 | void __iomem *addr, *mem_ptr = NULL; |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1296 | int ret = 0; |
| 1297 | u64 start; |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1298 | unsigned long mem_base; |
| 1299 | unsigned long mem_page; |
| 1300 | |
| 1301 | write_lock_irqsave(&adapter->adapter_lock, flags); |
| 1302 | |
| 1303 | /* |
| 1304 | * If attempting to access unknown address or straddle hw windows, |
| 1305 | * do not access. |
| 1306 | */ |
| 1307 | start = adapter->pci_set_window(adapter, off); |
| 1308 | if ((start == -1UL) || |
| 1309 | (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) { |
| 1310 | write_unlock_irqrestore(&adapter->adapter_lock, flags); |
| 1311 | printk(KERN_ERR "%s out of bound pci memory access. " |
Andrew Morton | 11a859e | 2008-07-30 12:50:12 -0700 | [diff] [blame] | 1312 | "offset is 0x%llx\n", netxen_nic_driver_name, |
| 1313 | (unsigned long long)off); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1314 | return -1; |
| 1315 | } |
| 1316 | |
Dhananjay Phadke | d8313ce | 2009-02-17 20:26:44 -0800 | [diff] [blame] | 1317 | addr = pci_base_offset(adapter, start); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1318 | if (!addr) { |
| 1319 | write_unlock_irqrestore(&adapter->adapter_lock, flags); |
| 1320 | mem_base = pci_resource_start(adapter->pdev, 0); |
| 1321 | mem_page = start & PAGE_MASK; |
| 1322 | /* Map two pages whenever user tries to access addresses in two |
| 1323 | consecutive pages. |
| 1324 | */ |
| 1325 | if (mem_page != ((start + size - 1) & PAGE_MASK)) |
| 1326 | mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2); |
| 1327 | else |
| 1328 | mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); |
Hannes Eder | f8057b7 | 2008-12-26 00:04:26 -0800 | [diff] [blame] | 1329 | if (mem_ptr == NULL) { |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1330 | *(uint8_t *)data = 0; |
| 1331 | return -1; |
| 1332 | } |
| 1333 | addr = mem_ptr; |
| 1334 | addr += start & (PAGE_SIZE - 1); |
| 1335 | write_lock_irqsave(&adapter->adapter_lock, flags); |
| 1336 | } |
| 1337 | |
| 1338 | switch (size) { |
| 1339 | case 1: |
| 1340 | *(uint8_t *)data = readb(addr); |
| 1341 | break; |
| 1342 | case 2: |
| 1343 | *(uint16_t *)data = readw(addr); |
| 1344 | break; |
| 1345 | case 4: |
| 1346 | *(uint32_t *)data = readl(addr); |
| 1347 | break; |
| 1348 | case 8: |
| 1349 | *(uint64_t *)data = readq(addr); |
| 1350 | break; |
| 1351 | default: |
| 1352 | ret = -1; |
| 1353 | break; |
| 1354 | } |
| 1355 | write_unlock_irqrestore(&adapter->adapter_lock, flags); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1356 | |
| 1357 | if (mem_ptr) |
| 1358 | iounmap(mem_ptr); |
| 1359 | return ret; |
| 1360 | } |
| 1361 | |
| 1362 | static int |
| 1363 | netxen_nic_pci_mem_write_direct(struct netxen_adapter *adapter, u64 off, |
| 1364 | void *data, int size) |
| 1365 | { |
| 1366 | unsigned long flags; |
Dhananjay Phadke | d8313ce | 2009-02-17 20:26:44 -0800 | [diff] [blame] | 1367 | void __iomem *addr, *mem_ptr = NULL; |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1368 | int ret = 0; |
| 1369 | u64 start; |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1370 | unsigned long mem_base; |
| 1371 | unsigned long mem_page; |
| 1372 | |
| 1373 | write_lock_irqsave(&adapter->adapter_lock, flags); |
| 1374 | |
| 1375 | /* |
| 1376 | * If attempting to access unknown address or straddle hw windows, |
| 1377 | * do not access. |
| 1378 | */ |
| 1379 | start = adapter->pci_set_window(adapter, off); |
| 1380 | if ((start == -1UL) || |
| 1381 | (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) { |
| 1382 | write_unlock_irqrestore(&adapter->adapter_lock, flags); |
| 1383 | printk(KERN_ERR "%s out of bound pci memory access. " |
Andrew Morton | 11a859e | 2008-07-30 12:50:12 -0700 | [diff] [blame] | 1384 | "offset is 0x%llx\n", netxen_nic_driver_name, |
| 1385 | (unsigned long long)off); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1386 | return -1; |
| 1387 | } |
| 1388 | |
Dhananjay Phadke | d8313ce | 2009-02-17 20:26:44 -0800 | [diff] [blame] | 1389 | addr = pci_base_offset(adapter, start); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1390 | if (!addr) { |
| 1391 | write_unlock_irqrestore(&adapter->adapter_lock, flags); |
| 1392 | mem_base = pci_resource_start(adapter->pdev, 0); |
| 1393 | mem_page = start & PAGE_MASK; |
| 1394 | /* Map two pages whenever user tries to access addresses in two |
| 1395 | * consecutive pages. |
| 1396 | */ |
| 1397 | if (mem_page != ((start + size - 1) & PAGE_MASK)) |
| 1398 | mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2); |
| 1399 | else |
| 1400 | mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); |
Hannes Eder | f8057b7 | 2008-12-26 00:04:26 -0800 | [diff] [blame] | 1401 | if (mem_ptr == NULL) |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1402 | return -1; |
| 1403 | addr = mem_ptr; |
| 1404 | addr += start & (PAGE_SIZE - 1); |
| 1405 | write_lock_irqsave(&adapter->adapter_lock, flags); |
| 1406 | } |
| 1407 | |
| 1408 | switch (size) { |
| 1409 | case 1: |
| 1410 | writeb(*(uint8_t *)data, addr); |
| 1411 | break; |
| 1412 | case 2: |
| 1413 | writew(*(uint16_t *)data, addr); |
| 1414 | break; |
| 1415 | case 4: |
| 1416 | writel(*(uint32_t *)data, addr); |
| 1417 | break; |
| 1418 | case 8: |
| 1419 | writeq(*(uint64_t *)data, addr); |
| 1420 | break; |
| 1421 | default: |
| 1422 | ret = -1; |
| 1423 | break; |
| 1424 | } |
| 1425 | write_unlock_irqrestore(&adapter->adapter_lock, flags); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1426 | if (mem_ptr) |
| 1427 | iounmap(mem_ptr); |
| 1428 | return ret; |
| 1429 | } |
| 1430 | |
| 1431 | #define MAX_CTL_CHECK 1000 |
| 1432 | |
| 1433 | int |
| 1434 | netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter, |
| 1435 | u64 off, void *data, int size) |
| 1436 | { |
Dhananjay Phadke | d8313ce | 2009-02-17 20:26:44 -0800 | [diff] [blame] | 1437 | unsigned long flags; |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1438 | int i, j, ret = 0, loop, sz[2], off0; |
| 1439 | uint32_t temp; |
| 1440 | uint64_t off8, tmpw, word[2] = {0, 0}; |
Dhananjay Phadke | d8313ce | 2009-02-17 20:26:44 -0800 | [diff] [blame] | 1441 | void __iomem *mem_crb; |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1442 | |
| 1443 | /* |
| 1444 | * If not MN, go check for MS or invalid. |
| 1445 | */ |
| 1446 | if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0) |
| 1447 | return netxen_nic_pci_mem_write_direct(adapter, |
| 1448 | off, data, size); |
| 1449 | |
| 1450 | off8 = off & 0xfffffff8; |
| 1451 | off0 = off & 0x7; |
| 1452 | sz[0] = (size < (8 - off0)) ? size : (8 - off0); |
| 1453 | sz[1] = size - sz[0]; |
| 1454 | loop = ((off0 + size - 1) >> 3) + 1; |
Dhananjay Phadke | d8313ce | 2009-02-17 20:26:44 -0800 | [diff] [blame] | 1455 | mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1456 | |
| 1457 | if ((size != 8) || (off0 != 0)) { |
| 1458 | for (i = 0; i < loop; i++) { |
| 1459 | if (adapter->pci_mem_read(adapter, |
| 1460 | off8 + (i << 3), &word[i], 8)) |
| 1461 | return -1; |
| 1462 | } |
| 1463 | } |
| 1464 | |
| 1465 | switch (size) { |
| 1466 | case 1: |
| 1467 | tmpw = *((uint8_t *)data); |
| 1468 | break; |
| 1469 | case 2: |
| 1470 | tmpw = *((uint16_t *)data); |
| 1471 | break; |
| 1472 | case 4: |
| 1473 | tmpw = *((uint32_t *)data); |
| 1474 | break; |
| 1475 | case 8: |
| 1476 | default: |
| 1477 | tmpw = *((uint64_t *)data); |
| 1478 | break; |
| 1479 | } |
| 1480 | word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); |
| 1481 | word[0] |= tmpw << (off0 * 8); |
| 1482 | |
| 1483 | if (loop == 2) { |
| 1484 | word[1] &= ~(~0ULL << (sz[1] * 8)); |
| 1485 | word[1] |= tmpw >> (sz[0] * 8); |
| 1486 | } |
| 1487 | |
| 1488 | write_lock_irqsave(&adapter->adapter_lock, flags); |
| 1489 | netxen_nic_pci_change_crbwindow_128M(adapter, 0); |
| 1490 | |
| 1491 | for (i = 0; i < loop; i++) { |
| 1492 | writel((uint32_t)(off8 + (i << 3)), |
Dhananjay Phadke | d8313ce | 2009-02-17 20:26:44 -0800 | [diff] [blame] | 1493 | (mem_crb+MIU_TEST_AGT_ADDR_LO)); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1494 | writel(0, |
Dhananjay Phadke | d8313ce | 2009-02-17 20:26:44 -0800 | [diff] [blame] | 1495 | (mem_crb+MIU_TEST_AGT_ADDR_HI)); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1496 | writel(word[i] & 0xffffffff, |
Dhananjay Phadke | d8313ce | 2009-02-17 20:26:44 -0800 | [diff] [blame] | 1497 | (mem_crb+MIU_TEST_AGT_WRDATA_LO)); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1498 | writel((word[i] >> 32) & 0xffffffff, |
Dhananjay Phadke | d8313ce | 2009-02-17 20:26:44 -0800 | [diff] [blame] | 1499 | (mem_crb+MIU_TEST_AGT_WRDATA_HI)); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1500 | writel(MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE, |
Dhananjay Phadke | d8313ce | 2009-02-17 20:26:44 -0800 | [diff] [blame] | 1501 | (mem_crb+MIU_TEST_AGT_CTRL)); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1502 | writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE, |
Dhananjay Phadke | d8313ce | 2009-02-17 20:26:44 -0800 | [diff] [blame] | 1503 | (mem_crb+MIU_TEST_AGT_CTRL)); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1504 | |
| 1505 | for (j = 0; j < MAX_CTL_CHECK; j++) { |
| 1506 | temp = readl( |
Dhananjay Phadke | d8313ce | 2009-02-17 20:26:44 -0800 | [diff] [blame] | 1507 | (mem_crb+MIU_TEST_AGT_CTRL)); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1508 | if ((temp & MIU_TA_CTL_BUSY) == 0) |
| 1509 | break; |
| 1510 | } |
| 1511 | |
| 1512 | if (j >= MAX_CTL_CHECK) { |
Dhananjay Phadke | 39754f4 | 2009-02-17 20:27:02 -0800 | [diff] [blame] | 1513 | if (printk_ratelimit()) |
| 1514 | dev_err(&adapter->pdev->dev, |
| 1515 | "failed to write through agent\n"); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1516 | ret = -1; |
| 1517 | break; |
| 1518 | } |
| 1519 | } |
| 1520 | |
| 1521 | netxen_nic_pci_change_crbwindow_128M(adapter, 1); |
| 1522 | write_unlock_irqrestore(&adapter->adapter_lock, flags); |
| 1523 | return ret; |
| 1524 | } |
| 1525 | |
| 1526 | int |
| 1527 | netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter, |
| 1528 | u64 off, void *data, int size) |
| 1529 | { |
Dhananjay Phadke | d8313ce | 2009-02-17 20:26:44 -0800 | [diff] [blame] | 1530 | unsigned long flags; |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1531 | int i, j = 0, k, start, end, loop, sz[2], off0[2]; |
| 1532 | uint32_t temp; |
| 1533 | uint64_t off8, val, word[2] = {0, 0}; |
Dhananjay Phadke | d8313ce | 2009-02-17 20:26:44 -0800 | [diff] [blame] | 1534 | void __iomem *mem_crb; |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1535 | |
| 1536 | |
| 1537 | /* |
| 1538 | * If not MN, go check for MS or invalid. |
| 1539 | */ |
| 1540 | if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0) |
| 1541 | return netxen_nic_pci_mem_read_direct(adapter, off, data, size); |
| 1542 | |
| 1543 | off8 = off & 0xfffffff8; |
| 1544 | off0[0] = off & 0x7; |
| 1545 | off0[1] = 0; |
| 1546 | sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]); |
| 1547 | sz[1] = size - sz[0]; |
| 1548 | loop = ((off0[0] + size - 1) >> 3) + 1; |
Dhananjay Phadke | d8313ce | 2009-02-17 20:26:44 -0800 | [diff] [blame] | 1549 | mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1550 | |
| 1551 | write_lock_irqsave(&adapter->adapter_lock, flags); |
| 1552 | netxen_nic_pci_change_crbwindow_128M(adapter, 0); |
| 1553 | |
| 1554 | for (i = 0; i < loop; i++) { |
| 1555 | writel((uint32_t)(off8 + (i << 3)), |
Dhananjay Phadke | d8313ce | 2009-02-17 20:26:44 -0800 | [diff] [blame] | 1556 | (mem_crb+MIU_TEST_AGT_ADDR_LO)); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1557 | writel(0, |
Dhananjay Phadke | d8313ce | 2009-02-17 20:26:44 -0800 | [diff] [blame] | 1558 | (mem_crb+MIU_TEST_AGT_ADDR_HI)); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1559 | writel(MIU_TA_CTL_ENABLE, |
Dhananjay Phadke | d8313ce | 2009-02-17 20:26:44 -0800 | [diff] [blame] | 1560 | (mem_crb+MIU_TEST_AGT_CTRL)); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1561 | writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE, |
Dhananjay Phadke | d8313ce | 2009-02-17 20:26:44 -0800 | [diff] [blame] | 1562 | (mem_crb+MIU_TEST_AGT_CTRL)); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1563 | |
| 1564 | for (j = 0; j < MAX_CTL_CHECK; j++) { |
| 1565 | temp = readl( |
Dhananjay Phadke | d8313ce | 2009-02-17 20:26:44 -0800 | [diff] [blame] | 1566 | (mem_crb+MIU_TEST_AGT_CTRL)); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1567 | if ((temp & MIU_TA_CTL_BUSY) == 0) |
| 1568 | break; |
| 1569 | } |
| 1570 | |
| 1571 | if (j >= MAX_CTL_CHECK) { |
Dhananjay Phadke | 39754f4 | 2009-02-17 20:27:02 -0800 | [diff] [blame] | 1572 | if (printk_ratelimit()) |
| 1573 | dev_err(&adapter->pdev->dev, |
| 1574 | "failed to read through agent\n"); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1575 | break; |
| 1576 | } |
| 1577 | |
| 1578 | start = off0[i] >> 2; |
| 1579 | end = (off0[i] + sz[i] - 1) >> 2; |
| 1580 | for (k = start; k <= end; k++) { |
| 1581 | word[i] |= ((uint64_t) readl( |
Dhananjay Phadke | d8313ce | 2009-02-17 20:26:44 -0800 | [diff] [blame] | 1582 | (mem_crb + |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1583 | MIU_TEST_AGT_RDDATA(k))) << (32*k)); |
| 1584 | } |
| 1585 | } |
| 1586 | |
| 1587 | netxen_nic_pci_change_crbwindow_128M(adapter, 1); |
| 1588 | write_unlock_irqrestore(&adapter->adapter_lock, flags); |
| 1589 | |
| 1590 | if (j >= MAX_CTL_CHECK) |
| 1591 | return -1; |
| 1592 | |
| 1593 | if (sz[0] == 8) { |
| 1594 | val = word[0]; |
| 1595 | } else { |
| 1596 | val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | |
| 1597 | ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); |
| 1598 | } |
| 1599 | |
| 1600 | switch (size) { |
| 1601 | case 1: |
| 1602 | *(uint8_t *)data = val; |
| 1603 | break; |
| 1604 | case 2: |
| 1605 | *(uint16_t *)data = val; |
| 1606 | break; |
| 1607 | case 4: |
| 1608 | *(uint32_t *)data = val; |
| 1609 | break; |
| 1610 | case 8: |
| 1611 | *(uint64_t *)data = val; |
| 1612 | break; |
| 1613 | } |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1614 | return 0; |
| 1615 | } |
| 1616 | |
| 1617 | int |
| 1618 | netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter, |
| 1619 | u64 off, void *data, int size) |
| 1620 | { |
| 1621 | int i, j, ret = 0, loop, sz[2], off0; |
| 1622 | uint32_t temp; |
| 1623 | uint64_t off8, mem_crb, tmpw, word[2] = {0, 0}; |
| 1624 | |
| 1625 | /* |
| 1626 | * If not MN, go check for MS or invalid. |
| 1627 | */ |
| 1628 | if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3) |
| 1629 | mem_crb = NETXEN_CRB_QDR_NET; |
| 1630 | else { |
| 1631 | mem_crb = NETXEN_CRB_DDR_NET; |
| 1632 | if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0) |
| 1633 | return netxen_nic_pci_mem_write_direct(adapter, |
| 1634 | off, data, size); |
| 1635 | } |
| 1636 | |
| 1637 | off8 = off & 0xfffffff8; |
| 1638 | off0 = off & 0x7; |
| 1639 | sz[0] = (size < (8 - off0)) ? size : (8 - off0); |
| 1640 | sz[1] = size - sz[0]; |
| 1641 | loop = ((off0 + size - 1) >> 3) + 1; |
| 1642 | |
| 1643 | if ((size != 8) || (off0 != 0)) { |
| 1644 | for (i = 0; i < loop; i++) { |
| 1645 | if (adapter->pci_mem_read(adapter, off8 + (i << 3), |
| 1646 | &word[i], 8)) |
| 1647 | return -1; |
| 1648 | } |
| 1649 | } |
| 1650 | |
| 1651 | switch (size) { |
| 1652 | case 1: |
| 1653 | tmpw = *((uint8_t *)data); |
| 1654 | break; |
| 1655 | case 2: |
| 1656 | tmpw = *((uint16_t *)data); |
| 1657 | break; |
| 1658 | case 4: |
| 1659 | tmpw = *((uint32_t *)data); |
| 1660 | break; |
| 1661 | case 8: |
| 1662 | default: |
| 1663 | tmpw = *((uint64_t *)data); |
| 1664 | break; |
| 1665 | } |
| 1666 | |
| 1667 | word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); |
| 1668 | word[0] |= tmpw << (off0 * 8); |
| 1669 | |
| 1670 | if (loop == 2) { |
| 1671 | word[1] &= ~(~0ULL << (sz[1] * 8)); |
| 1672 | word[1] |= tmpw >> (sz[0] * 8); |
| 1673 | } |
| 1674 | |
| 1675 | /* |
| 1676 | * don't lock here - write_wx gets the lock if each time |
| 1677 | * write_lock_irqsave(&adapter->adapter_lock, flags); |
| 1678 | * netxen_nic_pci_change_crbwindow_128M(adapter, 0); |
| 1679 | */ |
| 1680 | |
| 1681 | for (i = 0; i < loop; i++) { |
| 1682 | temp = off8 + (i << 3); |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 1683 | NXWR32(adapter, mem_crb+MIU_TEST_AGT_ADDR_LO, temp); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1684 | temp = 0; |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 1685 | NXWR32(adapter, mem_crb+MIU_TEST_AGT_ADDR_HI, temp); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1686 | temp = word[i] & 0xffffffff; |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 1687 | NXWR32(adapter, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1688 | temp = (word[i] >> 32) & 0xffffffff; |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 1689 | NXWR32(adapter, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1690 | temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 1691 | NXWR32(adapter, mem_crb+MIU_TEST_AGT_CTRL, temp); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1692 | temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 1693 | NXWR32(adapter, mem_crb+MIU_TEST_AGT_CTRL, temp); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1694 | |
| 1695 | for (j = 0; j < MAX_CTL_CHECK; j++) { |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 1696 | temp = NXRD32(adapter, mem_crb + MIU_TEST_AGT_CTRL); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1697 | if ((temp & MIU_TA_CTL_BUSY) == 0) |
| 1698 | break; |
| 1699 | } |
| 1700 | |
| 1701 | if (j >= MAX_CTL_CHECK) { |
Dhananjay Phadke | 39754f4 | 2009-02-17 20:27:02 -0800 | [diff] [blame] | 1702 | if (printk_ratelimit()) |
| 1703 | dev_err(&adapter->pdev->dev, |
| 1704 | "failed to write through agent\n"); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1705 | ret = -1; |
| 1706 | break; |
| 1707 | } |
| 1708 | } |
| 1709 | |
| 1710 | /* |
| 1711 | * netxen_nic_pci_change_crbwindow_128M(adapter, 1); |
| 1712 | * write_unlock_irqrestore(&adapter->adapter_lock, flags); |
| 1713 | */ |
| 1714 | return ret; |
| 1715 | } |
| 1716 | |
| 1717 | int |
| 1718 | netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter, |
| 1719 | u64 off, void *data, int size) |
| 1720 | { |
| 1721 | int i, j = 0, k, start, end, loop, sz[2], off0[2]; |
| 1722 | uint32_t temp; |
| 1723 | uint64_t off8, val, mem_crb, word[2] = {0, 0}; |
| 1724 | |
| 1725 | /* |
| 1726 | * If not MN, go check for MS or invalid. |
| 1727 | */ |
| 1728 | |
| 1729 | if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3) |
| 1730 | mem_crb = NETXEN_CRB_QDR_NET; |
| 1731 | else { |
| 1732 | mem_crb = NETXEN_CRB_DDR_NET; |
| 1733 | if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0) |
| 1734 | return netxen_nic_pci_mem_read_direct(adapter, |
| 1735 | off, data, size); |
| 1736 | } |
| 1737 | |
| 1738 | off8 = off & 0xfffffff8; |
| 1739 | off0[0] = off & 0x7; |
| 1740 | off0[1] = 0; |
| 1741 | sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]); |
| 1742 | sz[1] = size - sz[0]; |
| 1743 | loop = ((off0[0] + size - 1) >> 3) + 1; |
| 1744 | |
| 1745 | /* |
| 1746 | * don't lock here - write_wx gets the lock if each time |
| 1747 | * write_lock_irqsave(&adapter->adapter_lock, flags); |
| 1748 | * netxen_nic_pci_change_crbwindow_128M(adapter, 0); |
| 1749 | */ |
| 1750 | |
| 1751 | for (i = 0; i < loop; i++) { |
| 1752 | temp = off8 + (i << 3); |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 1753 | NXWR32(adapter, mem_crb + MIU_TEST_AGT_ADDR_LO, temp); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1754 | temp = 0; |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 1755 | NXWR32(adapter, mem_crb + MIU_TEST_AGT_ADDR_HI, temp); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1756 | temp = MIU_TA_CTL_ENABLE; |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 1757 | NXWR32(adapter, mem_crb + MIU_TEST_AGT_CTRL, temp); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1758 | temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 1759 | NXWR32(adapter, mem_crb + MIU_TEST_AGT_CTRL, temp); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1760 | |
| 1761 | for (j = 0; j < MAX_CTL_CHECK; j++) { |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 1762 | temp = NXRD32(adapter, mem_crb + MIU_TEST_AGT_CTRL); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1763 | if ((temp & MIU_TA_CTL_BUSY) == 0) |
| 1764 | break; |
| 1765 | } |
| 1766 | |
| 1767 | if (j >= MAX_CTL_CHECK) { |
Dhananjay Phadke | 39754f4 | 2009-02-17 20:27:02 -0800 | [diff] [blame] | 1768 | if (printk_ratelimit()) |
| 1769 | dev_err(&adapter->pdev->dev, |
| 1770 | "failed to read through agent\n"); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1771 | break; |
| 1772 | } |
| 1773 | |
| 1774 | start = off0[i] >> 2; |
| 1775 | end = (off0[i] + sz[i] - 1) >> 2; |
| 1776 | for (k = start; k <= end; k++) { |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 1777 | temp = NXRD32(adapter, |
Dhananjay Phadke | 1fbe632 | 2009-04-07 22:50:44 +0000 | [diff] [blame] | 1778 | mem_crb + MIU_TEST_AGT_RDDATA(k)); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1779 | word[i] |= ((uint64_t)temp << (32 * k)); |
| 1780 | } |
| 1781 | } |
| 1782 | |
| 1783 | /* |
| 1784 | * netxen_nic_pci_change_crbwindow_128M(adapter, 1); |
| 1785 | * write_unlock_irqrestore(&adapter->adapter_lock, flags); |
| 1786 | */ |
| 1787 | |
| 1788 | if (j >= MAX_CTL_CHECK) |
| 1789 | return -1; |
| 1790 | |
| 1791 | if (sz[0] == 8) { |
| 1792 | val = word[0]; |
| 1793 | } else { |
| 1794 | val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | |
| 1795 | ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); |
| 1796 | } |
| 1797 | |
| 1798 | switch (size) { |
| 1799 | case 1: |
| 1800 | *(uint8_t *)data = val; |
| 1801 | break; |
| 1802 | case 2: |
| 1803 | *(uint16_t *)data = val; |
| 1804 | break; |
| 1805 | case 4: |
| 1806 | *(uint32_t *)data = val; |
| 1807 | break; |
| 1808 | case 8: |
| 1809 | *(uint64_t *)data = val; |
| 1810 | break; |
| 1811 | } |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1812 | return 0; |
| 1813 | } |
| 1814 | |
| 1815 | /* |
| 1816 | * Note : only 32-bit writes! |
| 1817 | */ |
| 1818 | int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter, |
| 1819 | u64 off, u32 data) |
| 1820 | { |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 1821 | NXWR32(adapter, off, data); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1822 | |
| 1823 | return 0; |
| 1824 | } |
| 1825 | |
| 1826 | u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off) |
| 1827 | { |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 1828 | return NXRD32(adapter, off); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1829 | } |
| 1830 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1831 | int netxen_nic_get_board_info(struct netxen_adapter *adapter) |
| 1832 | { |
Dhananjay Phadke | 1e2d005 | 2009-03-09 08:50:56 +0000 | [diff] [blame] | 1833 | int offset, board_type, magic, header_version; |
| 1834 | struct pci_dev *pdev = adapter->pdev; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1835 | |
Dhananjay Phadke | 1e2d005 | 2009-03-09 08:50:56 +0000 | [diff] [blame] | 1836 | offset = NETXEN_BRDCFG_START + |
| 1837 | offsetof(struct netxen_board_info, magic); |
| 1838 | if (netxen_rom_fast_read(adapter, offset, &magic)) |
| 1839 | return -EIO; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1840 | |
Dhananjay Phadke | 1e2d005 | 2009-03-09 08:50:56 +0000 | [diff] [blame] | 1841 | offset = NETXEN_BRDCFG_START + |
| 1842 | offsetof(struct netxen_board_info, header_version); |
| 1843 | if (netxen_rom_fast_read(adapter, offset, &header_version)) |
| 1844 | return -EIO; |
| 1845 | |
| 1846 | if (magic != NETXEN_BDINFO_MAGIC || |
| 1847 | header_version != NETXEN_BDINFO_VERSION) { |
| 1848 | dev_err(&pdev->dev, |
| 1849 | "invalid board config, magic=%08x, version=%08x\n", |
| 1850 | magic, header_version); |
| 1851 | return -EIO; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1852 | } |
| 1853 | |
Dhananjay Phadke | 1e2d005 | 2009-03-09 08:50:56 +0000 | [diff] [blame] | 1854 | offset = NETXEN_BRDCFG_START + |
| 1855 | offsetof(struct netxen_board_info, board_type); |
| 1856 | if (netxen_rom_fast_read(adapter, offset, &board_type)) |
| 1857 | return -EIO; |
| 1858 | |
| 1859 | adapter->ahw.board_type = board_type; |
| 1860 | |
| 1861 | if (board_type == NETXEN_BRDTYPE_P3_4_GB_MM) { |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 1862 | u32 gpio = NXRD32(adapter, NETXEN_ROMUSB_GLB_PAD_GPIO_I); |
Dhananjay Phadke | c7860a2 | 2009-01-14 20:48:32 -0800 | [diff] [blame] | 1863 | if ((gpio & 0x8000) == 0) |
Dhananjay Phadke | 1e2d005 | 2009-03-09 08:50:56 +0000 | [diff] [blame] | 1864 | board_type = NETXEN_BRDTYPE_P3_10G_TP; |
Dhananjay Phadke | c7860a2 | 2009-01-14 20:48:32 -0800 | [diff] [blame] | 1865 | } |
| 1866 | |
Dhananjay Phadke | e98e335 | 2009-04-07 22:50:38 +0000 | [diff] [blame] | 1867 | switch (board_type) { |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1868 | case NETXEN_BRDTYPE_P2_SB35_4G: |
Dhananjay Phadke | 1e2d005 | 2009-03-09 08:50:56 +0000 | [diff] [blame] | 1869 | adapter->ahw.port_type = NETXEN_NIC_GBE; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1870 | break; |
| 1871 | case NETXEN_BRDTYPE_P2_SB31_10G: |
| 1872 | case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ: |
| 1873 | case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ: |
| 1874 | case NETXEN_BRDTYPE_P2_SB31_10G_CX4: |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 1875 | case NETXEN_BRDTYPE_P3_HMEZ: |
| 1876 | case NETXEN_BRDTYPE_P3_XG_LOM: |
| 1877 | case NETXEN_BRDTYPE_P3_10G_CX4: |
| 1878 | case NETXEN_BRDTYPE_P3_10G_CX4_LP: |
| 1879 | case NETXEN_BRDTYPE_P3_IMEZ: |
| 1880 | case NETXEN_BRDTYPE_P3_10G_SFP_PLUS: |
Dhananjay Phadke | a70f939 | 2008-08-01 03:14:56 -0700 | [diff] [blame] | 1881 | case NETXEN_BRDTYPE_P3_10G_SFP_CT: |
| 1882 | case NETXEN_BRDTYPE_P3_10G_SFP_QT: |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 1883 | case NETXEN_BRDTYPE_P3_10G_XFP: |
| 1884 | case NETXEN_BRDTYPE_P3_10000_BASE_T: |
Dhananjay Phadke | 1e2d005 | 2009-03-09 08:50:56 +0000 | [diff] [blame] | 1885 | adapter->ahw.port_type = NETXEN_NIC_XGBE; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1886 | break; |
| 1887 | case NETXEN_BRDTYPE_P1_BD: |
| 1888 | case NETXEN_BRDTYPE_P1_SB: |
| 1889 | case NETXEN_BRDTYPE_P1_SMAX: |
| 1890 | case NETXEN_BRDTYPE_P1_SOCK: |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 1891 | case NETXEN_BRDTYPE_P3_REF_QG: |
| 1892 | case NETXEN_BRDTYPE_P3_4_GB: |
| 1893 | case NETXEN_BRDTYPE_P3_4_GB_MM: |
Dhananjay Phadke | 1e2d005 | 2009-03-09 08:50:56 +0000 | [diff] [blame] | 1894 | adapter->ahw.port_type = NETXEN_NIC_GBE; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1895 | break; |
Dhananjay Phadke | c7860a2 | 2009-01-14 20:48:32 -0800 | [diff] [blame] | 1896 | case NETXEN_BRDTYPE_P3_10G_TP: |
Dhananjay Phadke | 1e2d005 | 2009-03-09 08:50:56 +0000 | [diff] [blame] | 1897 | adapter->ahw.port_type = (adapter->portnum < 2) ? |
Dhananjay Phadke | c7860a2 | 2009-01-14 20:48:32 -0800 | [diff] [blame] | 1898 | NETXEN_NIC_XGBE : NETXEN_NIC_GBE; |
| 1899 | break; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1900 | default: |
Dhananjay Phadke | 1e2d005 | 2009-03-09 08:50:56 +0000 | [diff] [blame] | 1901 | dev_err(&pdev->dev, "unknown board type %x\n", board_type); |
| 1902 | adapter->ahw.port_type = NETXEN_NIC_XGBE; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1903 | break; |
| 1904 | } |
| 1905 | |
Dhananjay Phadke | 1e2d005 | 2009-03-09 08:50:56 +0000 | [diff] [blame] | 1906 | return 0; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1907 | } |
| 1908 | |
| 1909 | /* NIU access sections */ |
| 1910 | |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 1911 | int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1912 | { |
Dhananjay Phadke | 9ad2764 | 2008-08-01 03:14:59 -0700 | [diff] [blame] | 1913 | new_mtu += MTU_FUDGE_FACTOR; |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 1914 | NXWR32(adapter, NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port), |
Dhananjay Phadke | 3276fba | 2008-06-15 22:59:44 -0700 | [diff] [blame] | 1915 | new_mtu); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1916 | return 0; |
| 1917 | } |
| 1918 | |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 1919 | int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1920 | { |
Dhananjay Phadke | 9ad2764 | 2008-08-01 03:14:59 -0700 | [diff] [blame] | 1921 | new_mtu += MTU_FUDGE_FACTOR; |
Dhananjay Phadke | 3276fba | 2008-06-15 22:59:44 -0700 | [diff] [blame] | 1922 | if (adapter->physical_port == 0) |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 1923 | NXWR32(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, new_mtu); |
Jeff Garzik | 4790654 | 2007-11-23 21:23:36 -0500 | [diff] [blame] | 1924 | else |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 1925 | NXWR32(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE, new_mtu); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1926 | return 0; |
| 1927 | } |
| 1928 | |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 1929 | void netxen_nic_set_link_parameters(struct netxen_adapter *adapter) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1930 | { |
Al Viro | a608ab9 | 2007-01-02 10:39:10 +0000 | [diff] [blame] | 1931 | __u32 status; |
| 1932 | __u32 autoneg; |
Dhananjay Phadke | 24a7a45 | 2008-08-01 03:14:55 -0700 | [diff] [blame] | 1933 | __u32 port_mode; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1934 | |
Dhananjay Phadke | c7860a2 | 2009-01-14 20:48:32 -0800 | [diff] [blame] | 1935 | if (!netif_carrier_ok(adapter->netdev)) { |
| 1936 | adapter->link_speed = 0; |
| 1937 | adapter->link_duplex = -1; |
| 1938 | adapter->link_autoneg = AUTONEG_ENABLE; |
| 1939 | return; |
| 1940 | } |
Dhananjay Phadke | 24a7a45 | 2008-08-01 03:14:55 -0700 | [diff] [blame] | 1941 | |
Dhananjay Phadke | 1e2d005 | 2009-03-09 08:50:56 +0000 | [diff] [blame] | 1942 | if (adapter->ahw.port_type == NETXEN_NIC_GBE) { |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 1943 | port_mode = NXRD32(adapter, NETXEN_PORT_MODE_ADDR); |
Dhananjay Phadke | 24a7a45 | 2008-08-01 03:14:55 -0700 | [diff] [blame] | 1944 | if (port_mode == NETXEN_PORT_MODE_802_3_AP) { |
| 1945 | adapter->link_speed = SPEED_1000; |
| 1946 | adapter->link_duplex = DUPLEX_FULL; |
| 1947 | adapter->link_autoneg = AUTONEG_DISABLE; |
| 1948 | return; |
| 1949 | } |
| 1950 | |
Amit S. Kale | 80922fb | 2006-12-04 09:18:00 -0800 | [diff] [blame] | 1951 | if (adapter->phy_read |
Dhananjay Phadke | 24a7a45 | 2008-08-01 03:14:55 -0700 | [diff] [blame] | 1952 | && adapter->phy_read(adapter, |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1953 | NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS, |
| 1954 | &status) == 0) { |
| 1955 | if (netxen_get_phy_link(status)) { |
| 1956 | switch (netxen_get_phy_speed(status)) { |
| 1957 | case 0: |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 1958 | adapter->link_speed = SPEED_10; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1959 | break; |
| 1960 | case 1: |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 1961 | adapter->link_speed = SPEED_100; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1962 | break; |
| 1963 | case 2: |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 1964 | adapter->link_speed = SPEED_1000; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1965 | break; |
| 1966 | default: |
Dhananjay Phadke | c7860a2 | 2009-01-14 20:48:32 -0800 | [diff] [blame] | 1967 | adapter->link_speed = 0; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1968 | break; |
| 1969 | } |
| 1970 | switch (netxen_get_phy_duplex(status)) { |
| 1971 | case 0: |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 1972 | adapter->link_duplex = DUPLEX_HALF; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1973 | break; |
| 1974 | case 1: |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 1975 | adapter->link_duplex = DUPLEX_FULL; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1976 | break; |
| 1977 | default: |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 1978 | adapter->link_duplex = -1; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1979 | break; |
| 1980 | } |
Amit S. Kale | 80922fb | 2006-12-04 09:18:00 -0800 | [diff] [blame] | 1981 | if (adapter->phy_read |
Dhananjay Phadke | 24a7a45 | 2008-08-01 03:14:55 -0700 | [diff] [blame] | 1982 | && adapter->phy_read(adapter, |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1983 | NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG, |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 1984 | &autoneg) != 0) |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 1985 | adapter->link_autoneg = autoneg; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1986 | } else |
| 1987 | goto link_down; |
| 1988 | } else { |
| 1989 | link_down: |
Dhananjay Phadke | c7860a2 | 2009-01-14 20:48:32 -0800 | [diff] [blame] | 1990 | adapter->link_speed = 0; |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 1991 | adapter->link_duplex = -1; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1992 | } |
| 1993 | } |
| 1994 | } |
| 1995 | |
Dhananjay Phadke | 1e2d005 | 2009-03-09 08:50:56 +0000 | [diff] [blame] | 1996 | void netxen_nic_get_firmware_info(struct netxen_adapter *adapter) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1997 | { |
Dhananjay Phadke | 1e2d005 | 2009-03-09 08:50:56 +0000 | [diff] [blame] | 1998 | u32 fw_major, fw_minor, fw_build; |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 1999 | char brd_name[NETXEN_MAX_SHORT_NAME]; |
Harvey Harrison | 8d74849 | 2008-04-22 11:48:35 -0700 | [diff] [blame] | 2000 | char serial_num[32]; |
Dhananjay Phadke | fbb52f2 | 2009-03-13 14:52:01 +0000 | [diff] [blame] | 2001 | int i, addr, val; |
Dhananjay Phadke | d8313ce | 2009-02-17 20:26:44 -0800 | [diff] [blame] | 2002 | int *ptr32; |
Dhananjay Phadke | 1e2d005 | 2009-03-09 08:50:56 +0000 | [diff] [blame] | 2003 | struct pci_dev *pdev = adapter->pdev; |
Harvey Harrison | 8d74849 | 2008-04-22 11:48:35 -0700 | [diff] [blame] | 2004 | |
Dhananjay Phadke | dcd56fd | 2008-06-15 22:59:45 -0700 | [diff] [blame] | 2005 | adapter->driver_mismatch = 0; |
| 2006 | |
Dhananjay Phadke | d8313ce | 2009-02-17 20:26:44 -0800 | [diff] [blame] | 2007 | ptr32 = (int *)&serial_num; |
Dhananjay Phadke | dcd56fd | 2008-06-15 22:59:45 -0700 | [diff] [blame] | 2008 | addr = NETXEN_USER_START + |
| 2009 | offsetof(struct netxen_new_user_info, serial_num); |
| 2010 | for (i = 0; i < 8; i++) { |
Dhananjay Phadke | fbb52f2 | 2009-03-13 14:52:01 +0000 | [diff] [blame] | 2011 | if (netxen_rom_fast_read(adapter, addr, &val) == -1) { |
| 2012 | dev_err(&pdev->dev, "error reading board info\n"); |
Dhananjay Phadke | dcd56fd | 2008-06-15 22:59:45 -0700 | [diff] [blame] | 2013 | adapter->driver_mismatch = 1; |
| 2014 | return; |
| 2015 | } |
Dhananjay Phadke | fbb52f2 | 2009-03-13 14:52:01 +0000 | [diff] [blame] | 2016 | ptr32[i] = cpu_to_le32(val); |
Dhananjay Phadke | dcd56fd | 2008-06-15 22:59:45 -0700 | [diff] [blame] | 2017 | addr += sizeof(u32); |
| 2018 | } |
| 2019 | |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 2020 | fw_major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR); |
| 2021 | fw_minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR); |
| 2022 | fw_build = NXRD32(adapter, NETXEN_FW_VERSION_SUB); |
Dhananjay Phadke | dcd56fd | 2008-06-15 22:59:45 -0700 | [diff] [blame] | 2023 | |
Dhananjay Phadke | 2956640 | 2008-07-21 19:44:04 -0700 | [diff] [blame] | 2024 | adapter->fw_major = fw_major; |
Dhananjay Phadke | 1e2d005 | 2009-03-09 08:50:56 +0000 | [diff] [blame] | 2025 | adapter->fw_version = NETXEN_VERSION_CODE(fw_major, fw_minor, fw_build); |
Dhananjay Phadke | 2956640 | 2008-07-21 19:44:04 -0700 | [diff] [blame] | 2026 | |
Dhananjay Phadke | dcd56fd | 2008-06-15 22:59:45 -0700 | [diff] [blame] | 2027 | if (adapter->portnum == 0) { |
Dhananjay Phadke | 1e2d005 | 2009-03-09 08:50:56 +0000 | [diff] [blame] | 2028 | get_brd_name_by_type(adapter->ahw.board_type, brd_name); |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 2029 | |
Dhananjay Phadke | 11d89d6 | 2008-08-08 00:08:45 -0700 | [diff] [blame] | 2030 | printk(KERN_INFO "NetXen %s Board S/N %s Chip rev 0x%x\n", |
| 2031 | brd_name, serial_num, adapter->ahw.revision_id); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2032 | } |
Dhananjay Phadke | dcd56fd | 2008-06-15 22:59:45 -0700 | [diff] [blame] | 2033 | |
Dhananjay Phadke | 1e2d005 | 2009-03-09 08:50:56 +0000 | [diff] [blame] | 2034 | if (adapter->fw_version < NETXEN_VERSION_CODE(3, 4, 216)) { |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2035 | adapter->driver_mismatch = 1; |
Dhananjay Phadke | 1e2d005 | 2009-03-09 08:50:56 +0000 | [diff] [blame] | 2036 | dev_warn(&pdev->dev, "firmware version %d.%d.%d unsupported\n", |
Dhananjay Phadke | 5873556 | 2008-07-21 19:44:10 -0700 | [diff] [blame] | 2037 | fw_major, fw_minor, fw_build); |
Dhananjay Phadke | dcd56fd | 2008-06-15 22:59:45 -0700 | [diff] [blame] | 2038 | return; |
| 2039 | } |
Dhananjay Phadke | 1e2d005 | 2009-03-09 08:50:56 +0000 | [diff] [blame] | 2040 | |
| 2041 | dev_info(&pdev->dev, "firmware version %d.%d.%d\n", |
| 2042 | fw_major, fw_minor, fw_build); |
| 2043 | |
| 2044 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { |
Dhananjay Phadke | d173346 | 2009-06-17 17:27:24 +0000 | [diff] [blame] | 2045 | i = NXRD32(adapter, NETXEN_SRE_MISC); |
| 2046 | adapter->ahw.cut_through = (i & 0x8000) ? 1 : 0; |
Dhananjay Phadke | 1e2d005 | 2009-03-09 08:50:56 +0000 | [diff] [blame] | 2047 | dev_info(&pdev->dev, "firmware running in %s mode\n", |
| 2048 | adapter->ahw.cut_through ? "cut-through" : "legacy"); |
| 2049 | } |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2050 | } |
| 2051 | |
Dhananjay Phadke | 0b72e65 | 2009-03-13 14:52:02 +0000 | [diff] [blame] | 2052 | int |
| 2053 | netxen_nic_wol_supported(struct netxen_adapter *adapter) |
| 2054 | { |
| 2055 | u32 wol_cfg; |
| 2056 | |
| 2057 | if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) |
| 2058 | return 0; |
| 2059 | |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 2060 | wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG_NV); |
Dhananjay Phadke | 0b72e65 | 2009-03-13 14:52:02 +0000 | [diff] [blame] | 2061 | if (wol_cfg & (1UL << adapter->portnum)) { |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 2062 | wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG); |
Dhananjay Phadke | 0b72e65 | 2009-03-13 14:52:02 +0000 | [diff] [blame] | 2063 | if (wol_cfg & (1 << adapter->portnum)) |
| 2064 | return 1; |
| 2065 | } |
| 2066 | |
| 2067 | return 0; |
| 2068 | } |