Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1 | /* |
Pierre Ossman | 70f1048 | 2007-07-11 20:04:50 +0200 | [diff] [blame] | 2 | * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3 | * |
Giuseppe Cavallaro | 1978fda | 2010-09-28 10:41:29 +0200 | [diff] [blame] | 4 | * Header file for Host Controller registers and I/O accessors. |
| 5 | * |
Pierre Ossman | b69c905 | 2008-03-08 23:44:25 +0100 | [diff] [blame] | 6 | * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
Pierre Ossman | 643f720 | 2006-09-30 23:27:52 -0700 | [diff] [blame] | 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or (at |
| 11 | * your option) any later version. |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 12 | */ |
Giuseppe Cavallaro | 1978fda | 2010-09-28 10:41:29 +0200 | [diff] [blame] | 13 | #ifndef __SDHCI_HW_H |
| 14 | #define __SDHCI_HW_H |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 15 | |
Andrew Morton | 0c7ad10 | 2008-07-25 19:44:35 -0700 | [diff] [blame] | 16 | #include <linux/scatterlist.h> |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 17 | #include <linux/compiler.h> |
| 18 | #include <linux/types.h> |
| 19 | #include <linux/io.h> |
Andrew Morton | 0c7ad10 | 2008-07-25 19:44:35 -0700 | [diff] [blame] | 20 | |
Giuseppe Cavallaro | 1978fda | 2010-09-28 10:41:29 +0200 | [diff] [blame] | 21 | #include <linux/mmc/sdhci.h> |
| 22 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 23 | /* |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 24 | * Controller registers |
| 25 | */ |
| 26 | |
| 27 | #define SDHCI_DMA_ADDRESS 0x00 |
Andrei Warkentin | 8edf6371 | 2011-05-23 15:06:39 -0500 | [diff] [blame] | 28 | #define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 29 | |
| 30 | #define SDHCI_BLOCK_SIZE 0x04 |
Pierre Ossman | bab7696 | 2006-07-02 16:51:35 +0100 | [diff] [blame] | 31 | #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 32 | |
| 33 | #define SDHCI_BLOCK_COUNT 0x06 |
| 34 | |
| 35 | #define SDHCI_ARGUMENT 0x08 |
| 36 | |
| 37 | #define SDHCI_TRANSFER_MODE 0x0C |
| 38 | #define SDHCI_TRNS_DMA 0x01 |
| 39 | #define SDHCI_TRNS_BLK_CNT_EN 0x02 |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 40 | #define SDHCI_TRNS_AUTO_CMD12 0x04 |
Andrei Warkentin | 8edf6371 | 2011-05-23 15:06:39 -0500 | [diff] [blame] | 41 | #define SDHCI_TRNS_AUTO_CMD23 0x08 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 42 | #define SDHCI_TRNS_READ 0x10 |
| 43 | #define SDHCI_TRNS_MULTI 0x20 |
| 44 | |
| 45 | #define SDHCI_COMMAND 0x0E |
| 46 | #define SDHCI_CMD_RESP_MASK 0x03 |
| 47 | #define SDHCI_CMD_CRC 0x08 |
| 48 | #define SDHCI_CMD_INDEX 0x10 |
| 49 | #define SDHCI_CMD_DATA 0x20 |
Richard Zhu | 574e3f5 | 2011-03-21 13:22:14 +0800 | [diff] [blame] | 50 | #define SDHCI_CMD_ABORTCMD 0xC0 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 51 | |
| 52 | #define SDHCI_CMD_RESP_NONE 0x00 |
| 53 | #define SDHCI_CMD_RESP_LONG 0x01 |
| 54 | #define SDHCI_CMD_RESP_SHORT 0x02 |
| 55 | #define SDHCI_CMD_RESP_SHORT_BUSY 0x03 |
| 56 | |
| 57 | #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) |
Aries Lee | 22113ef | 2010-12-15 08:14:24 +0100 | [diff] [blame] | 58 | #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 59 | |
| 60 | #define SDHCI_RESPONSE 0x10 |
| 61 | |
| 62 | #define SDHCI_BUFFER 0x20 |
| 63 | |
| 64 | #define SDHCI_PRESENT_STATE 0x24 |
| 65 | #define SDHCI_CMD_INHIBIT 0x00000001 |
| 66 | #define SDHCI_DATA_INHIBIT 0x00000002 |
| 67 | #define SDHCI_DOING_WRITE 0x00000100 |
| 68 | #define SDHCI_DOING_READ 0x00000200 |
| 69 | #define SDHCI_SPACE_AVAILABLE 0x00000400 |
| 70 | #define SDHCI_DATA_AVAILABLE 0x00000800 |
| 71 | #define SDHCI_CARD_PRESENT 0x00010000 |
| 72 | #define SDHCI_WRITE_PROTECT 0x00080000 |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 73 | #define SDHCI_DATA_LVL_MASK 0x00F00000 |
| 74 | #define SDHCI_DATA_LVL_SHIFT 20 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 75 | |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 76 | #define SDHCI_HOST_CONTROL 0x28 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 77 | #define SDHCI_CTRL_LED 0x01 |
| 78 | #define SDHCI_CTRL_4BITBUS 0x02 |
Pierre Ossman | 077df88 | 2006-11-08 23:06:35 +0100 | [diff] [blame] | 79 | #define SDHCI_CTRL_HISPD 0x04 |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 80 | #define SDHCI_CTRL_DMA_MASK 0x18 |
| 81 | #define SDHCI_CTRL_SDMA 0x00 |
| 82 | #define SDHCI_CTRL_ADMA1 0x08 |
| 83 | #define SDHCI_CTRL_ADMA32 0x10 |
| 84 | #define SDHCI_CTRL_ADMA64 0x18 |
Philip Rakity | 15ec446 | 2010-11-19 16:48:39 -0500 | [diff] [blame] | 85 | #define SDHCI_CTRL_8BITBUS 0x20 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 86 | |
| 87 | #define SDHCI_POWER_CONTROL 0x29 |
Pierre Ossman | 146ad66 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 88 | #define SDHCI_POWER_ON 0x01 |
| 89 | #define SDHCI_POWER_180 0x0A |
| 90 | #define SDHCI_POWER_300 0x0C |
| 91 | #define SDHCI_POWER_330 0x0E |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 92 | |
| 93 | #define SDHCI_BLOCK_GAP_CONTROL 0x2A |
| 94 | |
Nicolas Pitre | 2df3b71 | 2007-09-29 10:46:20 -0400 | [diff] [blame] | 95 | #define SDHCI_WAKE_UP_CONTROL 0x2B |
Daniel Drake | 5f61970 | 2010-11-04 22:20:39 +0000 | [diff] [blame] | 96 | #define SDHCI_WAKE_ON_INT 0x01 |
| 97 | #define SDHCI_WAKE_ON_INSERT 0x02 |
| 98 | #define SDHCI_WAKE_ON_REMOVE 0x04 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 99 | |
| 100 | #define SDHCI_CLOCK_CONTROL 0x2C |
| 101 | #define SDHCI_DIVIDER_SHIFT 8 |
Zhangfei Gao | 85105c5 | 2010-08-06 07:10:01 +0800 | [diff] [blame] | 102 | #define SDHCI_DIVIDER_HI_SHIFT 6 |
| 103 | #define SDHCI_DIV_MASK 0xFF |
| 104 | #define SDHCI_DIV_MASK_LEN 8 |
| 105 | #define SDHCI_DIV_HI_MASK 0x300 |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 106 | #define SDHCI_PROG_CLOCK_MODE 0x0020 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 107 | #define SDHCI_CLOCK_CARD_EN 0x0004 |
| 108 | #define SDHCI_CLOCK_INT_STABLE 0x0002 |
| 109 | #define SDHCI_CLOCK_INT_EN 0x0001 |
| 110 | |
| 111 | #define SDHCI_TIMEOUT_CONTROL 0x2E |
| 112 | |
| 113 | #define SDHCI_SOFTWARE_RESET 0x2F |
| 114 | #define SDHCI_RESET_ALL 0x01 |
| 115 | #define SDHCI_RESET_CMD 0x02 |
| 116 | #define SDHCI_RESET_DATA 0x04 |
| 117 | |
| 118 | #define SDHCI_INT_STATUS 0x30 |
| 119 | #define SDHCI_INT_ENABLE 0x34 |
| 120 | #define SDHCI_SIGNAL_ENABLE 0x38 |
| 121 | #define SDHCI_INT_RESPONSE 0x00000001 |
| 122 | #define SDHCI_INT_DATA_END 0x00000002 |
| 123 | #define SDHCI_INT_DMA_END 0x00000008 |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 124 | #define SDHCI_INT_SPACE_AVAIL 0x00000010 |
| 125 | #define SDHCI_INT_DATA_AVAIL 0x00000020 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 126 | #define SDHCI_INT_CARD_INSERT 0x00000040 |
| 127 | #define SDHCI_INT_CARD_REMOVE 0x00000080 |
| 128 | #define SDHCI_INT_CARD_INT 0x00000100 |
Pierre Ossman | 964f9ce | 2007-07-20 18:20:36 +0200 | [diff] [blame] | 129 | #define SDHCI_INT_ERROR 0x00008000 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 130 | #define SDHCI_INT_TIMEOUT 0x00010000 |
| 131 | #define SDHCI_INT_CRC 0x00020000 |
| 132 | #define SDHCI_INT_END_BIT 0x00040000 |
| 133 | #define SDHCI_INT_INDEX 0x00080000 |
| 134 | #define SDHCI_INT_DATA_TIMEOUT 0x00100000 |
| 135 | #define SDHCI_INT_DATA_CRC 0x00200000 |
| 136 | #define SDHCI_INT_DATA_END_BIT 0x00400000 |
| 137 | #define SDHCI_INT_BUS_POWER 0x00800000 |
Asutosh Das | 80c0255 | 2013-07-23 16:20:34 +0530 | [diff] [blame] | 138 | #define SDHCI_INT_AUTO_CMD_ERR 0x01000000 |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 139 | #define SDHCI_INT_ADMA_ERROR 0x02000000 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 140 | |
| 141 | #define SDHCI_INT_NORMAL_MASK 0x00007FFF |
| 142 | #define SDHCI_INT_ERROR_MASK 0xFFFF8000 |
| 143 | |
| 144 | #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ |
Asutosh Das | 80c0255 | 2013-07-23 16:20:34 +0530 | [diff] [blame] | 145 | SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX | \ |
| 146 | SDHCI_INT_AUTO_CMD_ERR) |
| 147 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 148 | #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 149 | SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 150 | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ |
Zhangfei Gao | a751a7d69 | 2010-05-26 14:42:02 -0700 | [diff] [blame] | 151 | SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR) |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 152 | #define SDHCI_INT_ALL_MASK ((unsigned int)-1) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 153 | |
Asutosh Das | 80c0255 | 2013-07-23 16:20:34 +0530 | [diff] [blame] | 154 | #define SDHCI_AUTO_CMD_ERR 0x3C |
| 155 | #define SDHCI_AUTO_CMD12_NOT_EXEC 0x0001 |
| 156 | #define SDHCI_AUTO_CMD_TIMEOUT_ERR 0x0002 |
| 157 | #define SDHCI_AUTO_CMD_CRC_ERR 0x0004 |
| 158 | #define SDHCI_AUTO_CMD_ENDBIT_ERR 0x0008 |
| 159 | #define SDHCI_AUTO_CMD_INDEX_ERR 0x0010 |
| 160 | #define SDHCI_AUTO_CMD12_NOT_ISSUED 0x0080 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 161 | |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 162 | #define SDHCI_HOST_CONTROL2 0x3E |
Arindam Nath | 49c468f | 2011-05-05 12:19:01 +0530 | [diff] [blame] | 163 | #define SDHCI_CTRL_UHS_MASK 0x0007 |
| 164 | #define SDHCI_CTRL_UHS_SDR12 0x0000 |
| 165 | #define SDHCI_CTRL_UHS_SDR25 0x0001 |
| 166 | #define SDHCI_CTRL_UHS_SDR50 0x0002 |
| 167 | #define SDHCI_CTRL_UHS_SDR104 0x0003 |
| 168 | #define SDHCI_CTRL_UHS_DDR50 0x0004 |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 169 | #define SDHCI_CTRL_HS_SDR200 0x0005 /* reserved value in SDIO spec */ |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 170 | #define SDHCI_CTRL_VDD_180 0x0008 |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 171 | #define SDHCI_CTRL_DRV_TYPE_MASK 0x0030 |
| 172 | #define SDHCI_CTRL_DRV_TYPE_B 0x0000 |
| 173 | #define SDHCI_CTRL_DRV_TYPE_A 0x0010 |
| 174 | #define SDHCI_CTRL_DRV_TYPE_C 0x0020 |
| 175 | #define SDHCI_CTRL_DRV_TYPE_D 0x0030 |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 176 | #define SDHCI_CTRL_EXEC_TUNING 0x0040 |
| 177 | #define SDHCI_CTRL_TUNED_CLK 0x0080 |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 178 | #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 179 | |
| 180 | #define SDHCI_CAPABILITIES 0x40 |
Pierre Ossman | 1c8cde9 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 181 | #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F |
| 182 | #define SDHCI_TIMEOUT_CLK_SHIFT 0 |
| 183 | #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 184 | #define SDHCI_CLOCK_BASE_MASK 0x00003F00 |
Zhangfei Gao | c4687d5 | 2010-08-20 14:02:36 -0400 | [diff] [blame] | 185 | #define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 186 | #define SDHCI_CLOCK_BASE_SHIFT 8 |
Pierre Ossman | 1d676e0 | 2006-07-02 16:52:10 +0100 | [diff] [blame] | 187 | #define SDHCI_MAX_BLOCK_MASK 0x00030000 |
| 188 | #define SDHCI_MAX_BLOCK_SHIFT 16 |
Philip Rakity | 15ec446 | 2010-11-19 16:48:39 -0500 | [diff] [blame] | 189 | #define SDHCI_CAN_DO_8BIT 0x00040000 |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 190 | #define SDHCI_CAN_DO_ADMA2 0x00080000 |
| 191 | #define SDHCI_CAN_DO_ADMA1 0x00100000 |
Pierre Ossman | 077df88 | 2006-11-08 23:06:35 +0100 | [diff] [blame] | 192 | #define SDHCI_CAN_DO_HISPD 0x00200000 |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 193 | #define SDHCI_CAN_DO_SDMA 0x00400000 |
Pierre Ossman | 146ad66 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 194 | #define SDHCI_CAN_VDD_330 0x01000000 |
| 195 | #define SDHCI_CAN_VDD_300 0x02000000 |
| 196 | #define SDHCI_CAN_VDD_180 0x04000000 |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 197 | #define SDHCI_CAN_64BIT 0x10000000 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 198 | |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 199 | #define SDHCI_SUPPORT_SDR50 0x00000001 |
| 200 | #define SDHCI_SUPPORT_SDR104 0x00000002 |
| 201 | #define SDHCI_SUPPORT_DDR50 0x00000004 |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 202 | #define SDHCI_DRIVER_TYPE_A 0x00000010 |
| 203 | #define SDHCI_DRIVER_TYPE_C 0x00000020 |
| 204 | #define SDHCI_DRIVER_TYPE_D 0x00000040 |
Arindam Nath | cf2b5ee | 2011-05-05 12:19:07 +0530 | [diff] [blame] | 205 | #define SDHCI_RETUNING_TIMER_COUNT_MASK 0x00000F00 |
| 206 | #define SDHCI_RETUNING_TIMER_COUNT_SHIFT 8 |
| 207 | #define SDHCI_USE_SDR50_TUNING 0x00002000 |
| 208 | #define SDHCI_RETUNING_MODE_MASK 0x0000C000 |
| 209 | #define SDHCI_RETUNING_MODE_SHIFT 14 |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 210 | #define SDHCI_CLOCK_MUL_MASK 0x00FF0000 |
| 211 | #define SDHCI_CLOCK_MUL_SHIFT 16 |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 212 | |
Philip Rakity | e8120ad | 2010-11-30 00:55:23 -0500 | [diff] [blame] | 213 | #define SDHCI_CAPABILITIES_1 0x44 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 214 | |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 215 | #define SDHCI_MAX_CURRENT 0x48 |
| 216 | #define SDHCI_MAX_CURRENT_330_MASK 0x0000FF |
| 217 | #define SDHCI_MAX_CURRENT_330_SHIFT 0 |
| 218 | #define SDHCI_MAX_CURRENT_300_MASK 0x00FF00 |
| 219 | #define SDHCI_MAX_CURRENT_300_SHIFT 8 |
| 220 | #define SDHCI_MAX_CURRENT_180_MASK 0xFF0000 |
| 221 | #define SDHCI_MAX_CURRENT_180_SHIFT 16 |
| 222 | #define SDHCI_MAX_CURRENT_MULTIPLIER 4 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 223 | |
| 224 | /* 4C-4F reserved for more max current */ |
| 225 | |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 226 | #define SDHCI_SET_ACMD12_ERROR 0x50 |
| 227 | #define SDHCI_SET_INT_ERROR 0x52 |
| 228 | |
| 229 | #define SDHCI_ADMA_ERROR 0x54 |
| 230 | |
| 231 | /* 55-57 reserved */ |
| 232 | |
| 233 | #define SDHCI_ADMA_ADDRESS 0x58 |
| 234 | |
| 235 | /* 60-FB reserved */ |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 236 | |
| 237 | #define SDHCI_SLOT_INT_STATUS 0xFC |
| 238 | |
| 239 | #define SDHCI_HOST_VERSION 0xFE |
Pierre Ossman | 4a96550 | 2006-06-30 02:22:29 -0700 | [diff] [blame] | 240 | #define SDHCI_VENDOR_VER_MASK 0xFF00 |
| 241 | #define SDHCI_VENDOR_VER_SHIFT 8 |
| 242 | #define SDHCI_SPEC_VER_MASK 0x00FF |
| 243 | #define SDHCI_SPEC_VER_SHIFT 0 |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 244 | #define SDHCI_SPEC_100 0 |
| 245 | #define SDHCI_SPEC_200 1 |
Zhangfei Gao | 85105c5 | 2010-08-06 07:10:01 +0800 | [diff] [blame] | 246 | #define SDHCI_SPEC_300 2 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 247 | |
Zhangfei Gao | 0397526 | 2010-09-20 15:15:18 -0400 | [diff] [blame] | 248 | /* |
| 249 | * End of controller registers. |
| 250 | */ |
| 251 | |
| 252 | #define SDHCI_MAX_DIV_SPEC_200 256 |
| 253 | #define SDHCI_MAX_DIV_SPEC_300 2046 |
| 254 | |
Mikko Vinni | f6a03cb | 2011-04-12 09:36:18 -0400 | [diff] [blame] | 255 | /* |
| 256 | * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2. |
| 257 | */ |
| 258 | #define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024) |
| 259 | #define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12) |
| 260 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 261 | struct sdhci_ops { |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 262 | #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS |
Matt Fleming | dc297c9 | 2010-05-26 14:42:03 -0700 | [diff] [blame] | 263 | u32 (*read_l)(struct sdhci_host *host, int reg); |
| 264 | u16 (*read_w)(struct sdhci_host *host, int reg); |
| 265 | u8 (*read_b)(struct sdhci_host *host, int reg); |
| 266 | void (*write_l)(struct sdhci_host *host, u32 val, int reg); |
| 267 | void (*write_w)(struct sdhci_host *host, u16 val, int reg); |
| 268 | void (*write_b)(struct sdhci_host *host, u8 val, int reg); |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 269 | #endif |
| 270 | |
Anton Vorontsov | 8114634 | 2009-03-17 00:13:59 +0300 | [diff] [blame] | 271 | void (*set_clock)(struct sdhci_host *host, unsigned int clock); |
| 272 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 273 | int (*enable_dma)(struct sdhci_host *host); |
Ben Dooks | 4240ff0 | 2009-03-17 00:13:57 +0300 | [diff] [blame] | 274 | unsigned int (*get_max_clock)(struct sdhci_host *host); |
Anton Vorontsov | a9e58f2 | 2009-07-29 15:04:16 -0700 | [diff] [blame] | 275 | unsigned int (*get_min_clock)(struct sdhci_host *host); |
Ben Dooks | 4240ff0 | 2009-03-17 00:13:57 +0300 | [diff] [blame] | 276 | unsigned int (*get_timeout_clock)(struct sdhci_host *host); |
Philip Rakity | 15ec446 | 2010-11-19 16:48:39 -0500 | [diff] [blame] | 277 | int (*platform_8bit_width)(struct sdhci_host *host, |
| 278 | int width); |
Philip Rakity | 643a81f | 2010-09-23 08:24:32 -0700 | [diff] [blame] | 279 | void (*platform_send_init_74_clocks)(struct sdhci_host *host, |
| 280 | u8 power_mode); |
Wolfram Sang | 2dfb579 | 2010-10-15 12:21:01 +0200 | [diff] [blame] | 281 | unsigned int (*get_ro)(struct sdhci_host *host); |
Philip Rakity | 393c1a3 | 2011-01-21 11:26:40 -0800 | [diff] [blame] | 282 | void (*platform_reset_enter)(struct sdhci_host *host, u8 mask); |
| 283 | void (*platform_reset_exit)(struct sdhci_host *host, u8 mask); |
Philip Rakity | 6322cdd | 2011-05-13 11:17:15 +0530 | [diff] [blame] | 284 | int (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs); |
Adrian Hunter | 20758b6 | 2011-08-29 16:42:12 +0300 | [diff] [blame] | 285 | void (*hw_reset)(struct sdhci_host *host); |
Chris Ball | a1b13b4 | 2012-02-06 00:43:59 -0500 | [diff] [blame] | 286 | void (*platform_suspend)(struct sdhci_host *host); |
| 287 | void (*platform_resume)(struct sdhci_host *host); |
Sahitya Tummala | 179e738 | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 288 | void (*check_power_status)(struct sdhci_host *host, u32 req_type); |
| 289 | #define REQ_BUS_OFF (1 << 0) |
| 290 | #define REQ_BUS_ON (1 << 1) |
| 291 | #define REQ_IO_LOW (1 << 2) |
| 292 | #define REQ_IO_HIGH (1 << 3) |
Asutosh Das | 8ddd348 | 2013-01-04 11:45:46 +0530 | [diff] [blame] | 293 | int (*execute_tuning)(struct sdhci_host *host, u32 opcode); |
Sahitya Tummala | 239e5a8 | 2013-02-25 15:45:32 +0530 | [diff] [blame] | 294 | void (*toggle_cdr)(struct sdhci_host *host, bool enable); |
Asutosh Das | c8e8e56 | 2013-01-10 21:05:49 +0530 | [diff] [blame] | 295 | unsigned int (*get_max_segments)(void); |
Sahitya Tummala | 9f5cbb8 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 296 | void (*platform_bus_voting)(struct sdhci_host *host, u32 enable); |
Konstantin Dorfman | cceca8d | 2013-04-24 15:51:31 +0300 | [diff] [blame] | 297 | void (*disable_data_xfer)(struct sdhci_host *host); |
Asutosh Das | d02c09a | 2013-11-08 12:31:48 +0530 | [diff] [blame] | 298 | int (*enable_controller_clock)(struct sdhci_host *host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 299 | }; |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 300 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 301 | #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS |
| 302 | |
| 303 | static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) |
| 304 | { |
Matt Fleming | dc297c9 | 2010-05-26 14:42:03 -0700 | [diff] [blame] | 305 | if (unlikely(host->ops->write_l)) |
| 306 | host->ops->write_l(host, val, reg); |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 307 | else |
| 308 | writel(val, host->ioaddr + reg); |
| 309 | } |
| 310 | |
| 311 | static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) |
| 312 | { |
Matt Fleming | dc297c9 | 2010-05-26 14:42:03 -0700 | [diff] [blame] | 313 | if (unlikely(host->ops->write_w)) |
| 314 | host->ops->write_w(host, val, reg); |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 315 | else |
| 316 | writew(val, host->ioaddr + reg); |
| 317 | } |
| 318 | |
| 319 | static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) |
| 320 | { |
Matt Fleming | dc297c9 | 2010-05-26 14:42:03 -0700 | [diff] [blame] | 321 | if (unlikely(host->ops->write_b)) |
| 322 | host->ops->write_b(host, val, reg); |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 323 | else |
| 324 | writeb(val, host->ioaddr + reg); |
| 325 | } |
| 326 | |
| 327 | static inline u32 sdhci_readl(struct sdhci_host *host, int reg) |
| 328 | { |
Matt Fleming | dc297c9 | 2010-05-26 14:42:03 -0700 | [diff] [blame] | 329 | if (unlikely(host->ops->read_l)) |
| 330 | return host->ops->read_l(host, reg); |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 331 | else |
| 332 | return readl(host->ioaddr + reg); |
| 333 | } |
| 334 | |
| 335 | static inline u16 sdhci_readw(struct sdhci_host *host, int reg) |
| 336 | { |
Matt Fleming | dc297c9 | 2010-05-26 14:42:03 -0700 | [diff] [blame] | 337 | if (unlikely(host->ops->read_w)) |
| 338 | return host->ops->read_w(host, reg); |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 339 | else |
| 340 | return readw(host->ioaddr + reg); |
| 341 | } |
| 342 | |
| 343 | static inline u8 sdhci_readb(struct sdhci_host *host, int reg) |
| 344 | { |
Matt Fleming | dc297c9 | 2010-05-26 14:42:03 -0700 | [diff] [blame] | 345 | if (unlikely(host->ops->read_b)) |
| 346 | return host->ops->read_b(host, reg); |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 347 | else |
| 348 | return readb(host->ioaddr + reg); |
| 349 | } |
| 350 | |
| 351 | #else |
| 352 | |
| 353 | static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) |
| 354 | { |
| 355 | writel(val, host->ioaddr + reg); |
| 356 | } |
| 357 | |
| 358 | static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) |
| 359 | { |
| 360 | writew(val, host->ioaddr + reg); |
| 361 | } |
| 362 | |
| 363 | static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) |
| 364 | { |
| 365 | writeb(val, host->ioaddr + reg); |
| 366 | } |
| 367 | |
| 368 | static inline u32 sdhci_readl(struct sdhci_host *host, int reg) |
| 369 | { |
| 370 | return readl(host->ioaddr + reg); |
| 371 | } |
| 372 | |
| 373 | static inline u16 sdhci_readw(struct sdhci_host *host, int reg) |
| 374 | { |
| 375 | return readw(host->ioaddr + reg); |
| 376 | } |
| 377 | |
| 378 | static inline u8 sdhci_readb(struct sdhci_host *host, int reg) |
| 379 | { |
| 380 | return readb(host->ioaddr + reg); |
| 381 | } |
| 382 | |
| 383 | #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */ |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 384 | |
| 385 | extern struct sdhci_host *sdhci_alloc_host(struct device *dev, |
| 386 | size_t priv_size); |
| 387 | extern void sdhci_free_host(struct sdhci_host *host); |
| 388 | |
| 389 | static inline void *sdhci_priv(struct sdhci_host *host) |
| 390 | { |
| 391 | return (void *)host->private; |
| 392 | } |
| 393 | |
Marek Szyprowski | 17866e1 | 2010-08-10 18:01:58 -0700 | [diff] [blame] | 394 | extern void sdhci_card_detect(struct sdhci_host *host); |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 395 | extern int sdhci_add_host(struct sdhci_host *host); |
Pierre Ossman | 1e72859 | 2008-04-16 19:13:13 +0200 | [diff] [blame] | 396 | extern void sdhci_remove_host(struct sdhci_host *host, int dead); |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 397 | |
| 398 | #ifdef CONFIG_PM |
Manuel Lauss | 29495aa | 2011-11-03 11:09:45 +0100 | [diff] [blame] | 399 | extern int sdhci_suspend_host(struct sdhci_host *host); |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 400 | extern int sdhci_resume_host(struct sdhci_host *host); |
Daniel Drake | 5f61970 | 2010-11-04 22:20:39 +0000 | [diff] [blame] | 401 | extern void sdhci_enable_irq_wakeups(struct sdhci_host *host); |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 402 | #endif |
Albert Herranz | c0bba0d | 2009-12-17 15:27:19 -0800 | [diff] [blame] | 403 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 404 | #ifdef CONFIG_PM_RUNTIME |
| 405 | extern int sdhci_runtime_suspend_host(struct sdhci_host *host); |
| 406 | extern int sdhci_runtime_resume_host(struct sdhci_host *host); |
| 407 | #endif |
| 408 | |
Giuseppe Cavallaro | 1978fda | 2010-09-28 10:41:29 +0200 | [diff] [blame] | 409 | #endif /* __SDHCI_HW_H */ |