Xiaozhe Shi | 72a72f2 | 2013-12-26 13:54:29 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2011-2014, The Linux Foundation. All rights reserved. |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
Xiaozhe Shi | 73a6569 | 2012-09-18 17:51:57 -0700 | [diff] [blame] | 13 | #define pr_fmt(fmt) "BMS: %s: " fmt, __func__ |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 14 | |
| 15 | #include <linux/module.h> |
| 16 | #include <linux/types.h> |
| 17 | #include <linux/init.h> |
| 18 | #include <linux/slab.h> |
| 19 | #include <linux/err.h> |
| 20 | #include <linux/of.h> |
| 21 | #include <linux/of_device.h> |
| 22 | #include <linux/power_supply.h> |
| 23 | #include <linux/spmi.h> |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 24 | #include <linux/rtc.h> |
Xiaozhe Shi | 7edde5d | 2012-09-26 11:23:09 -0700 | [diff] [blame] | 25 | #include <linux/delay.h> |
Xiaozhe Shi | 2737582 | 2013-08-22 11:40:15 -0700 | [diff] [blame] | 26 | #include <linux/sched.h> |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 27 | #include <linux/qpnp/qpnp-adc.h> |
Xiaozhe Shi | 77ec38d | 2013-04-29 16:41:58 -0700 | [diff] [blame] | 28 | #include <linux/qpnp/power-on.h> |
Xiaozhe Shi | af203c2 | 2013-06-19 12:01:38 -0700 | [diff] [blame] | 29 | #include <linux/of_batterydata.h> |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 30 | |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 31 | /* BMS Register Offsets */ |
Abhijeet Dharmapurikar | 604461d | 2013-07-09 13:34:33 -0700 | [diff] [blame] | 32 | #define REVISION1 0x0 |
| 33 | #define REVISION2 0x1 |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 34 | #define BMS1_STATUS1 0x8 |
| 35 | #define BMS1_MODE_CTL 0X40 |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 36 | /* Coulomb counter clear registers */ |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 37 | #define BMS1_CC_DATA_CTL 0x42 |
Xiaozhe Shi | a045a56 | 2012-11-28 16:55:39 -0800 | [diff] [blame] | 38 | #define BMS1_CC_CLEAR_CTL 0x43 |
Xiaozhe Shi | 20640b5 | 2013-01-03 11:49:30 -0800 | [diff] [blame] | 39 | /* BMS Tolerances */ |
| 40 | #define BMS1_TOL_CTL 0X44 |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 41 | /* OCV limit registers */ |
| 42 | #define BMS1_OCV_USE_LOW_LIMIT_THR0 0x48 |
| 43 | #define BMS1_OCV_USE_LOW_LIMIT_THR1 0x49 |
| 44 | #define BMS1_OCV_USE_HIGH_LIMIT_THR0 0x4A |
| 45 | #define BMS1_OCV_USE_HIGH_LIMIT_THR1 0x4B |
| 46 | #define BMS1_OCV_USE_LIMIT_CTL 0x4C |
Xiaozhe Shi | 7edde5d | 2012-09-26 11:23:09 -0700 | [diff] [blame] | 47 | /* Delay control */ |
| 48 | #define BMS1_S1_DELAY_CTL 0x5A |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 49 | /* OCV interrupt threshold */ |
| 50 | #define BMS1_OCV_THR0 0x50 |
Abhijeet Dharmapurikar | 84b13dd | 2013-07-08 18:43:56 -0700 | [diff] [blame] | 51 | #define BMS1_S2_SAMP_AVG_CTL 0x61 |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 52 | /* SW CC interrupt threshold */ |
| 53 | #define BMS1_SW_CC_THR0 0xA0 |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 54 | /* OCV for r registers */ |
| 55 | #define BMS1_OCV_FOR_R_DATA0 0x80 |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 56 | #define BMS1_VSENSE_FOR_R_DATA0 0x82 |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 57 | /* Coulomb counter data */ |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 58 | #define BMS1_CC_DATA0 0x8A |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 59 | /* Shadow Coulomb counter data */ |
| 60 | #define BMS1_SW_CC_DATA0 0xA8 |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 61 | /* OCV for soc data */ |
| 62 | #define BMS1_OCV_FOR_SOC_DATA0 0x90 |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 63 | #define BMS1_VSENSE_PON_DATA0 0x94 |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 64 | #define BMS1_VSENSE_AVG_DATA0 0x98 |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 65 | #define BMS1_VBAT_AVG_DATA0 0x9E |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 66 | /* Extra bms registers */ |
Xiaozhe Shi | 5705894 | 2013-03-27 16:54:54 -0700 | [diff] [blame] | 67 | #define SOC_STORAGE_REG 0xB0 |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 68 | #define IAVG_STORAGE_REG 0xB1 |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 69 | #define BMS_FCC_COUNT 0xB2 |
| 70 | #define BMS_FCC_BASE_REG 0xB3 /* FCC updates - 0xB3 to 0xB7 */ |
| 71 | #define BMS_CHGCYL_BASE_REG 0xB8 /* FCC chgcyl - 0xB8 to 0xBC */ |
| 72 | #define CHARGE_INCREASE_STORAGE 0xBD |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 73 | #define CHARGE_CYCLE_STORAGE_LSB 0xBE /* LSB=0xBE, MSB=0xBF */ |
| 74 | |
Xiaozhe Shi | c40b397 | 2012-11-30 14:11:16 -0800 | [diff] [blame] | 75 | /* IADC Channel Select */ |
Abhijeet Dharmapurikar | 84b13dd | 2013-07-08 18:43:56 -0700 | [diff] [blame] | 76 | #define IADC1_BMS_REVISION2 0x01 |
Xiaozhe Shi | c40b397 | 2012-11-30 14:11:16 -0800 | [diff] [blame] | 77 | #define IADC1_BMS_ADC_CH_SEL_CTL 0x48 |
Abhijeet Dharmapurikar | 604461d | 2013-07-09 13:34:33 -0700 | [diff] [blame] | 78 | #define IADC1_BMS_ADC_INT_RSNSN_CTL 0x49 |
| 79 | #define IADC1_BMS_FAST_AVG_EN 0x5B |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 80 | |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 81 | /* Configuration for saving of shutdown soc/iavg */ |
| 82 | #define IGNORE_SOC_TEMP_DECIDEG 50 |
Xiaozhe Shi | 68a1bb2 | 2013-09-23 14:52:00 -0700 | [diff] [blame] | 83 | #define IAVG_STEP_SIZE_MA 10 |
Xiaozhe Shi | f5f966d | 2013-02-19 14:23:11 -0800 | [diff] [blame] | 84 | #define IAVG_INVALID 0xFF |
Xiaozhe Shi | f9f9924 | 2013-08-29 12:27:50 -0700 | [diff] [blame] | 85 | #define SOC_INVALID 0x7E |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 86 | |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 87 | #define IAVG_SAMPLES 16 |
| 88 | |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 89 | /* FCC learning constants */ |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 90 | #define MAX_FCC_CYCLES 5 |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 91 | #define DELTA_FCC_PERCENT 5 |
| 92 | #define VALID_FCC_CHGCYL_RANGE 50 |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 93 | #define CHGCYL_RESOLUTION 20 |
| 94 | #define FCC_DEFAULT_TEMP 250 |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 95 | |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 96 | #define QPNP_BMS_DEV_NAME "qcom,qpnp-bms" |
| 97 | |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 98 | enum { |
| 99 | SHDW_CC, |
| 100 | CC |
| 101 | }; |
| 102 | |
| 103 | enum { |
| 104 | NORESET, |
| 105 | RESET |
| 106 | }; |
| 107 | |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 108 | struct soc_params { |
| 109 | int fcc_uah; |
| 110 | int cc_uah; |
Xiaozhe Shi | 904f1f7 | 2012-12-04 12:47:21 -0800 | [diff] [blame] | 111 | int rbatt_mohm; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 112 | int iavg_ua; |
| 113 | int uuc_uah; |
| 114 | int ocv_charge_uah; |
Xiaozhe Shi | f36d286 | 2013-01-04 10:17:35 -0800 | [diff] [blame] | 115 | int delta_time_s; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 116 | }; |
| 117 | |
| 118 | struct raw_soc_params { |
| 119 | uint16_t last_good_ocv_raw; |
| 120 | int64_t cc; |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 121 | int64_t shdw_cc; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 122 | int last_good_ocv_uv; |
| 123 | }; |
| 124 | |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 125 | struct fcc_sample { |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 126 | int fcc_new; |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 127 | int chargecycles; |
| 128 | }; |
| 129 | |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 130 | struct bms_irq { |
| 131 | unsigned int irq; |
| 132 | unsigned long disabled; |
Xiaozhe Shi | f511a6e | 2014-02-20 14:37:18 -0800 | [diff] [blame] | 133 | bool ready; |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 134 | }; |
| 135 | |
| 136 | struct bms_wakeup_source { |
| 137 | struct wakeup_source source; |
| 138 | unsigned long disabled; |
| 139 | }; |
| 140 | |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 141 | struct qpnp_bms_chip { |
| 142 | struct device *dev; |
| 143 | struct power_supply bms_psy; |
Abhijeet Dharmapurikar | 8e32249 | 2013-06-25 19:48:18 -0700 | [diff] [blame] | 144 | bool bms_psy_registered; |
Xiaozhe Shi | 7edde5d | 2012-09-26 11:23:09 -0700 | [diff] [blame] | 145 | struct power_supply *batt_psy; |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 146 | struct spmi_device *spmi; |
Xiaozhe Shi | 2737582 | 2013-08-22 11:40:15 -0700 | [diff] [blame] | 147 | wait_queue_head_t bms_wait_queue; |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 148 | u16 base; |
Xiaozhe Shi | c40b397 | 2012-11-30 14:11:16 -0800 | [diff] [blame] | 149 | u16 iadc_base; |
Xiaozhe Shi | 7c41a29 | 2013-08-16 16:50:17 -0700 | [diff] [blame] | 150 | u16 batt_pres_addr; |
Xiaozhe Shi | 12b25be | 2013-08-29 11:51:59 -0700 | [diff] [blame] | 151 | u16 soc_storage_addr; |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 152 | |
| 153 | u8 revision1; |
| 154 | u8 revision2; |
Abhijeet Dharmapurikar | 604461d | 2013-07-09 13:34:33 -0700 | [diff] [blame] | 155 | |
| 156 | u8 iadc_bms_revision1; |
| 157 | u8 iadc_bms_revision2; |
| 158 | |
Xiaozhe Shi | d5d2141 | 2013-02-06 17:14:41 -0800 | [diff] [blame] | 159 | int battery_present; |
Xiaozhe Shi | 890fbf4 | 2013-05-02 16:42:53 -0700 | [diff] [blame] | 160 | int battery_status; |
Abhijeet Dharmapurikar | 84b13dd | 2013-07-08 18:43:56 -0700 | [diff] [blame] | 161 | bool batfet_closed; |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 162 | bool new_battery; |
Xiaozhe Shi | 890fbf4 | 2013-05-02 16:42:53 -0700 | [diff] [blame] | 163 | bool done_charging; |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 164 | bool last_soc_invalid; |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 165 | /* platform data */ |
Abhijeet Dharmapurikar | eef8866 | 2012-11-08 17:26:29 -0800 | [diff] [blame] | 166 | int r_sense_uohm; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 167 | unsigned int v_cutoff_uv; |
Abhijeet Dharmapurikar | eef8866 | 2012-11-08 17:26:29 -0800 | [diff] [blame] | 168 | int max_voltage_uv; |
| 169 | int r_conn_mohm; |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 170 | int shutdown_soc_valid_limit; |
| 171 | int adjust_soc_low_threshold; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 172 | int chg_term_ua; |
Xiaozhe Shi | 73a6569 | 2012-09-18 17:51:57 -0700 | [diff] [blame] | 173 | enum battery_type batt_type; |
Xiaozhe Shi | 976618f | 2013-04-30 10:49:30 -0700 | [diff] [blame] | 174 | unsigned int fcc_mah; |
Xiaozhe Shi | 73a6569 | 2012-09-18 17:51:57 -0700 | [diff] [blame] | 175 | struct single_row_lut *fcc_temp_lut; |
| 176 | struct single_row_lut *fcc_sf_lut; |
| 177 | struct pc_temp_ocv_lut *pc_temp_ocv_lut; |
| 178 | struct sf_lut *pc_sf_lut; |
| 179 | struct sf_lut *rbatt_sf_lut; |
| 180 | int default_rbatt_mohm; |
Xiaozhe Shi | 1a10aff | 2013-04-01 15:40:05 -0700 | [diff] [blame] | 181 | int rbatt_capacitive_mohm; |
Xiaozhe Shi | 6dc56f1 | 2013-05-02 15:56:55 -0700 | [diff] [blame] | 182 | int rbatt_mohm; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 183 | |
| 184 | struct delayed_work calculate_soc_delayed_work; |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 185 | struct work_struct recalc_work; |
Abhijeet Dharmapurikar | 84b13dd | 2013-07-08 18:43:56 -0700 | [diff] [blame] | 186 | struct work_struct batfet_open_work; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 187 | |
| 188 | struct mutex bms_output_lock; |
| 189 | struct mutex last_ocv_uv_mutex; |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 190 | struct mutex vbat_monitor_mutex; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 191 | struct mutex soc_invalidation_mutex; |
Xiaozhe Shi | 04da099 | 2013-04-26 16:32:14 -0700 | [diff] [blame] | 192 | struct mutex last_soc_mutex; |
Xiaozhe Shi | bda8499 | 2013-09-05 10:39:11 -0700 | [diff] [blame] | 193 | struct mutex status_lock; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 194 | |
Xiaozhe Shi | c40b397 | 2012-11-30 14:11:16 -0800 | [diff] [blame] | 195 | bool use_external_rsense; |
Xiaozhe Shi | bdf1474 | 2012-12-05 12:41:48 -0800 | [diff] [blame] | 196 | bool use_ocv_thresholds; |
Xiaozhe Shi | c40b397 | 2012-11-30 14:11:16 -0800 | [diff] [blame] | 197 | |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 198 | bool ignore_shutdown_soc; |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 199 | bool shutdown_soc_invalid; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 200 | int shutdown_soc; |
| 201 | int shutdown_iavg_ma; |
| 202 | |
Xiaozhe Shi | 4be8578 | 2013-02-22 17:33:40 -0800 | [diff] [blame] | 203 | struct wake_lock low_voltage_wake_lock; |
Xiaozhe Shi | 4be8578 | 2013-02-22 17:33:40 -0800 | [diff] [blame] | 204 | int low_voltage_threshold; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 205 | int low_soc_calc_threshold; |
| 206 | int low_soc_calculate_soc_ms; |
Xiaozhe Shi | cb487b1 | 2013-10-14 17:42:07 -0700 | [diff] [blame] | 207 | int low_voltage_calculate_soc_ms; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 208 | int calculate_soc_ms; |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 209 | struct bms_wakeup_source soc_wake_source; |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 210 | struct wake_lock cv_wake_lock; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 211 | |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 212 | uint16_t ocv_reading_at_100; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 213 | uint16_t prev_last_good_ocv_raw; |
Xiaozhe Shi | 24f91a0 | 2013-08-29 17:15:05 -0700 | [diff] [blame] | 214 | int insertion_ocv_uv; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 215 | int last_ocv_uv; |
Xiaozhe Shi | cc48e99 | 2013-05-28 16:42:24 -0700 | [diff] [blame] | 216 | int charging_adjusted_ocv; |
Abhijeet Dharmapurikar | 4b97cdd | 2012-12-26 21:10:53 -0800 | [diff] [blame] | 217 | int last_ocv_temp; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 218 | int last_cc_uah; |
Xiaozhe Shi | 04da099 | 2013-04-26 16:32:14 -0700 | [diff] [blame] | 219 | unsigned long last_soc_change_sec; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 220 | unsigned long tm_sec; |
Xiaozhe Shi | 04da099 | 2013-04-26 16:32:14 -0700 | [diff] [blame] | 221 | unsigned long report_tm_sec; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 222 | bool first_time_calc_soc; |
| 223 | bool first_time_calc_uuc; |
Xiaozhe Shi | 80ba88d | 2013-04-05 10:23:34 -0700 | [diff] [blame] | 224 | int64_t software_cc_uah; |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 225 | int64_t software_shdw_cc_uah; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 226 | |
| 227 | int iavg_samples_ma[IAVG_SAMPLES]; |
| 228 | int iavg_index; |
| 229 | int iavg_num_samples; |
| 230 | struct timespec t_soc_queried; |
| 231 | int last_soc; |
Xiaozhe Shi | 7edde5d | 2012-09-26 11:23:09 -0700 | [diff] [blame] | 232 | int last_soc_est; |
Xiaozhe Shi | cc13726 | 2013-03-10 06:21:41 -0700 | [diff] [blame] | 233 | int last_soc_unbound; |
Xiaozhe Shi | 04da099 | 2013-04-26 16:32:14 -0700 | [diff] [blame] | 234 | bool was_charging_at_sleep; |
| 235 | int charge_start_tm_sec; |
| 236 | int catch_up_time_sec; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 237 | struct single_row_lut *adjusted_fcc_temp_lut; |
| 238 | |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 239 | struct qpnp_adc_tm_btm_param vbat_monitor_params; |
Xiaozhe Shi | 535494d | 2013-04-05 12:27:51 -0700 | [diff] [blame] | 240 | struct qpnp_adc_tm_btm_param die_temp_monitor_params; |
| 241 | int temperature_margin; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 242 | unsigned int vadc_v0625; |
| 243 | unsigned int vadc_v1250; |
| 244 | |
Xiaozhe Shi | ee39e5d | 2013-10-07 13:56:04 -0700 | [diff] [blame] | 245 | int system_load_count; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 246 | int prev_uuc_iavg_ma; |
| 247 | int prev_pc_unusable; |
| 248 | int ibat_at_cv_ua; |
| 249 | int soc_at_cv; |
| 250 | int prev_chg_soc; |
| 251 | int calculated_soc; |
Xiaozhe Shi | 79d6c1d | 2012-11-26 13:19:50 -0800 | [diff] [blame] | 252 | int prev_voltage_based_soc; |
| 253 | bool use_voltage_soc; |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 254 | bool in_cv_range; |
Xiaozhe Shi | bdf1474 | 2012-12-05 12:41:48 -0800 | [diff] [blame] | 255 | |
Xiaozhe Shi | fc2f5a0 | 2013-01-28 15:09:04 -0800 | [diff] [blame] | 256 | int prev_batt_terminal_uv; |
Xiaozhe Shi | 0ac7a00 | 2013-03-26 13:14:03 -0700 | [diff] [blame] | 257 | int high_ocv_correction_limit_uv; |
| 258 | int low_ocv_correction_limit_uv; |
| 259 | int flat_ocv_threshold_uv; |
| 260 | int hold_soc_est; |
Xiaozhe Shi | fc2f5a0 | 2013-01-28 15:09:04 -0800 | [diff] [blame] | 261 | |
Xiaozhe Shi | bdf1474 | 2012-12-05 12:41:48 -0800 | [diff] [blame] | 262 | int ocv_high_threshold_uv; |
| 263 | int ocv_low_threshold_uv; |
Xiaozhe Shi | cdeee31 | 2012-12-18 15:10:18 -0800 | [diff] [blame] | 264 | unsigned long last_recalc_time; |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 265 | |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 266 | struct fcc_sample *fcc_learning_samples; |
| 267 | u8 fcc_sample_count; |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 268 | int enable_fcc_learning; |
| 269 | int min_fcc_learning_soc; |
| 270 | int min_fcc_ocv_pc; |
| 271 | int min_fcc_learning_samples; |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 272 | int start_soc; |
| 273 | int end_soc; |
| 274 | int start_pc; |
| 275 | int start_cc_uah; |
| 276 | int start_real_soc; |
| 277 | int end_cc_uah; |
| 278 | uint16_t fcc_new_mah; |
| 279 | int fcc_new_batt_temp; |
| 280 | uint16_t charge_cycles; |
| 281 | u8 charge_increase; |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 282 | int fcc_resolution; |
| 283 | bool battery_removed; |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 284 | struct bms_irq sw_cc_thr_irq; |
| 285 | struct bms_irq ocv_thr_irq; |
Siddartha Mohanadoss | 3cb2b6b | 2013-06-21 12:07:05 -0700 | [diff] [blame] | 286 | struct qpnp_vadc_chip *vadc_dev; |
Siddartha Mohanadoss | 55d0bca | 2013-06-24 08:29:34 -0700 | [diff] [blame] | 287 | struct qpnp_iadc_chip *iadc_dev; |
Siddartha Mohanadoss | 88a3fde | 2013-06-24 16:18:52 -0700 | [diff] [blame] | 288 | struct qpnp_adc_tm_chip *adc_tm_dev; |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 289 | }; |
| 290 | |
| 291 | static struct of_device_id qpnp_bms_match_table[] = { |
| 292 | { .compatible = QPNP_BMS_DEV_NAME }, |
| 293 | {} |
| 294 | }; |
| 295 | |
| 296 | static char *qpnp_bms_supplicants[] = { |
| 297 | "battery" |
| 298 | }; |
| 299 | |
| 300 | static enum power_supply_property msm_bms_power_props[] = { |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 301 | POWER_SUPPLY_PROP_CAPACITY, |
Xiaozhe Shi | bda8499 | 2013-09-05 10:39:11 -0700 | [diff] [blame] | 302 | POWER_SUPPLY_PROP_STATUS, |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 303 | POWER_SUPPLY_PROP_CURRENT_NOW, |
Xiaozhe Shi | 6dc56f1 | 2013-05-02 15:56:55 -0700 | [diff] [blame] | 304 | POWER_SUPPLY_PROP_RESISTANCE, |
Xiaozhe Shi | fb37f3b | 2013-05-20 16:56:19 -0700 | [diff] [blame] | 305 | POWER_SUPPLY_PROP_CHARGE_COUNTER, |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 306 | POWER_SUPPLY_PROP_CHARGE_COUNTER_SHADOW, |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 307 | POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN, |
Anirudh Ghayal | c9d981a | 2013-06-24 09:50:33 +0530 | [diff] [blame] | 308 | POWER_SUPPLY_PROP_CHARGE_FULL, |
Anirudh Ghayal | 9dd582d | 2013-06-07 17:48:58 +0530 | [diff] [blame] | 309 | POWER_SUPPLY_PROP_CYCLE_COUNT, |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 310 | }; |
| 311 | |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 312 | static int discard_backup_fcc_data(struct qpnp_bms_chip *chip); |
| 313 | static void backup_charge_cycle(struct qpnp_bms_chip *chip); |
| 314 | |
Xiaozhe Shi | 20640b5 | 2013-01-03 11:49:30 -0800 | [diff] [blame] | 315 | static bool bms_reset; |
Xiaozhe Shi | 781b0a2 | 2012-11-05 17:18:27 -0800 | [diff] [blame] | 316 | |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 317 | static int qpnp_read_wrapper(struct qpnp_bms_chip *chip, u8 *val, |
| 318 | u16 base, int count) |
| 319 | { |
| 320 | int rc; |
| 321 | struct spmi_device *spmi = chip->spmi; |
| 322 | |
| 323 | rc = spmi_ext_register_readl(spmi->ctrl, spmi->sid, base, val, count); |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 324 | if (rc) { |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 325 | pr_err("SPMI read failed rc=%d\n", rc); |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 326 | return rc; |
| 327 | } |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 328 | return 0; |
| 329 | } |
| 330 | |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 331 | static int qpnp_write_wrapper(struct qpnp_bms_chip *chip, u8 *val, |
| 332 | u16 base, int count) |
| 333 | { |
| 334 | int rc; |
| 335 | struct spmi_device *spmi = chip->spmi; |
| 336 | |
| 337 | rc = spmi_ext_register_writel(spmi->ctrl, spmi->sid, base, val, count); |
| 338 | if (rc) { |
| 339 | pr_err("SPMI write failed rc=%d\n", rc); |
| 340 | return rc; |
| 341 | } |
| 342 | return 0; |
| 343 | } |
| 344 | |
Xiaozhe Shi | dffbe69 | 2012-12-11 15:35:46 -0800 | [diff] [blame] | 345 | static int qpnp_masked_write_base(struct qpnp_bms_chip *chip, u16 addr, |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 346 | u8 mask, u8 val) |
| 347 | { |
| 348 | int rc; |
| 349 | u8 reg; |
| 350 | |
Xiaozhe Shi | dffbe69 | 2012-12-11 15:35:46 -0800 | [diff] [blame] | 351 | rc = qpnp_read_wrapper(chip, ®, addr, 1); |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 352 | if (rc) { |
Xiaozhe Shi | dffbe69 | 2012-12-11 15:35:46 -0800 | [diff] [blame] | 353 | pr_err("read failed addr = %03X, rc = %d\n", addr, rc); |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 354 | return rc; |
| 355 | } |
| 356 | reg &= ~mask; |
| 357 | reg |= val & mask; |
Xiaozhe Shi | dffbe69 | 2012-12-11 15:35:46 -0800 | [diff] [blame] | 358 | rc = qpnp_write_wrapper(chip, ®, addr, 1); |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 359 | if (rc) { |
| 360 | pr_err("write failed addr = %03X, val = %02x, mask = %02x, reg = %02x, rc = %d\n", |
Xiaozhe Shi | dffbe69 | 2012-12-11 15:35:46 -0800 | [diff] [blame] | 361 | addr, val, mask, reg, rc); |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 362 | return rc; |
| 363 | } |
| 364 | return 0; |
| 365 | } |
| 366 | |
Xiaozhe Shi | dffbe69 | 2012-12-11 15:35:46 -0800 | [diff] [blame] | 367 | static int qpnp_masked_write_iadc(struct qpnp_bms_chip *chip, u16 addr, |
| 368 | u8 mask, u8 val) |
| 369 | { |
| 370 | return qpnp_masked_write_base(chip, chip->iadc_base + addr, mask, val); |
| 371 | } |
| 372 | |
| 373 | static int qpnp_masked_write(struct qpnp_bms_chip *chip, u16 addr, |
| 374 | u8 mask, u8 val) |
| 375 | { |
| 376 | return qpnp_masked_write_base(chip, chip->base + addr, mask, val); |
| 377 | } |
| 378 | |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 379 | static void bms_stay_awake(struct bms_wakeup_source *source) |
| 380 | { |
| 381 | if (__test_and_clear_bit(0, &source->disabled)) { |
| 382 | __pm_stay_awake(&source->source); |
| 383 | pr_debug("enabled source %s\n", source->source.name); |
| 384 | } |
| 385 | } |
| 386 | |
| 387 | static void bms_relax(struct bms_wakeup_source *source) |
| 388 | { |
| 389 | if (!__test_and_set_bit(0, &source->disabled)) { |
| 390 | __pm_relax(&source->source); |
| 391 | pr_debug("disabled source %s\n", source->source.name); |
| 392 | } |
| 393 | } |
| 394 | |
| 395 | static void enable_bms_irq(struct bms_irq *irq) |
| 396 | { |
Xiaozhe Shi | f511a6e | 2014-02-20 14:37:18 -0800 | [diff] [blame] | 397 | if (irq->ready && __test_and_clear_bit(0, &irq->disabled)) { |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 398 | enable_irq(irq->irq); |
| 399 | pr_debug("enabled irq %d\n", irq->irq); |
| 400 | } |
| 401 | } |
| 402 | |
| 403 | static void disable_bms_irq(struct bms_irq *irq) |
| 404 | { |
Xiaozhe Shi | f511a6e | 2014-02-20 14:37:18 -0800 | [diff] [blame] | 405 | if (irq->ready && !__test_and_set_bit(0, &irq->disabled)) { |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 406 | disable_irq(irq->irq); |
| 407 | pr_debug("disabled irq %d\n", irq->irq); |
| 408 | } |
| 409 | } |
| 410 | |
Anirudh Ghayal | 1166eef | 2013-12-23 19:05:33 +0530 | [diff] [blame] | 411 | static void disable_bms_irq_nosync(struct bms_irq *irq) |
| 412 | { |
Xiaozhe Shi | f511a6e | 2014-02-20 14:37:18 -0800 | [diff] [blame] | 413 | if (irq->ready && !__test_and_set_bit(0, &irq->disabled)) { |
Anirudh Ghayal | 1166eef | 2013-12-23 19:05:33 +0530 | [diff] [blame] | 414 | disable_irq_nosync(irq->irq); |
| 415 | pr_debug("disabled irq %d\n", irq->irq); |
| 416 | } |
| 417 | } |
| 418 | |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 419 | #define HOLD_OREG_DATA BIT(0) |
| 420 | static int lock_output_data(struct qpnp_bms_chip *chip) |
| 421 | { |
| 422 | int rc; |
| 423 | |
| 424 | rc = qpnp_masked_write(chip, BMS1_CC_DATA_CTL, |
| 425 | HOLD_OREG_DATA, HOLD_OREG_DATA); |
| 426 | if (rc) { |
| 427 | pr_err("couldnt lock bms output rc = %d\n", rc); |
| 428 | return rc; |
| 429 | } |
| 430 | return 0; |
| 431 | } |
| 432 | |
| 433 | static int unlock_output_data(struct qpnp_bms_chip *chip) |
| 434 | { |
| 435 | int rc; |
| 436 | |
| 437 | rc = qpnp_masked_write(chip, BMS1_CC_DATA_CTL, HOLD_OREG_DATA, 0); |
| 438 | if (rc) { |
| 439 | pr_err("fail to unlock BMS_CONTROL rc = %d\n", rc); |
| 440 | return rc; |
| 441 | } |
| 442 | return 0; |
| 443 | } |
| 444 | |
| 445 | #define V_PER_BIT_MUL_FACTOR 97656 |
| 446 | #define V_PER_BIT_DIV_FACTOR 1000 |
| 447 | #define VADC_INTRINSIC_OFFSET 0x6000 |
| 448 | |
Xiaozhe Shi | bdf1474 | 2012-12-05 12:41:48 -0800 | [diff] [blame] | 449 | static int vadc_reading_to_uv(int reading) |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 450 | { |
| 451 | if (reading <= VADC_INTRINSIC_OFFSET) |
| 452 | return 0; |
| 453 | |
| 454 | return (reading - VADC_INTRINSIC_OFFSET) |
| 455 | * V_PER_BIT_MUL_FACTOR / V_PER_BIT_DIV_FACTOR; |
| 456 | } |
| 457 | |
| 458 | #define VADC_CALIB_UV 625000 |
| 459 | #define VBATT_MUL_FACTOR 3 |
Xiaozhe Shi | bdf1474 | 2012-12-05 12:41:48 -0800 | [diff] [blame] | 460 | static int adjust_vbatt_reading(struct qpnp_bms_chip *chip, int reading_uv) |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 461 | { |
| 462 | s64 numerator, denominator; |
| 463 | |
| 464 | if (reading_uv == 0) |
| 465 | return 0; |
| 466 | |
| 467 | /* don't adjust if not calibrated */ |
| 468 | if (chip->vadc_v0625 == 0 || chip->vadc_v1250 == 0) { |
| 469 | pr_debug("No cal yet return %d\n", |
| 470 | VBATT_MUL_FACTOR * reading_uv); |
| 471 | return VBATT_MUL_FACTOR * reading_uv; |
| 472 | } |
| 473 | |
Xiaozhe Shi | 4e37665 | 2012-10-25 12:38:50 -0700 | [diff] [blame] | 474 | numerator = ((s64)reading_uv - chip->vadc_v0625) * VADC_CALIB_UV; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 475 | denominator = (s64)chip->vadc_v1250 - chip->vadc_v0625; |
| 476 | if (denominator == 0) |
| 477 | return reading_uv * VBATT_MUL_FACTOR; |
| 478 | return (VADC_CALIB_UV + div_s64(numerator, denominator)) |
| 479 | * VBATT_MUL_FACTOR; |
| 480 | } |
| 481 | |
Xiaozhe Shi | bdf1474 | 2012-12-05 12:41:48 -0800 | [diff] [blame] | 482 | static int convert_vbatt_uv_to_raw(struct qpnp_bms_chip *chip, |
| 483 | int unadjusted_vbatt) |
| 484 | { |
| 485 | int scaled_vbatt = unadjusted_vbatt / VBATT_MUL_FACTOR; |
| 486 | |
| 487 | if (scaled_vbatt <= 0) |
| 488 | return VADC_INTRINSIC_OFFSET; |
| 489 | return ((scaled_vbatt * V_PER_BIT_DIV_FACTOR) / V_PER_BIT_MUL_FACTOR) |
| 490 | + VADC_INTRINSIC_OFFSET; |
| 491 | } |
| 492 | |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 493 | static inline int convert_vbatt_raw_to_uv(struct qpnp_bms_chip *chip, |
| 494 | uint16_t reading) |
| 495 | { |
Xiaozhe Shi | 4dbc01b | 2013-04-30 11:27:52 -0700 | [diff] [blame] | 496 | int64_t uv; |
| 497 | int rc; |
Xiaozhe Shi | 4e37665 | 2012-10-25 12:38:50 -0700 | [diff] [blame] | 498 | |
| 499 | uv = vadc_reading_to_uv(reading); |
Xiaozhe Shi | 4dbc01b | 2013-04-30 11:27:52 -0700 | [diff] [blame] | 500 | pr_debug("%u raw converted into %lld uv\n", reading, uv); |
Xiaozhe Shi | 4e37665 | 2012-10-25 12:38:50 -0700 | [diff] [blame] | 501 | uv = adjust_vbatt_reading(chip, uv); |
Xiaozhe Shi | 4dbc01b | 2013-04-30 11:27:52 -0700 | [diff] [blame] | 502 | pr_debug("adjusted into %lld uv\n", uv); |
Siddartha Mohanadoss | 3cb2b6b | 2013-06-21 12:07:05 -0700 | [diff] [blame] | 503 | rc = qpnp_vbat_sns_comp_result(chip->vadc_dev, &uv); |
Xiaozhe Shi | 4dbc01b | 2013-04-30 11:27:52 -0700 | [diff] [blame] | 504 | if (rc) |
| 505 | pr_debug("could not compensate vbatt\n"); |
| 506 | pr_debug("compensated into %lld uv\n", uv); |
Xiaozhe Shi | 4e37665 | 2012-10-25 12:38:50 -0700 | [diff] [blame] | 507 | return uv; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 508 | } |
| 509 | |
| 510 | #define CC_READING_RESOLUTION_N 542535 |
| 511 | #define CC_READING_RESOLUTION_D 100000 |
Xiaozhe Shi | 8f5dd1b | 2013-04-30 10:27:58 -0700 | [diff] [blame] | 512 | static s64 cc_reading_to_uv(s64 reading) |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 513 | { |
| 514 | return div_s64(reading * CC_READING_RESOLUTION_N, |
| 515 | CC_READING_RESOLUTION_D); |
| 516 | } |
| 517 | |
Xiaozhe Shi | 0c48493 | 2013-02-05 16:14:10 -0800 | [diff] [blame] | 518 | #define QPNP_ADC_GAIN_IDEAL 3291LL |
Xiaozhe Shi | 4e37665 | 2012-10-25 12:38:50 -0700 | [diff] [blame] | 519 | static s64 cc_adjust_for_gain(s64 uv, uint16_t gain) |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 520 | { |
| 521 | s64 result_uv; |
| 522 | |
| 523 | pr_debug("adjusting_uv = %lld\n", uv); |
Xiaozhe Shi | 820a47a | 2012-11-27 13:23:27 -0800 | [diff] [blame] | 524 | if (gain == 0) { |
| 525 | pr_debug("gain is %d, not adjusting\n", gain); |
| 526 | return uv; |
| 527 | } |
Xiaozhe Shi | 4e37665 | 2012-10-25 12:38:50 -0700 | [diff] [blame] | 528 | pr_debug("adjusting by factor: %lld/%hu = %lld%%\n", |
Xiaozhe Shi | 0c48493 | 2013-02-05 16:14:10 -0800 | [diff] [blame] | 529 | QPNP_ADC_GAIN_IDEAL, gain, |
| 530 | div_s64(QPNP_ADC_GAIN_IDEAL * 100LL, (s64)gain)); |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 531 | |
Xiaozhe Shi | 0c48493 | 2013-02-05 16:14:10 -0800 | [diff] [blame] | 532 | result_uv = div_s64(uv * QPNP_ADC_GAIN_IDEAL, (s64)gain); |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 533 | pr_debug("result_uv = %lld\n", result_uv); |
| 534 | return result_uv; |
| 535 | } |
| 536 | |
Siddartha Mohanadoss | 55d0bca | 2013-06-24 08:29:34 -0700 | [diff] [blame] | 537 | static s64 cc_reverse_adjust_for_gain(struct qpnp_bms_chip *chip, s64 uv) |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 538 | { |
| 539 | struct qpnp_iadc_calib calibration; |
| 540 | int gain; |
| 541 | s64 result_uv; |
| 542 | |
Siddartha Mohanadoss | 55d0bca | 2013-06-24 08:29:34 -0700 | [diff] [blame] | 543 | qpnp_iadc_get_gain_and_offset(chip->iadc_dev, &calibration); |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 544 | gain = (int)calibration.gain_raw - (int)calibration.offset_raw; |
| 545 | |
| 546 | pr_debug("reverse adjusting_uv = %lld\n", uv); |
| 547 | if (gain == 0) { |
| 548 | pr_debug("gain is %d, not adjusting\n", gain); |
| 549 | return uv; |
| 550 | } |
| 551 | pr_debug("adjusting by factor: %hu/%lld = %lld%%\n", |
| 552 | gain, QPNP_ADC_GAIN_IDEAL, |
| 553 | div64_s64((s64)gain * 100LL, |
| 554 | (s64)QPNP_ADC_GAIN_IDEAL)); |
| 555 | |
| 556 | result_uv = div64_s64(uv * (s64)gain, QPNP_ADC_GAIN_IDEAL); |
| 557 | pr_debug("result_uv = %lld\n", result_uv); |
| 558 | return result_uv; |
| 559 | } |
| 560 | |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 561 | static int convert_vsense_to_uv(struct qpnp_bms_chip *chip, |
| 562 | int16_t reading) |
| 563 | { |
Xiaozhe Shi | 4e37665 | 2012-10-25 12:38:50 -0700 | [diff] [blame] | 564 | struct qpnp_iadc_calib calibration; |
| 565 | |
Siddartha Mohanadoss | 55d0bca | 2013-06-24 08:29:34 -0700 | [diff] [blame] | 566 | qpnp_iadc_get_gain_and_offset(chip->iadc_dev, &calibration); |
Xiaozhe Shi | 4e37665 | 2012-10-25 12:38:50 -0700 | [diff] [blame] | 567 | return cc_adjust_for_gain(cc_reading_to_uv(reading), |
Xiaozhe Shi | 0c48493 | 2013-02-05 16:14:10 -0800 | [diff] [blame] | 568 | calibration.gain_raw - calibration.offset_raw); |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 569 | } |
| 570 | |
| 571 | static int read_vsense_avg(struct qpnp_bms_chip *chip, int *result_uv) |
| 572 | { |
| 573 | int rc; |
| 574 | int16_t reading; |
| 575 | |
| 576 | rc = qpnp_read_wrapper(chip, (u8 *)&reading, |
| 577 | chip->base + BMS1_VSENSE_AVG_DATA0, 2); |
| 578 | |
| 579 | if (rc) { |
| 580 | pr_err("fail to read VSENSE_AVG rc = %d\n", rc); |
| 581 | return rc; |
| 582 | } |
| 583 | |
| 584 | *result_uv = convert_vsense_to_uv(chip, reading); |
| 585 | return 0; |
| 586 | } |
| 587 | |
| 588 | static int get_battery_current(struct qpnp_bms_chip *chip, int *result_ua) |
| 589 | { |
Xiaozhe Shi | 80ba88d | 2013-04-05 10:23:34 -0700 | [diff] [blame] | 590 | int rc, vsense_uv = 0; |
| 591 | int64_t temp_current; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 592 | |
Xiaozhe Shi | d0a7954 | 2012-11-06 10:00:38 -0800 | [diff] [blame] | 593 | if (chip->r_sense_uohm == 0) { |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 594 | pr_err("r_sense is zero\n"); |
| 595 | return -EINVAL; |
| 596 | } |
| 597 | |
| 598 | mutex_lock(&chip->bms_output_lock); |
| 599 | lock_output_data(chip); |
| 600 | read_vsense_avg(chip, &vsense_uv); |
| 601 | unlock_output_data(chip); |
| 602 | mutex_unlock(&chip->bms_output_lock); |
| 603 | |
| 604 | pr_debug("vsense_uv=%duV\n", vsense_uv); |
| 605 | /* cast for signed division */ |
Xiaozhe Shi | 80ba88d | 2013-04-05 10:23:34 -0700 | [diff] [blame] | 606 | temp_current = div_s64((vsense_uv * 1000000LL), |
| 607 | (int)chip->r_sense_uohm); |
| 608 | |
Siddartha Mohanadoss | 55d0bca | 2013-06-24 08:29:34 -0700 | [diff] [blame] | 609 | rc = qpnp_iadc_comp_result(chip->iadc_dev, &temp_current); |
Xiaozhe Shi | 80ba88d | 2013-04-05 10:23:34 -0700 | [diff] [blame] | 610 | if (rc) |
| 611 | pr_debug("error compensation failed: %d\n", rc); |
| 612 | |
| 613 | *result_ua = temp_current; |
| 614 | pr_debug("err compensated ibat=%duA\n", *result_ua); |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 615 | return 0; |
| 616 | } |
| 617 | |
Siddartha Mohanadoss | 3cb2b6b | 2013-06-21 12:07:05 -0700 | [diff] [blame] | 618 | static int get_battery_voltage(struct qpnp_bms_chip *chip, int *result_uv) |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 619 | { |
| 620 | int rc; |
| 621 | struct qpnp_vadc_result adc_result; |
| 622 | |
Siddartha Mohanadoss | 3cb2b6b | 2013-06-21 12:07:05 -0700 | [diff] [blame] | 623 | rc = qpnp_vadc_read(chip->vadc_dev, VBAT_SNS, &adc_result); |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 624 | if (rc) { |
| 625 | pr_err("error reading adc channel = %d, rc = %d\n", |
| 626 | VBAT_SNS, rc); |
| 627 | return rc; |
| 628 | } |
| 629 | pr_debug("mvolts phy = %lld meas = 0x%llx\n", adc_result.physical, |
| 630 | adc_result.measurement); |
| 631 | *result_uv = (int)adc_result.physical; |
| 632 | return 0; |
| 633 | } |
| 634 | |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 635 | #define CC_36_BIT_MASK 0xFFFFFFFFFLL |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 636 | static uint64_t convert_s64_to_s36(int64_t raw64) |
| 637 | { |
| 638 | return (uint64_t) raw64 & CC_36_BIT_MASK; |
| 639 | } |
| 640 | |
| 641 | #define SIGN_EXTEND_36_TO_64_MASK (-1LL ^ CC_36_BIT_MASK) |
| 642 | static int64_t convert_s36_to_s64(uint64_t raw36) |
| 643 | { |
| 644 | raw36 = raw36 & CC_36_BIT_MASK; |
| 645 | /* convert 36 bit signed value into 64 signed value */ |
| 646 | return (raw36 >> 35) == 0LL ? |
| 647 | raw36 : (SIGN_EXTEND_36_TO_64_MASK | raw36); |
| 648 | } |
| 649 | |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 650 | static int read_cc_raw(struct qpnp_bms_chip *chip, int64_t *reading, |
| 651 | int cc_type) |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 652 | { |
| 653 | int64_t raw_reading; |
| 654 | int rc; |
| 655 | |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 656 | if (cc_type == SHDW_CC) |
| 657 | rc = qpnp_read_wrapper(chip, (u8 *)&raw_reading, |
| 658 | chip->base + BMS1_SW_CC_DATA0, 5); |
| 659 | else |
| 660 | rc = qpnp_read_wrapper(chip, (u8 *)&raw_reading, |
| 661 | chip->base + BMS1_CC_DATA0, 5); |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 662 | if (rc) { |
| 663 | pr_err("Error reading cc: rc = %d\n", rc); |
| 664 | return -ENXIO; |
| 665 | } |
| 666 | |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 667 | *reading = convert_s36_to_s64(raw_reading); |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 668 | |
| 669 | return 0; |
| 670 | } |
| 671 | |
Xiaozhe Shi | 4e37665 | 2012-10-25 12:38:50 -0700 | [diff] [blame] | 672 | static int calib_vadc(struct qpnp_bms_chip *chip) |
| 673 | { |
Xiaozhe Shi | f62c015 | 2013-03-28 17:57:19 -0700 | [diff] [blame] | 674 | int rc, raw_0625, raw_1250; |
Xiaozhe Shi | 4e37665 | 2012-10-25 12:38:50 -0700 | [diff] [blame] | 675 | struct qpnp_vadc_result result; |
| 676 | |
Siddartha Mohanadoss | 3cb2b6b | 2013-06-21 12:07:05 -0700 | [diff] [blame] | 677 | rc = qpnp_vadc_read(chip->vadc_dev, REF_625MV, &result); |
Xiaozhe Shi | 4e37665 | 2012-10-25 12:38:50 -0700 | [diff] [blame] | 678 | if (rc) { |
| 679 | pr_debug("vadc read failed with rc = %d\n", rc); |
| 680 | return rc; |
| 681 | } |
Xiaozhe Shi | f62c015 | 2013-03-28 17:57:19 -0700 | [diff] [blame] | 682 | raw_0625 = result.adc_code; |
Xiaozhe Shi | 4e37665 | 2012-10-25 12:38:50 -0700 | [diff] [blame] | 683 | |
Siddartha Mohanadoss | 3cb2b6b | 2013-06-21 12:07:05 -0700 | [diff] [blame] | 684 | rc = qpnp_vadc_read(chip->vadc_dev, REF_125V, &result); |
Xiaozhe Shi | 4e37665 | 2012-10-25 12:38:50 -0700 | [diff] [blame] | 685 | if (rc) { |
| 686 | pr_debug("vadc read failed with rc = %d\n", rc); |
| 687 | return rc; |
| 688 | } |
Xiaozhe Shi | f62c015 | 2013-03-28 17:57:19 -0700 | [diff] [blame] | 689 | raw_1250 = result.adc_code; |
| 690 | chip->vadc_v0625 = vadc_reading_to_uv(raw_0625); |
| 691 | chip->vadc_v1250 = vadc_reading_to_uv(raw_1250); |
| 692 | pr_debug("vadc calib: 0625 = %d raw (%d uv), 1250 = %d raw (%d uv)\n", |
| 693 | raw_0625, chip->vadc_v0625, |
| 694 | raw_1250, chip->vadc_v1250); |
Xiaozhe Shi | 4e37665 | 2012-10-25 12:38:50 -0700 | [diff] [blame] | 695 | return 0; |
| 696 | } |
| 697 | |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 698 | static void convert_and_store_ocv(struct qpnp_bms_chip *chip, |
Abhijeet Dharmapurikar | 4b97cdd | 2012-12-26 21:10:53 -0800 | [diff] [blame] | 699 | struct raw_soc_params *raw, |
| 700 | int batt_temp) |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 701 | { |
Xiaozhe Shi | 4e37665 | 2012-10-25 12:38:50 -0700 | [diff] [blame] | 702 | int rc; |
| 703 | |
| 704 | pr_debug("prev_last_good_ocv_raw = %d, last_good_ocv_raw = %d\n", |
| 705 | chip->prev_last_good_ocv_raw, |
| 706 | raw->last_good_ocv_raw); |
| 707 | rc = calib_vadc(chip); |
| 708 | if (rc) |
| 709 | pr_err("Vadc reference voltage read failed, rc = %d\n", rc); |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 710 | chip->prev_last_good_ocv_raw = raw->last_good_ocv_raw; |
| 711 | raw->last_good_ocv_uv = convert_vbatt_raw_to_uv(chip, |
| 712 | raw->last_good_ocv_raw); |
| 713 | chip->last_ocv_uv = raw->last_good_ocv_uv; |
Abhijeet Dharmapurikar | 4b97cdd | 2012-12-26 21:10:53 -0800 | [diff] [blame] | 714 | chip->last_ocv_temp = batt_temp; |
Xiaozhe Shi | 80ba88d | 2013-04-05 10:23:34 -0700 | [diff] [blame] | 715 | chip->software_cc_uah = 0; |
Xiaozhe Shi | 4e37665 | 2012-10-25 12:38:50 -0700 | [diff] [blame] | 716 | pr_debug("last_good_ocv_uv = %d\n", raw->last_good_ocv_uv); |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 717 | } |
| 718 | |
Xiaozhe Shi | a045a56 | 2012-11-28 16:55:39 -0800 | [diff] [blame] | 719 | #define CLEAR_CC BIT(7) |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 720 | #define CLEAR_SHDW_CC BIT(6) |
Xiaozhe Shi | a045a56 | 2012-11-28 16:55:39 -0800 | [diff] [blame] | 721 | /** |
| 722 | * reset both cc and sw-cc. |
| 723 | * note: this should only be ever called from one thread |
| 724 | * or there may be a race condition where CC is never enabled |
| 725 | * again |
| 726 | */ |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 727 | static void reset_cc(struct qpnp_bms_chip *chip, u8 flags) |
Xiaozhe Shi | a045a56 | 2012-11-28 16:55:39 -0800 | [diff] [blame] | 728 | { |
| 729 | int rc; |
| 730 | |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 731 | pr_debug("resetting cc manually with flags %hhu\n", flags); |
| 732 | mutex_lock(&chip->bms_output_lock); |
Xiaozhe Shi | a045a56 | 2012-11-28 16:55:39 -0800 | [diff] [blame] | 733 | rc = qpnp_masked_write(chip, BMS1_CC_CLEAR_CTL, |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 734 | flags, |
| 735 | flags); |
Xiaozhe Shi | a045a56 | 2012-11-28 16:55:39 -0800 | [diff] [blame] | 736 | if (rc) |
| 737 | pr_err("cc reset failed: %d\n", rc); |
| 738 | |
| 739 | /* wait for 100us for cc to reset */ |
| 740 | udelay(100); |
| 741 | |
| 742 | rc = qpnp_masked_write(chip, BMS1_CC_CLEAR_CTL, |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 743 | flags, 0); |
Xiaozhe Shi | a045a56 | 2012-11-28 16:55:39 -0800 | [diff] [blame] | 744 | if (rc) |
| 745 | pr_err("cc reenable failed: %d\n", rc); |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 746 | mutex_unlock(&chip->bms_output_lock); |
Xiaozhe Shi | a045a56 | 2012-11-28 16:55:39 -0800 | [diff] [blame] | 747 | } |
| 748 | |
Xiaozhe Shi | 890fbf4 | 2013-05-02 16:42:53 -0700 | [diff] [blame] | 749 | static int get_battery_status(struct qpnp_bms_chip *chip) |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 750 | { |
| 751 | union power_supply_propval ret = {0,}; |
| 752 | |
| 753 | if (chip->batt_psy == NULL) |
| 754 | chip->batt_psy = power_supply_get_by_name("battery"); |
| 755 | if (chip->batt_psy) { |
| 756 | /* if battery has been registered, use the status property */ |
| 757 | chip->batt_psy->get_property(chip->batt_psy, |
| 758 | POWER_SUPPLY_PROP_STATUS, &ret); |
Xiaozhe Shi | 890fbf4 | 2013-05-02 16:42:53 -0700 | [diff] [blame] | 759 | return ret.intval; |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 760 | } |
| 761 | |
| 762 | /* Default to false if the battery power supply is not registered. */ |
| 763 | pr_debug("battery power supply is not registered\n"); |
Xiaozhe Shi | 890fbf4 | 2013-05-02 16:42:53 -0700 | [diff] [blame] | 764 | return POWER_SUPPLY_STATUS_UNKNOWN; |
| 765 | } |
| 766 | |
| 767 | static bool is_battery_charging(struct qpnp_bms_chip *chip) |
| 768 | { |
Xiaozhe Shi | 72a72f2 | 2013-12-26 13:54:29 -0800 | [diff] [blame] | 769 | union power_supply_propval ret = {0,}; |
| 770 | |
| 771 | if (chip->batt_psy == NULL) |
| 772 | chip->batt_psy = power_supply_get_by_name("battery"); |
| 773 | if (chip->batt_psy) { |
| 774 | /* if battery has been registered, use the status property */ |
| 775 | chip->batt_psy->get_property(chip->batt_psy, |
| 776 | POWER_SUPPLY_PROP_CHARGE_TYPE, &ret); |
| 777 | return ret.intval != POWER_SUPPLY_CHARGE_TYPE_NONE; |
| 778 | } |
| 779 | |
| 780 | /* Default to false if the battery power supply is not registered. */ |
| 781 | pr_debug("battery power supply is not registered\n"); |
| 782 | return false; |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 783 | } |
| 784 | |
Abhijeet Dharmapurikar | 84b13dd | 2013-07-08 18:43:56 -0700 | [diff] [blame] | 785 | static bool is_battery_full(struct qpnp_bms_chip *chip) |
| 786 | { |
| 787 | return get_battery_status(chip) == POWER_SUPPLY_STATUS_FULL; |
| 788 | } |
| 789 | |
Xiaozhe Shi | 4515c76 | 2013-11-13 16:36:54 -0800 | [diff] [blame] | 790 | #define BAT_PRES_BIT BIT(7) |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 791 | static bool is_battery_present(struct qpnp_bms_chip *chip) |
| 792 | { |
| 793 | union power_supply_propval ret = {0,}; |
Xiaozhe Shi | 4515c76 | 2013-11-13 16:36:54 -0800 | [diff] [blame] | 794 | int rc; |
| 795 | u8 batt_pres; |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 796 | |
Xiaozhe Shi | 4515c76 | 2013-11-13 16:36:54 -0800 | [diff] [blame] | 797 | /* first try to use the batt_pres register if given */ |
| 798 | if (chip->batt_pres_addr) { |
| 799 | rc = qpnp_read_wrapper(chip, &batt_pres, |
| 800 | chip->batt_pres_addr, 1); |
| 801 | if (!rc && (batt_pres & BAT_PRES_BIT)) |
| 802 | return true; |
| 803 | else |
| 804 | return false; |
| 805 | } |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 806 | if (chip->batt_psy == NULL) |
| 807 | chip->batt_psy = power_supply_get_by_name("battery"); |
| 808 | if (chip->batt_psy) { |
Xiaozhe Shi | 24f91a0 | 2013-08-29 17:15:05 -0700 | [diff] [blame] | 809 | /* if battery has been registered, use the present property */ |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 810 | chip->batt_psy->get_property(chip->batt_psy, |
| 811 | POWER_SUPPLY_PROP_PRESENT, &ret); |
| 812 | return ret.intval; |
| 813 | } |
| 814 | |
| 815 | /* Default to false if the battery power supply is not registered. */ |
| 816 | pr_debug("battery power supply is not registered\n"); |
| 817 | return false; |
| 818 | } |
| 819 | |
Xiaozhe Shi | 24f91a0 | 2013-08-29 17:15:05 -0700 | [diff] [blame] | 820 | static int get_battery_insertion_ocv_uv(struct qpnp_bms_chip *chip) |
| 821 | { |
| 822 | union power_supply_propval ret = {0,}; |
| 823 | int rc, vbat; |
| 824 | |
| 825 | if (chip->batt_psy == NULL) |
| 826 | chip->batt_psy = power_supply_get_by_name("battery"); |
| 827 | if (chip->batt_psy) { |
| 828 | /* if battery has been registered, use the ocv property */ |
| 829 | rc = chip->batt_psy->get_property(chip->batt_psy, |
| 830 | POWER_SUPPLY_PROP_VOLTAGE_OCV, &ret); |
| 831 | if (rc) { |
| 832 | /* |
| 833 | * Default to vbatt if the battery OCV is not |
| 834 | * registered. |
| 835 | */ |
| 836 | pr_debug("Battery psy does not have voltage ocv\n"); |
| 837 | rc = get_battery_voltage(chip, &vbat); |
| 838 | if (rc) |
| 839 | return -EINVAL; |
| 840 | return vbat; |
| 841 | } |
| 842 | return ret.intval; |
| 843 | } |
| 844 | |
| 845 | pr_debug("battery power supply is not registered\n"); |
| 846 | return -EINVAL; |
| 847 | } |
| 848 | |
Abhijeet Dharmapurikar | 84b13dd | 2013-07-08 18:43:56 -0700 | [diff] [blame] | 849 | static bool is_batfet_closed(struct qpnp_bms_chip *chip) |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 850 | { |
Abhijeet Dharmapurikar | 84b13dd | 2013-07-08 18:43:56 -0700 | [diff] [blame] | 851 | union power_supply_propval ret = {0,}; |
| 852 | |
| 853 | if (chip->batt_psy == NULL) |
| 854 | chip->batt_psy = power_supply_get_by_name("battery"); |
| 855 | if (chip->batt_psy) { |
| 856 | /* if battery has been registered, use the online property */ |
| 857 | chip->batt_psy->get_property(chip->batt_psy, |
| 858 | POWER_SUPPLY_PROP_ONLINE, &ret); |
| 859 | return !!ret.intval; |
| 860 | } |
| 861 | |
| 862 | /* Default to true if the battery power supply is not registered. */ |
| 863 | pr_debug("battery power supply is not registered\n"); |
| 864 | return true; |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 865 | } |
| 866 | |
| 867 | static int get_simultaneous_batt_v_and_i(struct qpnp_bms_chip *chip, |
| 868 | int *ibat_ua, int *vbat_uv) |
| 869 | { |
| 870 | struct qpnp_iadc_result i_result; |
| 871 | struct qpnp_vadc_result v_result; |
| 872 | enum qpnp_iadc_channels iadc_channel; |
| 873 | int rc; |
| 874 | |
| 875 | iadc_channel = chip->use_external_rsense ? |
| 876 | EXTERNAL_RSENSE : INTERNAL_RSENSE; |
Xiaozhe Shi | 8658c98 | 2013-04-30 11:33:07 -0700 | [diff] [blame] | 877 | if (is_battery_full(chip)) { |
| 878 | rc = get_battery_current(chip, ibat_ua); |
| 879 | if (rc) { |
| 880 | pr_err("bms current read failed with rc: %d\n", rc); |
| 881 | return rc; |
| 882 | } |
Siddartha Mohanadoss | 3cb2b6b | 2013-06-21 12:07:05 -0700 | [diff] [blame] | 883 | rc = qpnp_vadc_read(chip->vadc_dev, VBAT_SNS, &v_result); |
Xiaozhe Shi | 8658c98 | 2013-04-30 11:33:07 -0700 | [diff] [blame] | 884 | if (rc) { |
| 885 | pr_err("vadc read failed with rc: %d\n", rc); |
| 886 | return rc; |
| 887 | } |
| 888 | *vbat_uv = (int)v_result.physical; |
| 889 | } else { |
Siddartha Mohanadoss | 55d0bca | 2013-06-24 08:29:34 -0700 | [diff] [blame] | 890 | rc = qpnp_iadc_vadc_sync_read(chip->iadc_dev, |
| 891 | iadc_channel, &i_result, |
Xiaozhe Shi | 8658c98 | 2013-04-30 11:33:07 -0700 | [diff] [blame] | 892 | VBAT_SNS, &v_result); |
| 893 | if (rc) { |
| 894 | pr_err("adc sync read failed with rc: %d\n", rc); |
| 895 | return rc; |
| 896 | } |
| 897 | /* |
| 898 | * reverse the current read by the iadc, since the bms uses |
| 899 | * flipped battery current polarity. |
| 900 | */ |
| 901 | *ibat_ua = -1 * (int)i_result.result_ua; |
| 902 | *vbat_uv = (int)v_result.physical; |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 903 | } |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 904 | |
| 905 | return 0; |
| 906 | } |
| 907 | |
| 908 | static int estimate_ocv(struct qpnp_bms_chip *chip) |
| 909 | { |
| 910 | int ibat_ua, vbat_uv, ocv_est_uv; |
| 911 | int rc; |
Xiaozhe Shi | 1a10aff | 2013-04-01 15:40:05 -0700 | [diff] [blame] | 912 | int rbatt_mohm = chip->default_rbatt_mohm + chip->r_conn_mohm |
| 913 | + chip->rbatt_capacitive_mohm; |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 914 | |
| 915 | rc = get_simultaneous_batt_v_and_i(chip, &ibat_ua, &vbat_uv); |
| 916 | if (rc) { |
| 917 | pr_err("simultaneous failed rc = %d\n", rc); |
| 918 | return rc; |
| 919 | } |
| 920 | |
| 921 | ocv_est_uv = vbat_uv + (ibat_ua * rbatt_mohm) / 1000; |
| 922 | pr_debug("estimated pon ocv = %d\n", ocv_est_uv); |
| 923 | return ocv_est_uv; |
| 924 | } |
| 925 | |
| 926 | static void reset_for_new_battery(struct qpnp_bms_chip *chip, int batt_temp) |
| 927 | { |
Xiaozhe Shi | 24f91a0 | 2013-08-29 17:15:05 -0700 | [diff] [blame] | 928 | chip->last_ocv_uv = chip->insertion_ocv_uv; |
Xiaozhe Shi | 04da099 | 2013-04-26 16:32:14 -0700 | [diff] [blame] | 929 | mutex_lock(&chip->last_soc_mutex); |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 930 | chip->last_soc = -EINVAL; |
Xiaozhe Shi | 04da099 | 2013-04-26 16:32:14 -0700 | [diff] [blame] | 931 | chip->last_soc_invalid = true; |
| 932 | mutex_unlock(&chip->last_soc_mutex); |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 933 | chip->soc_at_cv = -EINVAL; |
| 934 | chip->shutdown_soc_invalid = true; |
| 935 | chip->shutdown_soc = 0; |
| 936 | chip->shutdown_iavg_ma = 0; |
| 937 | chip->prev_pc_unusable = -EINVAL; |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 938 | reset_cc(chip, CLEAR_CC | CLEAR_SHDW_CC); |
Xiaozhe Shi | 80ba88d | 2013-04-05 10:23:34 -0700 | [diff] [blame] | 939 | chip->software_cc_uah = 0; |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 940 | chip->software_shdw_cc_uah = 0; |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 941 | chip->last_cc_uah = INT_MIN; |
| 942 | chip->last_ocv_temp = batt_temp; |
Xiaozhe Shi | fc2f5a0 | 2013-01-28 15:09:04 -0800 | [diff] [blame] | 943 | chip->prev_batt_terminal_uv = 0; |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 944 | if (chip->enable_fcc_learning) { |
| 945 | chip->adjusted_fcc_temp_lut = NULL; |
| 946 | chip->fcc_new_mah = -EINVAL; |
| 947 | /* reset the charge-cycle and charge-increase registers */ |
| 948 | chip->charge_increase = 0; |
| 949 | chip->charge_cycles = 0; |
| 950 | backup_charge_cycle(chip); |
| 951 | /* discard all the FCC learnt data and reset the local table */ |
| 952 | discard_backup_fcc_data(chip); |
| 953 | memset(chip->fcc_learning_samples, 0, |
| 954 | chip->min_fcc_learning_samples * |
| 955 | sizeof(struct fcc_sample)); |
| 956 | } |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 957 | } |
| 958 | |
Xiaozhe Shi | 39a5dc6 | 2013-10-30 11:33:27 -0700 | [diff] [blame] | 959 | #define SIGN(x) ((x) < 0 ? -1 : 1) |
| 960 | #define UV_PER_SPIN 50000 |
| 961 | static int find_ocv_for_pc(struct qpnp_bms_chip *chip, int batt_temp, int pc) |
| 962 | { |
| 963 | int new_pc; |
| 964 | int batt_temp_degc = batt_temp / 10; |
| 965 | int ocv_mv; |
| 966 | int delta_mv = 5; |
| 967 | int max_spin_count; |
| 968 | int count = 0; |
| 969 | int sign, new_sign; |
| 970 | |
| 971 | ocv_mv = interpolate_ocv(chip->pc_temp_ocv_lut, batt_temp_degc, pc); |
| 972 | |
| 973 | new_pc = interpolate_pc(chip->pc_temp_ocv_lut, batt_temp_degc, ocv_mv); |
| 974 | pr_debug("test revlookup pc = %d for ocv = %d\n", new_pc, ocv_mv); |
| 975 | max_spin_count = 1 + (chip->max_voltage_uv - chip->v_cutoff_uv) |
| 976 | / UV_PER_SPIN; |
| 977 | sign = SIGN(pc - new_pc); |
| 978 | |
| 979 | while (abs(new_pc - pc) != 0 && count < max_spin_count) { |
| 980 | /* |
| 981 | * If the newly interpolated pc is larger than the lookup pc, |
| 982 | * the ocv should be reduced and vice versa |
| 983 | */ |
| 984 | new_sign = SIGN(pc - new_pc); |
| 985 | /* |
| 986 | * If the sign has changed, then we have passed the lookup pc. |
| 987 | * reduce the ocv step size to get finer results. |
| 988 | * |
| 989 | * If we have already reduced the ocv step size and still |
| 990 | * passed the lookup pc, just stop and use the current ocv. |
| 991 | * This can only happen if the batterydata profile is |
| 992 | * non-monotonic anyways. |
| 993 | */ |
| 994 | if (new_sign != sign) { |
| 995 | if (delta_mv > 1) |
| 996 | delta_mv = 1; |
| 997 | else |
| 998 | break; |
| 999 | } |
| 1000 | sign = new_sign; |
| 1001 | |
| 1002 | ocv_mv = ocv_mv + delta_mv * sign; |
| 1003 | new_pc = interpolate_pc(chip->pc_temp_ocv_lut, |
| 1004 | batt_temp_degc, ocv_mv); |
| 1005 | pr_debug("test revlookup pc = %d for ocv = %d\n", |
| 1006 | new_pc, ocv_mv); |
| 1007 | count++; |
| 1008 | } |
| 1009 | |
| 1010 | return ocv_mv * 1000; |
| 1011 | } |
| 1012 | |
Abhijeet Dharmapurikar | 15f30fb | 2012-12-27 17:20:29 -0800 | [diff] [blame] | 1013 | #define OCV_RAW_UNINITIALIZED 0xFFFF |
Xiaozhe Shi | 77ec38d | 2013-04-29 16:41:58 -0700 | [diff] [blame] | 1014 | #define MIN_OCV_UV 2000000 |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 1015 | static int read_soc_params_raw(struct qpnp_bms_chip *chip, |
Abhijeet Dharmapurikar | 4b97cdd | 2012-12-26 21:10:53 -0800 | [diff] [blame] | 1016 | struct raw_soc_params *raw, |
| 1017 | int batt_temp) |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 1018 | { |
Xiaozhe Shi | 39a5dc6 | 2013-10-30 11:33:27 -0700 | [diff] [blame] | 1019 | int warm_reset, rc; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1020 | |
| 1021 | mutex_lock(&chip->bms_output_lock); |
Xiaozhe Shi | a045a56 | 2012-11-28 16:55:39 -0800 | [diff] [blame] | 1022 | |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1023 | lock_output_data(chip); |
| 1024 | |
| 1025 | rc = qpnp_read_wrapper(chip, (u8 *)&raw->last_good_ocv_raw, |
| 1026 | chip->base + BMS1_OCV_FOR_SOC_DATA0, 2); |
| 1027 | if (rc) { |
| 1028 | pr_err("Error reading ocv: rc = %d\n", rc); |
| 1029 | return -ENXIO; |
| 1030 | } |
| 1031 | |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 1032 | rc = read_cc_raw(chip, &raw->cc, CC); |
| 1033 | rc = read_cc_raw(chip, &raw->shdw_cc, SHDW_CC); |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1034 | if (rc) { |
| 1035 | pr_err("Failed to read raw cc data, rc = %d\n", rc); |
| 1036 | return rc; |
| 1037 | } |
| 1038 | |
| 1039 | unlock_output_data(chip); |
| 1040 | mutex_unlock(&chip->bms_output_lock); |
| 1041 | |
Abhijeet Dharmapurikar | 15f30fb | 2012-12-27 17:20:29 -0800 | [diff] [blame] | 1042 | if (chip->prev_last_good_ocv_raw == OCV_RAW_UNINITIALIZED) { |
Abhijeet Dharmapurikar | 4b97cdd | 2012-12-26 21:10:53 -0800 | [diff] [blame] | 1043 | convert_and_store_ocv(chip, raw, batt_temp); |
Xiaozhe Shi | 77ec38d | 2013-04-29 16:41:58 -0700 | [diff] [blame] | 1044 | pr_debug("PON_OCV_UV = %d, cc = %llx\n", |
| 1045 | chip->last_ocv_uv, raw->cc); |
| 1046 | warm_reset = qpnp_pon_is_warm_reset(); |
| 1047 | if (raw->last_good_ocv_uv < MIN_OCV_UV |
| 1048 | || warm_reset > 0) { |
| 1049 | pr_debug("OCV is stale or bad, estimating new OCV.\n"); |
| 1050 | chip->last_ocv_uv = estimate_ocv(chip); |
| 1051 | raw->last_good_ocv_uv = chip->last_ocv_uv; |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 1052 | reset_cc(chip, CLEAR_CC | CLEAR_SHDW_CC); |
Xiaozhe Shi | 77ec38d | 2013-04-29 16:41:58 -0700 | [diff] [blame] | 1053 | pr_debug("New PON_OCV_UV = %d, cc = %llx\n", |
| 1054 | chip->last_ocv_uv, raw->cc); |
| 1055 | } |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 1056 | } else if (chip->new_battery) { |
| 1057 | /* if a new battery was inserted, estimate the ocv */ |
| 1058 | reset_for_new_battery(chip, batt_temp); |
| 1059 | raw->cc = 0; |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 1060 | raw->shdw_cc = 0; |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 1061 | raw->last_good_ocv_uv = chip->last_ocv_uv; |
| 1062 | chip->new_battery = false; |
Xiaozhe Shi | 74548b9 | 2013-05-02 16:47:08 -0700 | [diff] [blame] | 1063 | } else if (chip->done_charging) { |
| 1064 | chip->done_charging = false; |
| 1065 | /* if we just finished charging, reset CC and fake 100% */ |
| 1066 | chip->ocv_reading_at_100 = raw->last_good_ocv_raw; |
Xiaozhe Shi | 39a5dc6 | 2013-10-30 11:33:27 -0700 | [diff] [blame] | 1067 | chip->last_ocv_uv = find_ocv_for_pc(chip, batt_temp, 100); |
| 1068 | raw->last_good_ocv_uv = chip->last_ocv_uv; |
Xiaozhe Shi | 74548b9 | 2013-05-02 16:47:08 -0700 | [diff] [blame] | 1069 | raw->cc = 0; |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 1070 | raw->shdw_cc = 0; |
| 1071 | reset_cc(chip, CLEAR_CC | CLEAR_SHDW_CC); |
Xiaozhe Shi | 74548b9 | 2013-05-02 16:47:08 -0700 | [diff] [blame] | 1072 | chip->last_ocv_temp = batt_temp; |
| 1073 | chip->software_cc_uah = 0; |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 1074 | chip->software_shdw_cc_uah = 0; |
Xiaozhe Shi | 74548b9 | 2013-05-02 16:47:08 -0700 | [diff] [blame] | 1075 | chip->last_cc_uah = INT_MIN; |
| 1076 | pr_debug("EOC Battery full ocv_reading = 0x%x\n", |
| 1077 | chip->ocv_reading_at_100); |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1078 | } else if (chip->prev_last_good_ocv_raw != raw->last_good_ocv_raw) { |
Abhijeet Dharmapurikar | 4b97cdd | 2012-12-26 21:10:53 -0800 | [diff] [blame] | 1079 | convert_and_store_ocv(chip, raw, batt_temp); |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1080 | /* forget the old cc value upon ocv */ |
Xiaozhe Shi | f36d286 | 2013-01-04 10:17:35 -0800 | [diff] [blame] | 1081 | chip->last_cc_uah = INT_MIN; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1082 | } else { |
| 1083 | raw->last_good_ocv_uv = chip->last_ocv_uv; |
| 1084 | } |
| 1085 | |
Xiaozhe Shi | 74548b9 | 2013-05-02 16:47:08 -0700 | [diff] [blame] | 1086 | /* stop faking a high OCV if we get a new OCV */ |
| 1087 | if (chip->ocv_reading_at_100 != raw->last_good_ocv_raw) |
Abhijeet Dharmapurikar | 15f30fb | 2012-12-27 17:20:29 -0800 | [diff] [blame] | 1088 | chip->ocv_reading_at_100 = OCV_RAW_UNINITIALIZED; |
Xiaozhe Shi | 74548b9 | 2013-05-02 16:47:08 -0700 | [diff] [blame] | 1089 | |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1090 | pr_debug("last_good_ocv_raw= 0x%x, last_good_ocv_uv= %duV\n", |
| 1091 | raw->last_good_ocv_raw, raw->last_good_ocv_uv); |
| 1092 | pr_debug("cc_raw= 0x%llx\n", raw->cc); |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 1093 | return 0; |
| 1094 | } |
| 1095 | |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1096 | static int calculate_pc(struct qpnp_bms_chip *chip, int ocv_uv, |
| 1097 | int batt_temp) |
| 1098 | { |
| 1099 | int pc; |
| 1100 | |
| 1101 | pc = interpolate_pc(chip->pc_temp_ocv_lut, |
| 1102 | batt_temp / 10, ocv_uv / 1000); |
| 1103 | pr_debug("pc = %u %% for ocv = %d uv batt_temp = %d\n", |
| 1104 | pc, ocv_uv, batt_temp); |
| 1105 | /* Multiply the initial FCC value by the scale factor. */ |
| 1106 | return pc; |
| 1107 | } |
| 1108 | |
| 1109 | static int calculate_fcc(struct qpnp_bms_chip *chip, int batt_temp) |
| 1110 | { |
| 1111 | int fcc_uah; |
| 1112 | |
| 1113 | if (chip->adjusted_fcc_temp_lut == NULL) { |
| 1114 | /* interpolate_fcc returns a mv value. */ |
| 1115 | fcc_uah = interpolate_fcc(chip->fcc_temp_lut, |
| 1116 | batt_temp) * 1000; |
| 1117 | pr_debug("fcc = %d uAh\n", fcc_uah); |
| 1118 | return fcc_uah; |
| 1119 | } else { |
| 1120 | return 1000 * interpolate_fcc(chip->adjusted_fcc_temp_lut, |
| 1121 | batt_temp); |
| 1122 | } |
| 1123 | } |
| 1124 | |
| 1125 | /* calculate remaining charge at the time of ocv */ |
| 1126 | static int calculate_ocv_charge(struct qpnp_bms_chip *chip, |
| 1127 | struct raw_soc_params *raw, |
Abhijeet Dharmapurikar | 4b97cdd | 2012-12-26 21:10:53 -0800 | [diff] [blame] | 1128 | int fcc_uah) |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1129 | { |
| 1130 | int ocv_uv, pc; |
| 1131 | |
| 1132 | ocv_uv = raw->last_good_ocv_uv; |
Abhijeet Dharmapurikar | 4b97cdd | 2012-12-26 21:10:53 -0800 | [diff] [blame] | 1133 | pc = calculate_pc(chip, ocv_uv, chip->last_ocv_temp); |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1134 | pr_debug("ocv_uv = %d pc = %d\n", ocv_uv, pc); |
| 1135 | return (fcc_uah * pc) / 100; |
| 1136 | } |
| 1137 | |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1138 | #define CC_READING_TICKS 56 |
| 1139 | #define SLEEP_CLK_HZ 32764 |
| 1140 | #define SECONDS_PER_HOUR 3600 |
| 1141 | |
Xiaozhe Shi | a9b597d | 2013-02-12 11:00:39 -0800 | [diff] [blame] | 1142 | static s64 cc_uv_to_pvh(s64 cc_uv) |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1143 | { |
Xiaozhe Shi | a9b597d | 2013-02-12 11:00:39 -0800 | [diff] [blame] | 1144 | /* Note that it is necessary need to multiply by 1000000 to convert |
| 1145 | * from uvh to pvh here. |
| 1146 | * However, the maximum Coulomb Counter value is 2^35, which can cause |
| 1147 | * an over flow. |
| 1148 | * Multiply by 100000 first to perserve as much precision as possible |
| 1149 | * then multiply by 10 after doing the division in order to avoid |
| 1150 | * overflow on the maximum Coulomb Counter value. |
| 1151 | */ |
| 1152 | return div_s64(cc_uv * CC_READING_TICKS * 100000, |
| 1153 | SLEEP_CLK_HZ * SECONDS_PER_HOUR) * 10; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1154 | } |
| 1155 | |
| 1156 | /** |
Xiaozhe Shi | fb37f3b | 2013-05-20 16:56:19 -0700 | [diff] [blame] | 1157 | * calculate_cc() - converts a hardware coulomb counter reading into uah |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1158 | * @chip: the bms chip pointer |
| 1159 | * @cc: the cc reading from bms h/w |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 1160 | * @cc_type: calcualte cc from regular or shadow coulomb counter |
Xiaozhe Shi | fb37f3b | 2013-05-20 16:56:19 -0700 | [diff] [blame] | 1161 | * @clear_cc: whether this function should clear the hardware counter |
| 1162 | * after reading |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1163 | * |
Xiaozhe Shi | fb37f3b | 2013-05-20 16:56:19 -0700 | [diff] [blame] | 1164 | * Converts the 64 bit hardware coulomb counter into microamp-hour by taking |
| 1165 | * into account hardware resolution and adc errors. |
| 1166 | * |
| 1167 | * Return: the coulomb counter based charge in uAh (micro-amp hour) |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1168 | */ |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 1169 | static int calculate_cc(struct qpnp_bms_chip *chip, int64_t cc, |
| 1170 | int cc_type, int clear_cc) |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1171 | { |
Xiaozhe Shi | 4e37665 | 2012-10-25 12:38:50 -0700 | [diff] [blame] | 1172 | struct qpnp_iadc_calib calibration; |
Xiaozhe Shi | 80ba88d | 2013-04-05 10:23:34 -0700 | [diff] [blame] | 1173 | struct qpnp_vadc_result result; |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 1174 | int64_t cc_voltage_uv, cc_pvh, cc_uah, *software_counter; |
Xiaozhe Shi | fb37f3b | 2013-05-20 16:56:19 -0700 | [diff] [blame] | 1175 | int rc; |
Xiaozhe Shi | 80ba88d | 2013-04-05 10:23:34 -0700 | [diff] [blame] | 1176 | |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 1177 | software_counter = cc_type == SHDW_CC ? |
| 1178 | &chip->software_shdw_cc_uah : &chip->software_cc_uah; |
Siddartha Mohanadoss | 3cb2b6b | 2013-06-21 12:07:05 -0700 | [diff] [blame] | 1179 | rc = qpnp_vadc_read(chip->vadc_dev, DIE_TEMP, &result); |
Xiaozhe Shi | 80ba88d | 2013-04-05 10:23:34 -0700 | [diff] [blame] | 1180 | if (rc) { |
| 1181 | pr_err("could not read pmic die temperature: %d\n", rc); |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 1182 | return *software_counter; |
Xiaozhe Shi | 80ba88d | 2013-04-05 10:23:34 -0700 | [diff] [blame] | 1183 | } |
| 1184 | |
Siddartha Mohanadoss | 55d0bca | 2013-06-24 08:29:34 -0700 | [diff] [blame] | 1185 | qpnp_iadc_get_gain_and_offset(chip->iadc_dev, &calibration); |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 1186 | pr_debug("%scc = %lld, die_temp = %lld\n", |
| 1187 | cc_type == SHDW_CC ? "shdw_" : "", |
| 1188 | cc, result.physical); |
Xiaozhe Shi | 8f5dd1b | 2013-04-30 10:27:58 -0700 | [diff] [blame] | 1189 | cc_voltage_uv = cc_reading_to_uv(cc); |
Xiaozhe Shi | 0c48493 | 2013-02-05 16:14:10 -0800 | [diff] [blame] | 1190 | cc_voltage_uv = cc_adjust_for_gain(cc_voltage_uv, |
| 1191 | calibration.gain_raw |
| 1192 | - calibration.offset_raw); |
Xiaozhe Shi | a9b597d | 2013-02-12 11:00:39 -0800 | [diff] [blame] | 1193 | cc_pvh = cc_uv_to_pvh(cc_voltage_uv); |
Xiaozhe Shi | a9b597d | 2013-02-12 11:00:39 -0800 | [diff] [blame] | 1194 | cc_uah = div_s64(cc_pvh, chip->r_sense_uohm); |
Siddartha Mohanadoss | 55d0bca | 2013-06-24 08:29:34 -0700 | [diff] [blame] | 1195 | rc = qpnp_iadc_comp_result(chip->iadc_dev, &cc_uah); |
Xiaozhe Shi | 80ba88d | 2013-04-05 10:23:34 -0700 | [diff] [blame] | 1196 | if (rc) |
| 1197 | pr_debug("error compensation failed: %d\n", rc); |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 1198 | if (clear_cc == RESET) { |
| 1199 | pr_debug("software_%scc = %lld, added cc_uah = %lld\n", |
| 1200 | cc_type == SHDW_CC ? "sw_" : "", |
| 1201 | *software_counter, cc_uah); |
| 1202 | *software_counter += cc_uah; |
| 1203 | reset_cc(chip, cc_type == SHDW_CC ? CLEAR_SHDW_CC : CLEAR_CC); |
| 1204 | return (int)*software_counter; |
Xiaozhe Shi | fb37f3b | 2013-05-20 16:56:19 -0700 | [diff] [blame] | 1205 | } else { |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 1206 | pr_debug("software_%scc = %lld, cc_uah = %lld, total = %lld\n", |
| 1207 | cc_type == SHDW_CC ? "shdw_" : "", |
| 1208 | *software_counter, cc_uah, |
| 1209 | *software_counter + cc_uah); |
| 1210 | return *software_counter + cc_uah; |
Xiaozhe Shi | fb37f3b | 2013-05-20 16:56:19 -0700 | [diff] [blame] | 1211 | } |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1212 | } |
| 1213 | |
| 1214 | static int get_rbatt(struct qpnp_bms_chip *chip, |
| 1215 | int soc_rbatt_mohm, int batt_temp) |
| 1216 | { |
| 1217 | int rbatt_mohm, scalefactor; |
| 1218 | |
| 1219 | rbatt_mohm = chip->default_rbatt_mohm; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1220 | if (chip->rbatt_sf_lut == NULL) { |
| 1221 | pr_debug("RBATT = %d\n", rbatt_mohm); |
| 1222 | return rbatt_mohm; |
| 1223 | } |
| 1224 | /* Convert the batt_temp to DegC from deciDegC */ |
| 1225 | batt_temp = batt_temp / 10; |
| 1226 | scalefactor = interpolate_scalingfactor(chip->rbatt_sf_lut, |
| 1227 | batt_temp, soc_rbatt_mohm); |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1228 | rbatt_mohm = (rbatt_mohm * scalefactor) / 100; |
| 1229 | |
| 1230 | rbatt_mohm += chip->r_conn_mohm; |
Xiaozhe Shi | 1a10aff | 2013-04-01 15:40:05 -0700 | [diff] [blame] | 1231 | rbatt_mohm += chip->rbatt_capacitive_mohm; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1232 | return rbatt_mohm; |
| 1233 | } |
| 1234 | |
Xiaozhe Shi | 06b67cc | 2013-03-29 12:07:40 -0700 | [diff] [blame] | 1235 | #define IAVG_MINIMAL_TIME 2 |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1236 | static void calculate_iavg(struct qpnp_bms_chip *chip, int cc_uah, |
Xiaozhe Shi | f36d286 | 2013-01-04 10:17:35 -0800 | [diff] [blame] | 1237 | int *iavg_ua, int delta_time_s) |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1238 | { |
Xiaozhe Shi | f36d286 | 2013-01-04 10:17:35 -0800 | [diff] [blame] | 1239 | int delta_cc_uah = 0; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1240 | |
Xiaozhe Shi | 06b67cc | 2013-03-29 12:07:40 -0700 | [diff] [blame] | 1241 | /* |
| 1242 | * use the battery current if called too quickly |
| 1243 | */ |
| 1244 | if (delta_time_s < IAVG_MINIMAL_TIME |
| 1245 | || chip->last_cc_uah == INT_MIN) { |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1246 | get_battery_current(chip, iavg_ua); |
| 1247 | goto out; |
| 1248 | } |
| 1249 | |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1250 | delta_cc_uah = cc_uah - chip->last_cc_uah; |
| 1251 | |
| 1252 | *iavg_ua = div_s64((s64)delta_cc_uah * 3600, delta_time_s); |
| 1253 | |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1254 | out: |
Xiaozhe Shi | f36d286 | 2013-01-04 10:17:35 -0800 | [diff] [blame] | 1255 | pr_debug("delta_cc = %d iavg_ua = %d\n", delta_cc_uah, (int)*iavg_ua); |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1256 | |
| 1257 | /* remember cc_uah */ |
| 1258 | chip->last_cc_uah = cc_uah; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1259 | } |
| 1260 | |
| 1261 | static int calculate_termination_uuc(struct qpnp_bms_chip *chip, |
| 1262 | struct soc_params *params, |
| 1263 | int batt_temp, int uuc_iavg_ma, |
| 1264 | int *ret_pc_unusable) |
| 1265 | { |
| 1266 | int unusable_uv, pc_unusable, uuc_uah; |
| 1267 | int i = 0; |
| 1268 | int ocv_mv; |
| 1269 | int batt_temp_degc = batt_temp / 10; |
| 1270 | int rbatt_mohm; |
| 1271 | int delta_uv; |
| 1272 | int prev_delta_uv = 0; |
| 1273 | int prev_rbatt_mohm = 0; |
| 1274 | int uuc_rbatt_mohm; |
| 1275 | |
| 1276 | for (i = 0; i <= 100; i++) { |
| 1277 | ocv_mv = interpolate_ocv(chip->pc_temp_ocv_lut, |
| 1278 | batt_temp_degc, i); |
| 1279 | rbatt_mohm = get_rbatt(chip, i, batt_temp); |
| 1280 | unusable_uv = (rbatt_mohm * uuc_iavg_ma) |
| 1281 | + (chip->v_cutoff_uv); |
| 1282 | delta_uv = ocv_mv * 1000 - unusable_uv; |
| 1283 | |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1284 | if (delta_uv > 0) |
| 1285 | break; |
| 1286 | |
| 1287 | prev_delta_uv = delta_uv; |
| 1288 | prev_rbatt_mohm = rbatt_mohm; |
| 1289 | } |
| 1290 | |
| 1291 | uuc_rbatt_mohm = linear_interpolate(rbatt_mohm, delta_uv, |
| 1292 | prev_rbatt_mohm, prev_delta_uv, |
| 1293 | 0); |
| 1294 | |
| 1295 | unusable_uv = (uuc_rbatt_mohm * uuc_iavg_ma) + (chip->v_cutoff_uv); |
| 1296 | |
| 1297 | pc_unusable = calculate_pc(chip, unusable_uv, batt_temp); |
| 1298 | uuc_uah = (params->fcc_uah * pc_unusable) / 100; |
Xiaozhe Shi | 794607c | 2013-02-19 10:25:59 -0800 | [diff] [blame] | 1299 | pr_debug("For uuc_iavg_ma = %d, unusable_rbatt = %d unusable_uv = %d unusable_pc = %d rbatt_pc = %d uuc = %d\n", |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1300 | uuc_iavg_ma, |
| 1301 | uuc_rbatt_mohm, unusable_uv, |
Xiaozhe Shi | 794607c | 2013-02-19 10:25:59 -0800 | [diff] [blame] | 1302 | pc_unusable, i, uuc_uah); |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1303 | *ret_pc_unusable = pc_unusable; |
| 1304 | return uuc_uah; |
| 1305 | } |
| 1306 | |
Xiaozhe Shi | f36d286 | 2013-01-04 10:17:35 -0800 | [diff] [blame] | 1307 | #define TIME_PER_PERCENT_UUC 60 |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1308 | static int adjust_uuc(struct qpnp_bms_chip *chip, |
| 1309 | struct soc_params *params, |
| 1310 | int new_pc_unusable, |
| 1311 | int new_uuc_uah, |
| 1312 | int batt_temp) |
| 1313 | { |
| 1314 | int new_unusable_mv, new_iavg_ma; |
| 1315 | int batt_temp_degc = batt_temp / 10; |
Xiaozhe Shi | f36d286 | 2013-01-04 10:17:35 -0800 | [diff] [blame] | 1316 | int max_percent_change; |
| 1317 | |
| 1318 | max_percent_change = max(params->delta_time_s |
| 1319 | / TIME_PER_PERCENT_UUC, 1); |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1320 | |
| 1321 | if (chip->prev_pc_unusable == -EINVAL |
Xiaozhe Shi | f36d286 | 2013-01-04 10:17:35 -0800 | [diff] [blame] | 1322 | || abs(chip->prev_pc_unusable - new_pc_unusable) |
| 1323 | <= max_percent_change) { |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1324 | chip->prev_pc_unusable = new_pc_unusable; |
| 1325 | return new_uuc_uah; |
| 1326 | } |
| 1327 | |
| 1328 | /* the uuc is trying to change more than 1% restrict it */ |
| 1329 | if (new_pc_unusable > chip->prev_pc_unusable) |
Xiaozhe Shi | f36d286 | 2013-01-04 10:17:35 -0800 | [diff] [blame] | 1330 | chip->prev_pc_unusable += max_percent_change; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1331 | else |
Xiaozhe Shi | f36d286 | 2013-01-04 10:17:35 -0800 | [diff] [blame] | 1332 | chip->prev_pc_unusable -= max_percent_change; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1333 | |
| 1334 | new_uuc_uah = (params->fcc_uah * chip->prev_pc_unusable) / 100; |
| 1335 | |
| 1336 | /* also find update the iavg_ma accordingly */ |
| 1337 | new_unusable_mv = interpolate_ocv(chip->pc_temp_ocv_lut, |
| 1338 | batt_temp_degc, chip->prev_pc_unusable); |
| 1339 | if (new_unusable_mv < chip->v_cutoff_uv/1000) |
| 1340 | new_unusable_mv = chip->v_cutoff_uv/1000; |
| 1341 | |
| 1342 | new_iavg_ma = (new_unusable_mv * 1000 - chip->v_cutoff_uv) |
Xiaozhe Shi | 904f1f7 | 2012-12-04 12:47:21 -0800 | [diff] [blame] | 1343 | / params->rbatt_mohm; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1344 | if (new_iavg_ma == 0) |
| 1345 | new_iavg_ma = 1; |
| 1346 | chip->prev_uuc_iavg_ma = new_iavg_ma; |
| 1347 | pr_debug("Restricting UUC to %d (%d%%) unusable_mv = %d iavg_ma = %d\n", |
| 1348 | new_uuc_uah, chip->prev_pc_unusable, |
| 1349 | new_unusable_mv, new_iavg_ma); |
| 1350 | |
| 1351 | return new_uuc_uah; |
| 1352 | } |
| 1353 | |
Abhijeet Dharmapurikar | bdf8ba8 | 2012-12-20 18:33:56 -0800 | [diff] [blame] | 1354 | #define MIN_IAVG_MA 250 |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1355 | static int calculate_unusable_charge_uah(struct qpnp_bms_chip *chip, |
| 1356 | struct soc_params *params, |
| 1357 | int batt_temp) |
| 1358 | { |
| 1359 | int uuc_uah_iavg; |
| 1360 | int i; |
| 1361 | int uuc_iavg_ma = params->iavg_ua / 1000; |
| 1362 | int pc_unusable; |
| 1363 | |
| 1364 | /* |
| 1365 | * if called first time, fill all the samples with |
| 1366 | * the shutdown_iavg_ma |
| 1367 | */ |
| 1368 | if (chip->first_time_calc_uuc && chip->shutdown_iavg_ma != 0) { |
| 1369 | pr_debug("Using shutdown_iavg_ma = %d in all samples\n", |
| 1370 | chip->shutdown_iavg_ma); |
| 1371 | for (i = 0; i < IAVG_SAMPLES; i++) |
| 1372 | chip->iavg_samples_ma[i] = chip->shutdown_iavg_ma; |
| 1373 | |
| 1374 | chip->iavg_index = 0; |
| 1375 | chip->iavg_num_samples = IAVG_SAMPLES; |
| 1376 | } |
| 1377 | |
Xiaozhe Shi | 7063392 | 2013-09-23 15:50:53 -0700 | [diff] [blame] | 1378 | if (params->delta_time_s >= IAVG_MINIMAL_TIME) { |
| 1379 | /* |
| 1380 | * if charging use a nominal avg current to keep |
| 1381 | * a reasonable UUC while charging |
| 1382 | */ |
| 1383 | if (uuc_iavg_ma < MIN_IAVG_MA) |
| 1384 | uuc_iavg_ma = MIN_IAVG_MA; |
| 1385 | chip->iavg_samples_ma[chip->iavg_index] = uuc_iavg_ma; |
| 1386 | chip->iavg_index = (chip->iavg_index + 1) % IAVG_SAMPLES; |
| 1387 | chip->iavg_num_samples++; |
| 1388 | if (chip->iavg_num_samples >= IAVG_SAMPLES) |
| 1389 | chip->iavg_num_samples = IAVG_SAMPLES; |
| 1390 | } |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1391 | |
| 1392 | /* now that this sample is added calcualte the average */ |
| 1393 | uuc_iavg_ma = 0; |
| 1394 | if (chip->iavg_num_samples != 0) { |
| 1395 | for (i = 0; i < chip->iavg_num_samples; i++) { |
| 1396 | pr_debug("iavg_samples_ma[%d] = %d\n", i, |
| 1397 | chip->iavg_samples_ma[i]); |
| 1398 | uuc_iavg_ma += chip->iavg_samples_ma[i]; |
| 1399 | } |
| 1400 | |
| 1401 | uuc_iavg_ma = DIV_ROUND_CLOSEST(uuc_iavg_ma, |
| 1402 | chip->iavg_num_samples); |
| 1403 | } |
| 1404 | |
Xiaozhe Shi | 20640b5 | 2013-01-03 11:49:30 -0800 | [diff] [blame] | 1405 | /* |
| 1406 | * if we're in bms reset mode, force uuc to be 3% of fcc |
| 1407 | */ |
| 1408 | if (bms_reset) |
| 1409 | return (params->fcc_uah * 3) / 100; |
| 1410 | |
Xiaozhe Shi | 75e5efe | 2013-02-07 09:51:43 -0800 | [diff] [blame] | 1411 | uuc_uah_iavg = calculate_termination_uuc(chip, params, batt_temp, |
| 1412 | uuc_iavg_ma, &pc_unusable); |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1413 | pr_debug("uuc_iavg_ma = %d uuc with iavg = %d\n", |
| 1414 | uuc_iavg_ma, uuc_uah_iavg); |
| 1415 | |
| 1416 | chip->prev_uuc_iavg_ma = uuc_iavg_ma; |
| 1417 | /* restrict the uuc such that it can increase only by one percent */ |
| 1418 | uuc_uah_iavg = adjust_uuc(chip, params, pc_unusable, |
| 1419 | uuc_uah_iavg, batt_temp); |
| 1420 | |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1421 | return uuc_uah_iavg; |
| 1422 | } |
| 1423 | |
Xiaozhe Shi | d9ffdaf | 2013-09-19 16:23:21 -0700 | [diff] [blame] | 1424 | static s64 find_ocv_charge_for_soc(struct qpnp_bms_chip *chip, |
| 1425 | struct soc_params *params, int soc) |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1426 | { |
Xiaozhe Shi | d9ffdaf | 2013-09-19 16:23:21 -0700 | [diff] [blame] | 1427 | return div_s64((s64)soc * (params->fcc_uah - params->uuc_uah), |
| 1428 | 100) + params->cc_uah + params->uuc_uah; |
| 1429 | } |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1430 | |
Xiaozhe Shi | d9ffdaf | 2013-09-19 16:23:21 -0700 | [diff] [blame] | 1431 | static int find_pc_for_soc(struct qpnp_bms_chip *chip, |
| 1432 | struct soc_params *params, int soc) |
| 1433 | { |
| 1434 | int ocv_charge_uah = find_ocv_charge_for_soc(chip, params, soc); |
| 1435 | int pc; |
| 1436 | |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1437 | pc = DIV_ROUND_CLOSEST((int)ocv_charge_uah * 100, params->fcc_uah); |
| 1438 | pc = clamp(pc, 0, 100); |
Xiaozhe Shi | d9ffdaf | 2013-09-19 16:23:21 -0700 | [diff] [blame] | 1439 | pr_debug("soc = %d, fcc = %d uuc = %d rc = %d pc = %d\n", |
| 1440 | soc, params->fcc_uah, params->uuc_uah, |
| 1441 | ocv_charge_uah, pc); |
| 1442 | return pc; |
| 1443 | } |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1444 | |
Xiaozhe Shi | f36d286 | 2013-01-04 10:17:35 -0800 | [diff] [blame] | 1445 | static int get_current_time(unsigned long *now_tm_sec) |
| 1446 | { |
| 1447 | struct rtc_time tm; |
| 1448 | struct rtc_device *rtc; |
| 1449 | int rc; |
| 1450 | |
| 1451 | rtc = rtc_class_open(CONFIG_RTC_HCTOSYS_DEVICE); |
| 1452 | if (rtc == NULL) { |
| 1453 | pr_err("%s: unable to open rtc device (%s)\n", |
| 1454 | __FILE__, CONFIG_RTC_HCTOSYS_DEVICE); |
Xiaozhe Shi | 0e01af6 | 2013-05-06 12:56:08 -0700 | [diff] [blame] | 1455 | return -EINVAL; |
Xiaozhe Shi | f36d286 | 2013-01-04 10:17:35 -0800 | [diff] [blame] | 1456 | } |
| 1457 | |
| 1458 | rc = rtc_read_time(rtc, &tm); |
| 1459 | if (rc) { |
| 1460 | pr_err("Error reading rtc device (%s) : %d\n", |
| 1461 | CONFIG_RTC_HCTOSYS_DEVICE, rc); |
| 1462 | goto close_time; |
| 1463 | } |
| 1464 | |
| 1465 | rc = rtc_valid_tm(&tm); |
| 1466 | if (rc) { |
| 1467 | pr_err("Invalid RTC time (%s): %d\n", |
| 1468 | CONFIG_RTC_HCTOSYS_DEVICE, rc); |
| 1469 | goto close_time; |
| 1470 | } |
| 1471 | rtc_tm_to_time(&tm, now_tm_sec); |
| 1472 | |
| 1473 | close_time: |
| 1474 | rtc_class_close(rtc); |
| 1475 | return rc; |
| 1476 | } |
| 1477 | |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 1478 | /* Returns estimated battery resistance */ |
| 1479 | static int get_prop_bms_batt_resistance(struct qpnp_bms_chip *chip) |
| 1480 | { |
| 1481 | return chip->rbatt_mohm * 1000; |
| 1482 | } |
| 1483 | |
| 1484 | /* Returns instantaneous current in uA */ |
| 1485 | static int get_prop_bms_current_now(struct qpnp_bms_chip *chip) |
| 1486 | { |
| 1487 | int rc, result_ua; |
| 1488 | |
| 1489 | rc = get_battery_current(chip, &result_ua); |
| 1490 | if (rc) { |
| 1491 | pr_err("failed to get current: %d\n", rc); |
| 1492 | return rc; |
| 1493 | } |
| 1494 | return result_ua; |
| 1495 | } |
| 1496 | |
| 1497 | /* Returns coulomb counter in uAh */ |
| 1498 | static int get_prop_bms_charge_counter(struct qpnp_bms_chip *chip) |
| 1499 | { |
| 1500 | int64_t cc_raw; |
| 1501 | |
| 1502 | mutex_lock(&chip->bms_output_lock); |
| 1503 | lock_output_data(chip); |
| 1504 | read_cc_raw(chip, &cc_raw, false); |
| 1505 | unlock_output_data(chip); |
| 1506 | mutex_unlock(&chip->bms_output_lock); |
| 1507 | |
| 1508 | return calculate_cc(chip, cc_raw, CC, NORESET); |
| 1509 | } |
| 1510 | |
| 1511 | /* Returns shadow coulomb counter in uAh */ |
| 1512 | static int get_prop_bms_charge_counter_shadow(struct qpnp_bms_chip *chip) |
| 1513 | { |
| 1514 | int64_t cc_raw; |
| 1515 | |
| 1516 | mutex_lock(&chip->bms_output_lock); |
| 1517 | lock_output_data(chip); |
| 1518 | read_cc_raw(chip, &cc_raw, true); |
| 1519 | unlock_output_data(chip); |
| 1520 | mutex_unlock(&chip->bms_output_lock); |
| 1521 | |
| 1522 | return calculate_cc(chip, cc_raw, SHDW_CC, NORESET); |
| 1523 | } |
| 1524 | |
| 1525 | /* Returns full charge design in uAh */ |
| 1526 | static int get_prop_bms_charge_full_design(struct qpnp_bms_chip *chip) |
| 1527 | { |
| 1528 | return chip->fcc_mah * 1000; |
| 1529 | } |
| 1530 | |
Anirudh Ghayal | c9d981a | 2013-06-24 09:50:33 +0530 | [diff] [blame] | 1531 | /* Returns the current full charge in uAh */ |
| 1532 | static int get_prop_bms_charge_full(struct qpnp_bms_chip *chip) |
| 1533 | { |
| 1534 | int rc; |
| 1535 | struct qpnp_vadc_result result; |
| 1536 | |
Siddartha Mohanadoss | 3cb2b6b | 2013-06-21 12:07:05 -0700 | [diff] [blame] | 1537 | rc = qpnp_vadc_read(chip->vadc_dev, LR_MUX1_BATT_THERM, &result); |
Anirudh Ghayal | c9d981a | 2013-06-24 09:50:33 +0530 | [diff] [blame] | 1538 | if (rc) { |
| 1539 | pr_err("Unable to read battery temperature\n"); |
| 1540 | return rc; |
| 1541 | } |
| 1542 | |
| 1543 | return calculate_fcc(chip, (int)result.physical); |
| 1544 | } |
| 1545 | |
Xiaozhe Shi | 04da099 | 2013-04-26 16:32:14 -0700 | [diff] [blame] | 1546 | static int calculate_delta_time(unsigned long *time_stamp, int *delta_time_s) |
Xiaozhe Shi | f36d286 | 2013-01-04 10:17:35 -0800 | [diff] [blame] | 1547 | { |
| 1548 | unsigned long now_tm_sec = 0; |
| 1549 | |
| 1550 | /* default to delta time = 0 if anything fails */ |
| 1551 | *delta_time_s = 0; |
| 1552 | |
Xiaozhe Shi | 04da099 | 2013-04-26 16:32:14 -0700 | [diff] [blame] | 1553 | if (get_current_time(&now_tm_sec)) { |
| 1554 | pr_err("RTC read failed\n"); |
| 1555 | return 0; |
| 1556 | } |
Xiaozhe Shi | f36d286 | 2013-01-04 10:17:35 -0800 | [diff] [blame] | 1557 | |
Xiaozhe Shi | 04da099 | 2013-04-26 16:32:14 -0700 | [diff] [blame] | 1558 | *delta_time_s = (now_tm_sec - *time_stamp); |
Xiaozhe Shi | f36d286 | 2013-01-04 10:17:35 -0800 | [diff] [blame] | 1559 | |
| 1560 | /* remember this time */ |
Xiaozhe Shi | 04da099 | 2013-04-26 16:32:14 -0700 | [diff] [blame] | 1561 | *time_stamp = now_tm_sec; |
Xiaozhe Shi | f36d286 | 2013-01-04 10:17:35 -0800 | [diff] [blame] | 1562 | return 0; |
| 1563 | } |
| 1564 | |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1565 | static void calculate_soc_params(struct qpnp_bms_chip *chip, |
| 1566 | struct raw_soc_params *raw, |
| 1567 | struct soc_params *params, |
| 1568 | int batt_temp) |
| 1569 | { |
Xiaozhe Shi | 219cb22 | 2013-06-10 15:49:59 -0700 | [diff] [blame] | 1570 | int soc_rbatt, shdw_cc_uah; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1571 | |
Xiaozhe Shi | 04da099 | 2013-04-26 16:32:14 -0700 | [diff] [blame] | 1572 | calculate_delta_time(&chip->tm_sec, ¶ms->delta_time_s); |
| 1573 | pr_debug("tm_sec = %ld, delta_s = %d\n", |
| 1574 | chip->tm_sec, params->delta_time_s); |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1575 | params->fcc_uah = calculate_fcc(chip, batt_temp); |
| 1576 | pr_debug("FCC = %uuAh batt_temp = %d\n", params->fcc_uah, batt_temp); |
| 1577 | |
| 1578 | /* calculate remainging charge */ |
| 1579 | params->ocv_charge_uah = calculate_ocv_charge( |
| 1580 | chip, raw, |
Abhijeet Dharmapurikar | 4b97cdd | 2012-12-26 21:10:53 -0800 | [diff] [blame] | 1581 | params->fcc_uah); |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1582 | pr_debug("ocv_charge_uah = %uuAh\n", params->ocv_charge_uah); |
| 1583 | |
| 1584 | /* calculate cc micro_volt_hour */ |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 1585 | params->cc_uah = calculate_cc(chip, raw->cc, CC, RESET); |
Xiaozhe Shi | 219cb22 | 2013-06-10 15:49:59 -0700 | [diff] [blame] | 1586 | shdw_cc_uah = calculate_cc(chip, raw->shdw_cc, SHDW_CC, RESET); |
| 1587 | pr_debug("cc_uah = %duAh raw->cc = %llx, shdw_cc_uah = %duAh raw->shdw_cc = %llx\n", |
| 1588 | params->cc_uah, raw->cc, |
| 1589 | shdw_cc_uah, raw->shdw_cc); |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1590 | |
| 1591 | soc_rbatt = ((params->ocv_charge_uah - params->cc_uah) * 100) |
| 1592 | / params->fcc_uah; |
| 1593 | if (soc_rbatt < 0) |
| 1594 | soc_rbatt = 0; |
Xiaozhe Shi | 904f1f7 | 2012-12-04 12:47:21 -0800 | [diff] [blame] | 1595 | params->rbatt_mohm = get_rbatt(chip, soc_rbatt, batt_temp); |
Xiaozhe Shi | 794607c | 2013-02-19 10:25:59 -0800 | [diff] [blame] | 1596 | pr_debug("rbatt_mohm = %d\n", params->rbatt_mohm); |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1597 | |
Xiaozhe Shi | 1e87cda | 2013-05-17 10:18:56 -0700 | [diff] [blame] | 1598 | if (params->rbatt_mohm != chip->rbatt_mohm) { |
Xiaozhe Shi | 6dc56f1 | 2013-05-02 15:56:55 -0700 | [diff] [blame] | 1599 | chip->rbatt_mohm = params->rbatt_mohm; |
Abhijeet Dharmapurikar | 8e32249 | 2013-06-25 19:48:18 -0700 | [diff] [blame] | 1600 | if (chip->bms_psy_registered) |
Xiaozhe Shi | 1e87cda | 2013-05-17 10:18:56 -0700 | [diff] [blame] | 1601 | power_supply_changed(&chip->bms_psy); |
Xiaozhe Shi | 6dc56f1 | 2013-05-02 15:56:55 -0700 | [diff] [blame] | 1602 | } |
| 1603 | |
Xiaozhe Shi | f36d286 | 2013-01-04 10:17:35 -0800 | [diff] [blame] | 1604 | calculate_iavg(chip, params->cc_uah, ¶ms->iavg_ua, |
| 1605 | params->delta_time_s); |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 1606 | |
| 1607 | params->uuc_uah = calculate_unusable_charge_uah(chip, params, |
| 1608 | batt_temp); |
| 1609 | pr_debug("UUC = %uuAh\n", params->uuc_uah); |
| 1610 | } |
| 1611 | |
Xiaozhe Shi | 7edde5d | 2012-09-26 11:23:09 -0700 | [diff] [blame] | 1612 | static int bound_soc(int soc) |
| 1613 | { |
| 1614 | soc = max(0, soc); |
| 1615 | soc = min(100, soc); |
| 1616 | return soc; |
| 1617 | } |
| 1618 | |
Xiaozhe Shi | 20640b5 | 2013-01-03 11:49:30 -0800 | [diff] [blame] | 1619 | #define IBAT_TOL_MASK 0x0F |
| 1620 | #define OCV_TOL_MASK 0xF0 |
| 1621 | #define IBAT_TOL_DEFAULT 0x03 |
| 1622 | #define IBAT_TOL_NOCHG 0x0F |
| 1623 | #define OCV_TOL_DEFAULT 0x20 |
| 1624 | #define OCV_TOL_NO_OCV 0x00 |
| 1625 | static int stop_ocv_updates(struct qpnp_bms_chip *chip) |
| 1626 | { |
| 1627 | pr_debug("stopping ocv updates\n"); |
| 1628 | return qpnp_masked_write(chip, BMS1_TOL_CTL, |
| 1629 | OCV_TOL_MASK, OCV_TOL_NO_OCV); |
| 1630 | } |
| 1631 | |
| 1632 | static int reset_bms_for_test(struct qpnp_bms_chip *chip) |
| 1633 | { |
Xiaozhe Shi | 95da77f | 2013-02-20 13:40:06 -0800 | [diff] [blame] | 1634 | int ibat_ua = 0, vbat_uv = 0, rc; |
Xiaozhe Shi | 20640b5 | 2013-01-03 11:49:30 -0800 | [diff] [blame] | 1635 | int ocv_est_uv; |
| 1636 | |
| 1637 | if (!chip) { |
| 1638 | pr_err("BMS driver has not been initialized yet!\n"); |
| 1639 | return -EINVAL; |
| 1640 | } |
| 1641 | |
| 1642 | rc = get_simultaneous_batt_v_and_i(chip, &ibat_ua, &vbat_uv); |
| 1643 | |
Xiaozhe Shi | 1a10aff | 2013-04-01 15:40:05 -0700 | [diff] [blame] | 1644 | /* |
| 1645 | * Don't include rbatt and rbatt_capacitative since we expect this to |
| 1646 | * be used with a fake battery which does not have internal resistances |
| 1647 | */ |
Xiaozhe Shi | 20640b5 | 2013-01-03 11:49:30 -0800 | [diff] [blame] | 1648 | ocv_est_uv = vbat_uv + (ibat_ua * chip->r_conn_mohm) / 1000; |
| 1649 | pr_debug("forcing ocv to be %d due to bms reset mode\n", ocv_est_uv); |
| 1650 | chip->last_ocv_uv = ocv_est_uv; |
Xiaozhe Shi | 04da099 | 2013-04-26 16:32:14 -0700 | [diff] [blame] | 1651 | mutex_lock(&chip->last_soc_mutex); |
Xiaozhe Shi | 20640b5 | 2013-01-03 11:49:30 -0800 | [diff] [blame] | 1652 | chip->last_soc = -EINVAL; |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 1653 | chip->last_soc_invalid = true; |
Xiaozhe Shi | 04da099 | 2013-04-26 16:32:14 -0700 | [diff] [blame] | 1654 | mutex_unlock(&chip->last_soc_mutex); |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 1655 | reset_cc(chip, CLEAR_CC | CLEAR_SHDW_CC); |
Xiaozhe Shi | 80ba88d | 2013-04-05 10:23:34 -0700 | [diff] [blame] | 1656 | chip->software_cc_uah = 0; |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 1657 | chip->software_shdw_cc_uah = 0; |
Xiaozhe Shi | 20640b5 | 2013-01-03 11:49:30 -0800 | [diff] [blame] | 1658 | chip->last_cc_uah = INT_MIN; |
| 1659 | stop_ocv_updates(chip); |
| 1660 | |
| 1661 | pr_debug("bms reset to ocv = %duv vbat_ua = %d ibat_ua = %d\n", |
| 1662 | chip->last_ocv_uv, vbat_uv, ibat_ua); |
| 1663 | |
| 1664 | return rc; |
| 1665 | } |
| 1666 | |
| 1667 | static int bms_reset_set(const char *val, const struct kernel_param *kp) |
| 1668 | { |
| 1669 | int rc; |
| 1670 | |
| 1671 | rc = param_set_bool(val, kp); |
| 1672 | if (rc) { |
| 1673 | pr_err("Unable to set bms_reset: %d\n", rc); |
| 1674 | return rc; |
| 1675 | } |
| 1676 | |
| 1677 | if (*(bool *)kp->arg) { |
| 1678 | struct power_supply *bms_psy = power_supply_get_by_name("bms"); |
| 1679 | struct qpnp_bms_chip *chip = container_of(bms_psy, |
| 1680 | struct qpnp_bms_chip, bms_psy); |
| 1681 | |
| 1682 | rc = reset_bms_for_test(chip); |
| 1683 | if (rc) { |
| 1684 | pr_err("Unable to modify bms_reset: %d\n", rc); |
| 1685 | return rc; |
| 1686 | } |
| 1687 | } |
| 1688 | return 0; |
| 1689 | } |
| 1690 | |
| 1691 | static struct kernel_param_ops bms_reset_ops = { |
| 1692 | .set = bms_reset_set, |
| 1693 | .get = param_get_bool, |
| 1694 | }; |
| 1695 | |
| 1696 | module_param_cb(bms_reset, &bms_reset_ops, &bms_reset, 0644); |
| 1697 | |
Xiaozhe Shi | 12b25be | 2013-08-29 11:51:59 -0700 | [diff] [blame] | 1698 | #define SOC_STORAGE_MASK 0xFE |
Xiaozhe Shi | 83484e3 | 2013-05-16 10:59:59 -0700 | [diff] [blame] | 1699 | static void backup_soc_and_iavg(struct qpnp_bms_chip *chip, int batt_temp, |
| 1700 | int soc) |
| 1701 | { |
| 1702 | u8 temp; |
| 1703 | int rc; |
| 1704 | int iavg_ma = chip->prev_uuc_iavg_ma; |
| 1705 | |
Xiaozhe Shi | 68a1bb2 | 2013-09-23 14:52:00 -0700 | [diff] [blame] | 1706 | if (iavg_ma > MIN_IAVG_MA) |
| 1707 | temp = (iavg_ma - MIN_IAVG_MA) / IAVG_STEP_SIZE_MA; |
Xiaozhe Shi | 83484e3 | 2013-05-16 10:59:59 -0700 | [diff] [blame] | 1708 | else |
| 1709 | temp = 0; |
| 1710 | |
Xiaozhe Shi | 12b25be | 2013-08-29 11:51:59 -0700 | [diff] [blame] | 1711 | rc = qpnp_write_wrapper(chip, &temp, chip->base + IAVG_STORAGE_REG, 1); |
Xiaozhe Shi | 83484e3 | 2013-05-16 10:59:59 -0700 | [diff] [blame] | 1712 | |
Xiaozhe Shi | e945a8a | 2013-11-11 10:20:14 -0800 | [diff] [blame] | 1713 | /* store an invalid soc if temperature is below 5degC */ |
Xiaozhe Shi | 83484e3 | 2013-05-16 10:59:59 -0700 | [diff] [blame] | 1714 | if (batt_temp > IGNORE_SOC_TEMP_DECIDEG) |
Xiaozhe Shi | 12b25be | 2013-08-29 11:51:59 -0700 | [diff] [blame] | 1715 | qpnp_masked_write_base(chip, chip->soc_storage_addr, |
| 1716 | SOC_STORAGE_MASK, (soc + 1) << 1); |
Xiaozhe Shi | e945a8a | 2013-11-11 10:20:14 -0800 | [diff] [blame] | 1717 | else |
| 1718 | qpnp_masked_write_base(chip, chip->soc_storage_addr, |
| 1719 | SOC_STORAGE_MASK, SOC_STORAGE_MASK); |
Xiaozhe Shi | 83484e3 | 2013-05-16 10:59:59 -0700 | [diff] [blame] | 1720 | } |
| 1721 | |
| 1722 | static int scale_soc_while_chg(struct qpnp_bms_chip *chip, int chg_time_sec, |
| 1723 | int catch_up_sec, int new_soc, int prev_soc) |
| 1724 | { |
| 1725 | int scaled_soc; |
| 1726 | int numerator; |
| 1727 | |
| 1728 | /* |
| 1729 | * Don't report a high value immediately slowly scale the |
| 1730 | * value from prev_soc to the new soc based on a charge time |
| 1731 | * weighted average |
| 1732 | */ |
| 1733 | pr_debug("cts = %d catch_up_sec = %d\n", chg_time_sec, catch_up_sec); |
| 1734 | if (catch_up_sec == 0) |
| 1735 | return new_soc; |
| 1736 | |
| 1737 | if (chg_time_sec > catch_up_sec) |
| 1738 | return new_soc; |
| 1739 | |
| 1740 | numerator = (catch_up_sec - chg_time_sec) * prev_soc |
| 1741 | + chg_time_sec * new_soc; |
| 1742 | scaled_soc = numerator / catch_up_sec; |
| 1743 | |
| 1744 | pr_debug("cts = %d new_soc = %d prev_soc = %d scaled_soc = %d\n", |
| 1745 | chg_time_sec, new_soc, prev_soc, scaled_soc); |
| 1746 | |
| 1747 | return scaled_soc; |
| 1748 | } |
| 1749 | |
| 1750 | /* |
| 1751 | * bms_fake_battery is set in setups where a battery emulator is used instead |
| 1752 | * of a real battery. This makes the bms driver report a different/fake value |
| 1753 | * regardless of the calculated state of charge. |
| 1754 | */ |
| 1755 | static int bms_fake_battery = -EINVAL; |
| 1756 | module_param(bms_fake_battery, int, 0644); |
| 1757 | |
| 1758 | static int report_voltage_based_soc(struct qpnp_bms_chip *chip) |
| 1759 | { |
| 1760 | pr_debug("Reported voltage based soc = %d\n", |
| 1761 | chip->prev_voltage_based_soc); |
| 1762 | return chip->prev_voltage_based_soc; |
| 1763 | } |
| 1764 | |
| 1765 | #define SOC_CATCHUP_SEC_MAX 600 |
| 1766 | #define SOC_CATCHUP_SEC_PER_PERCENT 60 |
| 1767 | #define MAX_CATCHUP_SOC (SOC_CATCHUP_SEC_MAX / SOC_CATCHUP_SEC_PER_PERCENT) |
Xiaozhe Shi | e7fafe6 | 2013-06-05 15:25:16 -0700 | [diff] [blame] | 1768 | #define SOC_CHANGE_PER_SEC 5 |
Xiaozhe Shi | 2737582 | 2013-08-22 11:40:15 -0700 | [diff] [blame] | 1769 | #define REPORT_SOC_WAIT_MS 10000 |
Xiaozhe Shi | 83484e3 | 2013-05-16 10:59:59 -0700 | [diff] [blame] | 1770 | static int report_cc_based_soc(struct qpnp_bms_chip *chip) |
| 1771 | { |
| 1772 | int soc, soc_change; |
| 1773 | int time_since_last_change_sec, charge_time_sec = 0; |
| 1774 | unsigned long last_change_sec; |
| 1775 | struct timespec now; |
| 1776 | struct qpnp_vadc_result result; |
| 1777 | int batt_temp; |
| 1778 | int rc; |
| 1779 | bool charging, charging_since_last_report; |
| 1780 | |
Xiaozhe Shi | 2737582 | 2013-08-22 11:40:15 -0700 | [diff] [blame] | 1781 | rc = wait_event_interruptible_timeout(chip->bms_wait_queue, |
| 1782 | chip->calculated_soc != -EINVAL, |
| 1783 | round_jiffies_relative(msecs_to_jiffies |
| 1784 | (REPORT_SOC_WAIT_MS))); |
| 1785 | |
| 1786 | if (rc == 0 && chip->calculated_soc == -EINVAL) { |
| 1787 | pr_debug("calculate soc timed out\n"); |
| 1788 | } else if (rc == -ERESTARTSYS) { |
| 1789 | pr_err("Wait for SoC interrupted.\n"); |
| 1790 | return rc; |
| 1791 | } |
| 1792 | |
Siddartha Mohanadoss | 3cb2b6b | 2013-06-21 12:07:05 -0700 | [diff] [blame] | 1793 | rc = qpnp_vadc_read(chip->vadc_dev, LR_MUX1_BATT_THERM, &result); |
Xiaozhe Shi | 83484e3 | 2013-05-16 10:59:59 -0700 | [diff] [blame] | 1794 | |
| 1795 | if (rc) { |
| 1796 | pr_err("error reading adc channel = %d, rc = %d\n", |
| 1797 | LR_MUX1_BATT_THERM, rc); |
| 1798 | return rc; |
| 1799 | } |
| 1800 | pr_debug("batt_temp phy = %lld meas = 0x%llx\n", result.physical, |
| 1801 | result.measurement); |
| 1802 | batt_temp = (int)result.physical; |
| 1803 | |
| 1804 | mutex_lock(&chip->last_soc_mutex); |
Xiaozhe Shi | fa6ea69 | 2013-05-31 11:15:13 -0700 | [diff] [blame] | 1805 | soc = chip->calculated_soc; |
| 1806 | |
Xiaozhe Shi | 83484e3 | 2013-05-16 10:59:59 -0700 | [diff] [blame] | 1807 | last_change_sec = chip->last_soc_change_sec; |
| 1808 | calculate_delta_time(&last_change_sec, &time_since_last_change_sec); |
| 1809 | |
| 1810 | charging = is_battery_charging(chip); |
| 1811 | charging_since_last_report = charging || (chip->last_soc_unbound |
| 1812 | && chip->was_charging_at_sleep); |
| 1813 | /* |
| 1814 | * account for charge time - limit it to SOC_CATCHUP_SEC to |
| 1815 | * avoid overflows when charging continues for extended periods |
| 1816 | */ |
| 1817 | if (charging) { |
| 1818 | if (chip->charge_start_tm_sec == 0) { |
| 1819 | /* |
| 1820 | * calculating soc for the first time |
| 1821 | * after start of chg. Initialize catchup time |
| 1822 | */ |
| 1823 | if (abs(soc - chip->last_soc) < MAX_CATCHUP_SOC) |
| 1824 | chip->catch_up_time_sec = |
| 1825 | (soc - chip->last_soc) |
| 1826 | * SOC_CATCHUP_SEC_PER_PERCENT; |
| 1827 | else |
| 1828 | chip->catch_up_time_sec = SOC_CATCHUP_SEC_MAX; |
| 1829 | |
| 1830 | if (chip->catch_up_time_sec < 0) |
| 1831 | chip->catch_up_time_sec = 0; |
| 1832 | chip->charge_start_tm_sec = last_change_sec; |
| 1833 | } |
| 1834 | |
| 1835 | charge_time_sec = min(SOC_CATCHUP_SEC_MAX, (int)last_change_sec |
| 1836 | - chip->charge_start_tm_sec); |
| 1837 | |
| 1838 | /* end catchup if calculated soc and last soc are same */ |
| 1839 | if (chip->last_soc == soc) |
| 1840 | chip->catch_up_time_sec = 0; |
| 1841 | } |
| 1842 | |
| 1843 | if (chip->last_soc != -EINVAL) { |
| 1844 | /* |
| 1845 | * last_soc < soc ... if we have not been charging at all |
| 1846 | * since the last time this was called, report previous SoC. |
| 1847 | * Otherwise, scale and catch up. |
| 1848 | */ |
| 1849 | if (chip->last_soc < soc && !charging_since_last_report) |
| 1850 | soc = chip->last_soc; |
| 1851 | else if (chip->last_soc < soc && soc != 100) |
| 1852 | soc = scale_soc_while_chg(chip, charge_time_sec, |
| 1853 | chip->catch_up_time_sec, |
| 1854 | soc, chip->last_soc); |
| 1855 | |
Xiaozhe Shi | bd56b05 | 2013-10-21 11:51:30 -0700 | [diff] [blame] | 1856 | /* if the battery is close to cutoff allow more change */ |
| 1857 | if (wake_lock_active(&chip->low_voltage_wake_lock)) |
| 1858 | soc_change = min((int)abs(chip->last_soc - soc), |
| 1859 | time_since_last_change_sec); |
| 1860 | else |
| 1861 | soc_change = min((int)abs(chip->last_soc - soc), |
| 1862 | time_since_last_change_sec |
| 1863 | / SOC_CHANGE_PER_SEC); |
| 1864 | |
Xiaozhe Shi | 83484e3 | 2013-05-16 10:59:59 -0700 | [diff] [blame] | 1865 | if (chip->last_soc_unbound) { |
| 1866 | chip->last_soc_unbound = false; |
| 1867 | } else { |
| 1868 | /* |
| 1869 | * if soc have not been unbound by resume, |
| 1870 | * only change reported SoC by 1. |
| 1871 | */ |
| 1872 | soc_change = min(1, soc_change); |
| 1873 | } |
| 1874 | |
| 1875 | if (soc < chip->last_soc && soc != 0) |
| 1876 | soc = chip->last_soc - soc_change; |
| 1877 | if (soc > chip->last_soc && soc != 100) |
| 1878 | soc = chip->last_soc + soc_change; |
| 1879 | } |
| 1880 | |
Xiaozhe Shi | 208b8e5 | 2013-05-28 10:16:32 -0700 | [diff] [blame] | 1881 | if (chip->last_soc != soc && !chip->last_soc_unbound) |
Xiaozhe Shi | 83484e3 | 2013-05-16 10:59:59 -0700 | [diff] [blame] | 1882 | chip->last_soc_change_sec = last_change_sec; |
| 1883 | |
| 1884 | pr_debug("last_soc = %d, calculated_soc = %d, soc = %d, time since last change = %d\n", |
| 1885 | chip->last_soc, chip->calculated_soc, |
| 1886 | soc, time_since_last_change_sec); |
| 1887 | chip->last_soc = bound_soc(soc); |
| 1888 | backup_soc_and_iavg(chip, batt_temp, chip->last_soc); |
| 1889 | pr_debug("Reported SOC = %d\n", chip->last_soc); |
| 1890 | chip->t_soc_queried = now; |
| 1891 | mutex_unlock(&chip->last_soc_mutex); |
| 1892 | |
| 1893 | return soc; |
| 1894 | } |
| 1895 | |
| 1896 | static int report_state_of_charge(struct qpnp_bms_chip *chip) |
| 1897 | { |
| 1898 | if (bms_fake_battery != -EINVAL) { |
| 1899 | pr_debug("Returning Fake SOC = %d%%\n", bms_fake_battery); |
| 1900 | return bms_fake_battery; |
| 1901 | } else if (chip->use_voltage_soc) |
| 1902 | return report_voltage_based_soc(chip); |
| 1903 | else |
| 1904 | return report_cc_based_soc(chip); |
| 1905 | } |
| 1906 | |
Xiaozhe Shi | ee39e5d | 2013-10-07 13:56:04 -0700 | [diff] [blame] | 1907 | #define VDD_MAX_ERR 5000 |
| 1908 | #define VDD_STEP_SIZE 10000 |
| 1909 | #define MAX_COUNT_BEFORE_RESET_TO_CC 3 |
Xiaozhe Shi | 7edde5d | 2012-09-26 11:23:09 -0700 | [diff] [blame] | 1910 | static int charging_adjustments(struct qpnp_bms_chip *chip, |
| 1911 | struct soc_params *params, int soc, |
| 1912 | int vbat_uv, int ibat_ua, int batt_temp) |
| 1913 | { |
Xiaozhe Shi | fd98ddf | 2013-05-20 15:20:19 -0700 | [diff] [blame] | 1914 | int chg_soc, soc_ibat, batt_terminal_uv, weight_ibat, weight_cc; |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 1915 | |
Xiaozhe Shi | eabcebf | 2013-05-28 10:41:09 -0700 | [diff] [blame] | 1916 | batt_terminal_uv = vbat_uv + (ibat_ua * chip->r_conn_mohm) / 1000; |
Xiaozhe Shi | 41bc1f1 | 2012-09-26 16:55:22 -0700 | [diff] [blame] | 1917 | |
| 1918 | if (chip->soc_at_cv == -EINVAL) { |
Xiaozhe Shi | eabcebf | 2013-05-28 10:41:09 -0700 | [diff] [blame] | 1919 | if (batt_terminal_uv >= chip->max_voltage_uv - VDD_MAX_ERR) { |
Xiaozhe Shi | 41bc1f1 | 2012-09-26 16:55:22 -0700 | [diff] [blame] | 1920 | chip->soc_at_cv = soc; |
| 1921 | chip->prev_chg_soc = soc; |
Xiaozhe Shi | fc7af17 | 2013-11-04 14:15:44 -0800 | [diff] [blame] | 1922 | chip->ibat_at_cv_ua = params->iavg_ua; |
Xiaozhe Shi | 41bc1f1 | 2012-09-26 16:55:22 -0700 | [diff] [blame] | 1923 | pr_debug("CC_TO_CV ibat_ua = %d CHG SOC %d\n", |
| 1924 | ibat_ua, soc); |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 1925 | } else { |
| 1926 | /* In constant current charging return the calc soc */ |
| 1927 | pr_debug("CC CHG SOC %d\n", soc); |
Xiaozhe Shi | 41bc1f1 | 2012-09-26 16:55:22 -0700 | [diff] [blame] | 1928 | } |
Xiaozhe Shi | fc2f5a0 | 2013-01-28 15:09:04 -0800 | [diff] [blame] | 1929 | |
| 1930 | chip->prev_batt_terminal_uv = batt_terminal_uv; |
Xiaozhe Shi | ee39e5d | 2013-10-07 13:56:04 -0700 | [diff] [blame] | 1931 | chip->system_load_count = 0; |
| 1932 | return soc; |
| 1933 | } else if (ibat_ua > 0 && batt_terminal_uv |
| 1934 | < chip->max_voltage_uv - (VDD_MAX_ERR * 2)) { |
| 1935 | if (chip->system_load_count > MAX_COUNT_BEFORE_RESET_TO_CC) { |
| 1936 | chip->soc_at_cv = -EINVAL; |
| 1937 | pr_debug("Vbat below CV threshold, resetting CC_TO_CV\n"); |
| 1938 | chip->system_load_count = 0; |
| 1939 | } else { |
| 1940 | chip->system_load_count += 1; |
| 1941 | pr_debug("Vbat below CV threshold, count: %d\n", |
| 1942 | chip->system_load_count); |
| 1943 | } |
| 1944 | return soc; |
| 1945 | } else if (ibat_ua > 0) { |
| 1946 | pr_debug("NOT CHARGING SOC %d\n", soc); |
| 1947 | chip->system_load_count = 0; |
| 1948 | chip->prev_chg_soc = soc; |
Xiaozhe Shi | 41bc1f1 | 2012-09-26 16:55:22 -0700 | [diff] [blame] | 1949 | return soc; |
| 1950 | } |
| 1951 | |
Xiaozhe Shi | ee39e5d | 2013-10-07 13:56:04 -0700 | [diff] [blame] | 1952 | chip->system_load_count = 0; |
Xiaozhe Shi | 41bc1f1 | 2012-09-26 16:55:22 -0700 | [diff] [blame] | 1953 | /* |
Xiaozhe Shi | fc2f5a0 | 2013-01-28 15:09:04 -0800 | [diff] [blame] | 1954 | * battery is in CV phase - begin linear interpolation of soc based on |
Xiaozhe Shi | 41bc1f1 | 2012-09-26 16:55:22 -0700 | [diff] [blame] | 1955 | * battery charge current |
| 1956 | */ |
| 1957 | |
| 1958 | /* |
| 1959 | * if voltage lessened (possibly because of a system load) |
| 1960 | * keep reporting the prev chg soc |
| 1961 | */ |
Xiaozhe Shi | eabcebf | 2013-05-28 10:41:09 -0700 | [diff] [blame] | 1962 | if (batt_terminal_uv <= chip->prev_batt_terminal_uv - VDD_STEP_SIZE) { |
Abhijeet Dharmapurikar | eef8866 | 2012-11-08 17:26:29 -0800 | [diff] [blame] | 1963 | pr_debug("batt_terminal_uv %d < (max = %d - 10000); CC CHG SOC %d\n", |
Xiaozhe Shi | fc2f5a0 | 2013-01-28 15:09:04 -0800 | [diff] [blame] | 1964 | batt_terminal_uv, chip->prev_batt_terminal_uv, |
| 1965 | chip->prev_chg_soc); |
| 1966 | chip->prev_batt_terminal_uv = batt_terminal_uv; |
Xiaozhe Shi | 41bc1f1 | 2012-09-26 16:55:22 -0700 | [diff] [blame] | 1967 | return chip->prev_chg_soc; |
| 1968 | } |
| 1969 | |
Xiaozhe Shi | fd98ddf | 2013-05-20 15:20:19 -0700 | [diff] [blame] | 1970 | soc_ibat = bound_soc(linear_interpolate(chip->soc_at_cv, |
| 1971 | chip->ibat_at_cv_ua, |
Abhijeet Dharmapurikar | eef8866 | 2012-11-08 17:26:29 -0800 | [diff] [blame] | 1972 | 100, -1 * chip->chg_term_ua, |
Xiaozhe Shi | fc7af17 | 2013-11-04 14:15:44 -0800 | [diff] [blame] | 1973 | params->iavg_ua)); |
Xiaozhe Shi | fd98ddf | 2013-05-20 15:20:19 -0700 | [diff] [blame] | 1974 | weight_ibat = bound_soc(linear_interpolate(1, chip->soc_at_cv, |
| 1975 | 100, 100, chip->prev_chg_soc)); |
| 1976 | weight_cc = 100 - weight_ibat; |
Xiaozhe Shi | eabcebf | 2013-05-28 10:41:09 -0700 | [diff] [blame] | 1977 | chg_soc = bound_soc(DIV_ROUND_CLOSEST(soc_ibat * weight_ibat |
| 1978 | + weight_cc * soc, 100)); |
| 1979 | |
Xiaozhe Shi | fd98ddf | 2013-05-20 15:20:19 -0700 | [diff] [blame] | 1980 | pr_debug("weight_ibat = %d, weight_cc = %d, soc_ibat = %d, soc_cc = %d\n", |
| 1981 | weight_ibat, weight_cc, soc_ibat, soc); |
Xiaozhe Shi | 41bc1f1 | 2012-09-26 16:55:22 -0700 | [diff] [blame] | 1982 | |
| 1983 | /* always report a higher soc */ |
| 1984 | if (chg_soc > chip->prev_chg_soc) { |
Xiaozhe Shi | 41bc1f1 | 2012-09-26 16:55:22 -0700 | [diff] [blame] | 1985 | chip->prev_chg_soc = chg_soc; |
| 1986 | |
Xiaozhe Shi | d9ffdaf | 2013-09-19 16:23:21 -0700 | [diff] [blame] | 1987 | chip->charging_adjusted_ocv = find_ocv_for_pc(chip, batt_temp, |
| 1988 | find_pc_for_soc(chip, params, chg_soc)); |
| 1989 | pr_debug("CC CHG ADJ OCV = %d CHG SOC %d\n", |
| 1990 | chip->charging_adjusted_ocv, |
Xiaozhe Shi | 41bc1f1 | 2012-09-26 16:55:22 -0700 | [diff] [blame] | 1991 | chip->prev_chg_soc); |
| 1992 | } |
| 1993 | |
| 1994 | pr_debug("Reporting CHG SOC %d\n", chip->prev_chg_soc); |
Xiaozhe Shi | fc2f5a0 | 2013-01-28 15:09:04 -0800 | [diff] [blame] | 1995 | chip->prev_batt_terminal_uv = batt_terminal_uv; |
Xiaozhe Shi | 41bc1f1 | 2012-09-26 16:55:22 -0700 | [diff] [blame] | 1996 | return chip->prev_chg_soc; |
Xiaozhe Shi | 7edde5d | 2012-09-26 11:23:09 -0700 | [diff] [blame] | 1997 | } |
| 1998 | |
Xiaozhe Shi | 4be8578 | 2013-02-22 17:33:40 -0800 | [diff] [blame] | 1999 | static void very_low_voltage_check(struct qpnp_bms_chip *chip, int vbat_uv) |
| 2000 | { |
| 2001 | /* |
| 2002 | * if battery is very low (v_cutoff voltage + 20mv) hold |
| 2003 | * a wakelock untill soc = 0% |
| 2004 | */ |
| 2005 | if (vbat_uv <= chip->low_voltage_threshold |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 2006 | && !wake_lock_active(&chip->low_voltage_wake_lock)) { |
Xiaozhe Shi | 4be8578 | 2013-02-22 17:33:40 -0800 | [diff] [blame] | 2007 | pr_debug("voltage = %d low holding wakelock\n", vbat_uv); |
| 2008 | wake_lock(&chip->low_voltage_wake_lock); |
Xiaozhe Shi | 4be8578 | 2013-02-22 17:33:40 -0800 | [diff] [blame] | 2009 | } else if (vbat_uv > chip->low_voltage_threshold |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 2010 | && wake_lock_active(&chip->low_voltage_wake_lock)) { |
Xiaozhe Shi | 4be8578 | 2013-02-22 17:33:40 -0800 | [diff] [blame] | 2011 | pr_debug("voltage = %d releasing wakelock\n", vbat_uv); |
Xiaozhe Shi | 4be8578 | 2013-02-22 17:33:40 -0800 | [diff] [blame] | 2012 | wake_unlock(&chip->low_voltage_wake_lock); |
| 2013 | } |
| 2014 | } |
| 2015 | |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 2016 | #define VBATT_ERROR_MARGIN 20000 |
| 2017 | static void cv_voltage_check(struct qpnp_bms_chip *chip, int vbat_uv) |
| 2018 | { |
| 2019 | /* |
| 2020 | * if battery is very low (v_cutoff voltage + 20mv) hold |
| 2021 | * a wakelock untill soc = 0% |
| 2022 | */ |
| 2023 | if (wake_lock_active(&chip->cv_wake_lock)) { |
| 2024 | if (chip->soc_at_cv != -EINVAL) { |
| 2025 | pr_debug("hit CV, releasing cv wakelock\n"); |
| 2026 | wake_unlock(&chip->cv_wake_lock); |
| 2027 | } else if (!is_battery_charging(chip)) { |
| 2028 | pr_debug("charging stopped, releasing cv wakelock\n"); |
| 2029 | wake_unlock(&chip->cv_wake_lock); |
| 2030 | } |
| 2031 | } else if (vbat_uv > chip->max_voltage_uv - VBATT_ERROR_MARGIN |
| 2032 | && chip->soc_at_cv == -EINVAL |
| 2033 | && is_battery_charging(chip) |
| 2034 | && !wake_lock_active(&chip->cv_wake_lock)) { |
| 2035 | pr_debug("voltage = %d holding cv wakelock\n", vbat_uv); |
| 2036 | wake_lock(&chip->cv_wake_lock); |
| 2037 | } |
| 2038 | } |
| 2039 | |
Xiaozhe Shi | 2b64787 | 2013-10-31 14:30:27 -0700 | [diff] [blame] | 2040 | #define NO_ADJUST_HIGH_SOC_THRESHOLD 98 |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 2041 | static int adjust_soc(struct qpnp_bms_chip *chip, struct soc_params *params, |
| 2042 | int soc, int batt_temp) |
| 2043 | { |
Xiaozhe Shi | 7edde5d | 2012-09-26 11:23:09 -0700 | [diff] [blame] | 2044 | int ibat_ua = 0, vbat_uv = 0; |
| 2045 | int ocv_est_uv = 0, soc_est = 0, pc_est = 0, pc = 0; |
| 2046 | int delta_ocv_uv = 0; |
| 2047 | int n = 0; |
| 2048 | int rc_new_uah = 0; |
| 2049 | int pc_new = 0; |
| 2050 | int soc_new = 0; |
| 2051 | int slope = 0; |
| 2052 | int rc = 0; |
| 2053 | int delta_ocv_uv_limit = 0; |
Xiaozhe Shi | 0ac7a00 | 2013-03-26 13:14:03 -0700 | [diff] [blame] | 2054 | int correction_limit_uv = 0; |
Xiaozhe Shi | 7edde5d | 2012-09-26 11:23:09 -0700 | [diff] [blame] | 2055 | |
| 2056 | rc = get_simultaneous_batt_v_and_i(chip, &ibat_ua, &vbat_uv); |
| 2057 | if (rc < 0) { |
| 2058 | pr_err("simultaneous vbat ibat failed err = %d\n", rc); |
| 2059 | goto out; |
| 2060 | } |
| 2061 | |
Xiaozhe Shi | 4be8578 | 2013-02-22 17:33:40 -0800 | [diff] [blame] | 2062 | very_low_voltage_check(chip, vbat_uv); |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 2063 | cv_voltage_check(chip, vbat_uv); |
Xiaozhe Shi | 4be8578 | 2013-02-22 17:33:40 -0800 | [diff] [blame] | 2064 | |
Xiaozhe Shi | 7edde5d | 2012-09-26 11:23:09 -0700 | [diff] [blame] | 2065 | delta_ocv_uv_limit = DIV_ROUND_CLOSEST(ibat_ua, 1000); |
| 2066 | |
Xiaozhe Shi | 904f1f7 | 2012-12-04 12:47:21 -0800 | [diff] [blame] | 2067 | ocv_est_uv = vbat_uv + (ibat_ua * params->rbatt_mohm)/1000; |
| 2068 | |
Xiaozhe Shi | 7edde5d | 2012-09-26 11:23:09 -0700 | [diff] [blame] | 2069 | pc_est = calculate_pc(chip, ocv_est_uv, batt_temp); |
| 2070 | soc_est = div_s64((s64)params->fcc_uah * pc_est - params->uuc_uah*100, |
| 2071 | (s64)params->fcc_uah - params->uuc_uah); |
| 2072 | soc_est = bound_soc(soc_est); |
| 2073 | |
Xiaozhe Shi | 20640b5 | 2013-01-03 11:49:30 -0800 | [diff] [blame] | 2074 | /* never adjust during bms reset mode */ |
| 2075 | if (bms_reset) { |
| 2076 | pr_debug("bms reset mode, SOC adjustment skipped\n"); |
| 2077 | goto out; |
| 2078 | } |
| 2079 | |
Xiaozhe Shi | ee39e5d | 2013-10-07 13:56:04 -0700 | [diff] [blame] | 2080 | if (is_battery_charging(chip)) { |
Xiaozhe Shi | 7edde5d | 2012-09-26 11:23:09 -0700 | [diff] [blame] | 2081 | soc = charging_adjustments(chip, params, soc, vbat_uv, ibat_ua, |
| 2082 | batt_temp); |
Xiaozhe Shi | ee39e5d | 2013-10-07 13:56:04 -0700 | [diff] [blame] | 2083 | /* Skip adjustments if we are in CV or ibat is negative */ |
| 2084 | if (chip->soc_at_cv != -EINVAL || ibat_ua < 0) |
| 2085 | goto out; |
Xiaozhe Shi | 7edde5d | 2012-09-26 11:23:09 -0700 | [diff] [blame] | 2086 | } |
| 2087 | |
| 2088 | /* |
| 2089 | * do not adjust |
Xiaozhe Shi | 561ebf7 | 2013-03-25 13:51:27 -0700 | [diff] [blame] | 2090 | * if soc_est is same as what bms calculated |
| 2091 | * OR if soc_est > adjust_soc_low_threshold |
| 2092 | * OR if soc is above 90 |
| 2093 | * because we might pull it low |
| 2094 | * and cause a bad user experience |
Xiaozhe Shi | 7edde5d | 2012-09-26 11:23:09 -0700 | [diff] [blame] | 2095 | */ |
Xiaozhe Shi | bd56b05 | 2013-10-21 11:51:30 -0700 | [diff] [blame] | 2096 | if (!wake_lock_active(&chip->low_voltage_wake_lock) && |
| 2097 | (soc_est == soc |
| 2098 | || soc_est > chip->adjust_soc_low_threshold |
| 2099 | || soc >= NO_ADJUST_HIGH_SOC_THRESHOLD)) |
Xiaozhe Shi | 7edde5d | 2012-09-26 11:23:09 -0700 | [diff] [blame] | 2100 | goto out; |
| 2101 | |
| 2102 | if (chip->last_soc_est == -EINVAL) |
| 2103 | chip->last_soc_est = soc; |
| 2104 | |
| 2105 | n = min(200, max(1 , soc + soc_est + chip->last_soc_est)); |
| 2106 | chip->last_soc_est = soc_est; |
| 2107 | |
Abhijeet Dharmapurikar | 4b97cdd | 2012-12-26 21:10:53 -0800 | [diff] [blame] | 2108 | pc = calculate_pc(chip, chip->last_ocv_uv, chip->last_ocv_temp); |
Xiaozhe Shi | 7edde5d | 2012-09-26 11:23:09 -0700 | [diff] [blame] | 2109 | if (pc > 0) { |
| 2110 | pc_new = calculate_pc(chip, |
| 2111 | chip->last_ocv_uv - (++slope * 1000), |
Abhijeet Dharmapurikar | 4b97cdd | 2012-12-26 21:10:53 -0800 | [diff] [blame] | 2112 | chip->last_ocv_temp); |
Xiaozhe Shi | 7edde5d | 2012-09-26 11:23:09 -0700 | [diff] [blame] | 2113 | while (pc_new == pc) { |
| 2114 | /* start taking 10mV steps */ |
| 2115 | slope = slope + 10; |
| 2116 | pc_new = calculate_pc(chip, |
| 2117 | chip->last_ocv_uv - (slope * 1000), |
Abhijeet Dharmapurikar | 4b97cdd | 2012-12-26 21:10:53 -0800 | [diff] [blame] | 2118 | chip->last_ocv_temp); |
Xiaozhe Shi | 7edde5d | 2012-09-26 11:23:09 -0700 | [diff] [blame] | 2119 | } |
| 2120 | } else { |
| 2121 | /* |
| 2122 | * pc is already at the lowest point, |
| 2123 | * assume 1 millivolt translates to 1% pc |
| 2124 | */ |
| 2125 | pc = 1; |
| 2126 | pc_new = 0; |
| 2127 | slope = 1; |
| 2128 | } |
| 2129 | |
| 2130 | delta_ocv_uv = div_s64((soc - soc_est) * (s64)slope * 1000, |
| 2131 | n * (pc - pc_new)); |
| 2132 | |
| 2133 | if (abs(delta_ocv_uv) > delta_ocv_uv_limit) { |
| 2134 | pr_debug("limiting delta ocv %d limit = %d\n", delta_ocv_uv, |
| 2135 | delta_ocv_uv_limit); |
| 2136 | |
| 2137 | if (delta_ocv_uv > 0) |
| 2138 | delta_ocv_uv = delta_ocv_uv_limit; |
| 2139 | else |
| 2140 | delta_ocv_uv = -1 * delta_ocv_uv_limit; |
| 2141 | pr_debug("new delta ocv = %d\n", delta_ocv_uv); |
| 2142 | } |
| 2143 | |
Xiaozhe Shi | bd56b05 | 2013-10-21 11:51:30 -0700 | [diff] [blame] | 2144 | if (wake_lock_active(&chip->low_voltage_wake_lock)) { |
| 2145 | /* when in the cutoff region, do not correct upwards */ |
| 2146 | delta_ocv_uv = max(0, delta_ocv_uv); |
Xiaozhe Shi | 08d9aa7 | 2013-07-31 17:15:12 -0700 | [diff] [blame] | 2147 | goto skip_limits; |
Xiaozhe Shi | bd56b05 | 2013-10-21 11:51:30 -0700 | [diff] [blame] | 2148 | } |
Xiaozhe Shi | 08d9aa7 | 2013-07-31 17:15:12 -0700 | [diff] [blame] | 2149 | |
Xiaozhe Shi | 0ac7a00 | 2013-03-26 13:14:03 -0700 | [diff] [blame] | 2150 | if (chip->last_ocv_uv > chip->flat_ocv_threshold_uv) |
| 2151 | correction_limit_uv = chip->high_ocv_correction_limit_uv; |
| 2152 | else |
| 2153 | correction_limit_uv = chip->low_ocv_correction_limit_uv; |
| 2154 | |
| 2155 | if (abs(delta_ocv_uv) > correction_limit_uv) { |
| 2156 | pr_debug("limiting delta ocv %d limit = %d\n", |
| 2157 | delta_ocv_uv, correction_limit_uv); |
| 2158 | if (delta_ocv_uv > 0) |
| 2159 | delta_ocv_uv = correction_limit_uv; |
| 2160 | else |
| 2161 | delta_ocv_uv = -correction_limit_uv; |
| 2162 | pr_debug("new delta ocv = %d\n", delta_ocv_uv); |
| 2163 | } |
| 2164 | |
Xiaozhe Shi | 08d9aa7 | 2013-07-31 17:15:12 -0700 | [diff] [blame] | 2165 | skip_limits: |
| 2166 | |
Xiaozhe Shi | 7edde5d | 2012-09-26 11:23:09 -0700 | [diff] [blame] | 2167 | chip->last_ocv_uv -= delta_ocv_uv; |
| 2168 | |
| 2169 | if (chip->last_ocv_uv >= chip->max_voltage_uv) |
| 2170 | chip->last_ocv_uv = chip->max_voltage_uv; |
| 2171 | |
| 2172 | /* calculate the soc based on this new ocv */ |
Abhijeet Dharmapurikar | 4b97cdd | 2012-12-26 21:10:53 -0800 | [diff] [blame] | 2173 | pc_new = calculate_pc(chip, chip->last_ocv_uv, chip->last_ocv_temp); |
Xiaozhe Shi | 7edde5d | 2012-09-26 11:23:09 -0700 | [diff] [blame] | 2174 | rc_new_uah = (params->fcc_uah * pc_new) / 100; |
| 2175 | soc_new = (rc_new_uah - params->cc_uah - params->uuc_uah)*100 |
| 2176 | / (params->fcc_uah - params->uuc_uah); |
| 2177 | soc_new = bound_soc(soc_new); |
| 2178 | |
| 2179 | /* |
| 2180 | * if soc_new is ZERO force it higher so that phone doesnt report soc=0 |
Xiaozhe Shi | 0ac7a00 | 2013-03-26 13:14:03 -0700 | [diff] [blame] | 2181 | * soc = 0 should happen only when soc_est is above a set value |
Xiaozhe Shi | 7edde5d | 2012-09-26 11:23:09 -0700 | [diff] [blame] | 2182 | */ |
Xiaozhe Shi | 0ac7a00 | 2013-03-26 13:14:03 -0700 | [diff] [blame] | 2183 | if (soc_new == 0 && soc_est >= chip->hold_soc_est) |
Xiaozhe Shi | 7edde5d | 2012-09-26 11:23:09 -0700 | [diff] [blame] | 2184 | soc_new = 1; |
| 2185 | |
| 2186 | soc = soc_new; |
| 2187 | |
| 2188 | out: |
| 2189 | pr_debug("ibat_ua = %d, vbat_uv = %d, ocv_est_uv = %d, pc_est = %d, soc_est = %d, n = %d, delta_ocv_uv = %d, last_ocv_uv = %d, pc_new = %d, soc_new = %d, rbatt = %d, slope = %d\n", |
| 2190 | ibat_ua, vbat_uv, ocv_est_uv, pc_est, |
| 2191 | soc_est, n, delta_ocv_uv, chip->last_ocv_uv, |
Xiaozhe Shi | 904f1f7 | 2012-12-04 12:47:21 -0800 | [diff] [blame] | 2192 | pc_new, soc_new, params->rbatt_mohm, slope); |
Xiaozhe Shi | 7edde5d | 2012-09-26 11:23:09 -0700 | [diff] [blame] | 2193 | |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 2194 | return soc; |
| 2195 | } |
| 2196 | |
Xiaozhe Shi | 2542c60 | 2012-11-28 10:08:07 -0800 | [diff] [blame] | 2197 | static int clamp_soc_based_on_voltage(struct qpnp_bms_chip *chip, int soc) |
| 2198 | { |
| 2199 | int rc, vbat_uv; |
Xiaozhe Shi | 2542c60 | 2012-11-28 10:08:07 -0800 | [diff] [blame] | 2200 | |
Siddartha Mohanadoss | 3cb2b6b | 2013-06-21 12:07:05 -0700 | [diff] [blame] | 2201 | rc = get_battery_voltage(chip, &vbat_uv); |
Xiaozhe Shi | 3645896 | 2013-02-06 16:19:57 -0800 | [diff] [blame] | 2202 | if (rc < 0) { |
| 2203 | pr_err("adc vbat failed err = %d\n", rc); |
| 2204 | return soc; |
Xiaozhe Shi | 2542c60 | 2012-11-28 10:08:07 -0800 | [diff] [blame] | 2205 | } |
Xiaozhe Shi | 2542c60 | 2012-11-28 10:08:07 -0800 | [diff] [blame] | 2206 | if (soc == 0 && vbat_uv > chip->v_cutoff_uv) { |
| 2207 | pr_debug("clamping soc to 1, vbat (%d) > cutoff (%d)\n", |
| 2208 | vbat_uv, chip->v_cutoff_uv); |
| 2209 | return 1; |
Xiaozhe Shi | 2542c60 | 2012-11-28 10:08:07 -0800 | [diff] [blame] | 2210 | } else { |
| 2211 | pr_debug("not clamping, using soc = %d, vbat = %d and cutoff = %d\n", |
| 2212 | soc, vbat_uv, chip->v_cutoff_uv); |
| 2213 | return soc; |
| 2214 | } |
| 2215 | } |
| 2216 | |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 2217 | static int64_t convert_cc_uah_to_raw(struct qpnp_bms_chip *chip, int64_t cc_uah) |
| 2218 | { |
| 2219 | int64_t cc_uv, cc_pvh, cc_raw; |
| 2220 | |
| 2221 | cc_pvh = cc_uah * chip->r_sense_uohm; |
| 2222 | cc_uv = div_s64(cc_pvh * SLEEP_CLK_HZ * SECONDS_PER_HOUR, |
| 2223 | CC_READING_TICKS * 1000000LL); |
| 2224 | cc_raw = div_s64(cc_uv * CC_READING_RESOLUTION_D, |
| 2225 | CC_READING_RESOLUTION_N); |
| 2226 | return cc_raw; |
| 2227 | } |
| 2228 | |
| 2229 | #define CC_STEP_INCREMENT_UAH 1500 |
| 2230 | #define OCV_STEP_INCREMENT 0x10 |
| 2231 | static void configure_soc_wakeup(struct qpnp_bms_chip *chip, |
| 2232 | struct soc_params *params, |
| 2233 | int batt_temp, int target_soc) |
| 2234 | { |
| 2235 | int target_ocv_uv; |
| 2236 | int64_t target_cc_uah, cc_raw_64, current_shdw_cc_raw_64; |
| 2237 | int64_t current_shdw_cc_uah, iadc_comp_factor; |
| 2238 | uint64_t cc_raw, current_shdw_cc_raw; |
| 2239 | int16_t ocv_raw, current_ocv_raw; |
| 2240 | |
| 2241 | current_shdw_cc_raw = 0; |
| 2242 | mutex_lock(&chip->bms_output_lock); |
| 2243 | lock_output_data(chip); |
| 2244 | qpnp_read_wrapper(chip, (u8 *)¤t_ocv_raw, |
| 2245 | chip->base + BMS1_OCV_FOR_SOC_DATA0, 2); |
| 2246 | unlock_output_data(chip); |
| 2247 | mutex_unlock(&chip->bms_output_lock); |
| 2248 | current_shdw_cc_uah = get_prop_bms_charge_counter_shadow(chip); |
| 2249 | current_shdw_cc_raw_64 = convert_cc_uah_to_raw(chip, |
| 2250 | current_shdw_cc_uah); |
| 2251 | |
| 2252 | /* |
| 2253 | * Calculate the target shadow coulomb counter threshold for when |
| 2254 | * the SoC changes. |
| 2255 | * |
| 2256 | * Since the BMS driver resets the shadow coulomb counter every |
| 2257 | * 20 seconds when the device is awake, calculate the threshold as |
| 2258 | * a delta from the current shadow coulomb count. |
| 2259 | */ |
| 2260 | target_cc_uah = (100 - target_soc) |
| 2261 | * (params->fcc_uah - params->uuc_uah) |
| 2262 | / 100 - current_shdw_cc_uah; |
| 2263 | if (target_cc_uah < 0) { |
| 2264 | /* |
| 2265 | * If the target cc is below 0, that means we have already |
| 2266 | * passed the point where SoC should have fallen. |
| 2267 | * Set a wakeup in a few more mAh and check back again |
| 2268 | */ |
| 2269 | target_cc_uah = CC_STEP_INCREMENT_UAH; |
| 2270 | } |
| 2271 | iadc_comp_factor = 100000; |
Siddartha Mohanadoss | 55d0bca | 2013-06-24 08:29:34 -0700 | [diff] [blame] | 2272 | qpnp_iadc_comp_result(chip->iadc_dev, &iadc_comp_factor); |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 2273 | target_cc_uah = div64_s64(target_cc_uah * 100000, iadc_comp_factor); |
Siddartha Mohanadoss | 55d0bca | 2013-06-24 08:29:34 -0700 | [diff] [blame] | 2274 | target_cc_uah = cc_reverse_adjust_for_gain(chip, target_cc_uah); |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 2275 | cc_raw_64 = convert_cc_uah_to_raw(chip, target_cc_uah); |
| 2276 | cc_raw = convert_s64_to_s36(cc_raw_64); |
| 2277 | |
Xiaozhe Shi | d9ffdaf | 2013-09-19 16:23:21 -0700 | [diff] [blame] | 2278 | target_ocv_uv = find_ocv_for_pc(chip, batt_temp, |
| 2279 | find_pc_for_soc(chip, params, target_soc)); |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 2280 | ocv_raw = convert_vbatt_uv_to_raw(chip, target_ocv_uv); |
| 2281 | |
| 2282 | /* |
| 2283 | * If the current_ocv_raw was updated since reaching 100% and is lower |
| 2284 | * than the calculated target ocv threshold, set the new target |
| 2285 | * threshold 1.5mAh lower in order to check if the SoC changed yet. |
| 2286 | */ |
| 2287 | if (current_ocv_raw != chip->ocv_reading_at_100 |
| 2288 | && current_ocv_raw < ocv_raw) |
| 2289 | ocv_raw = current_ocv_raw - OCV_STEP_INCREMENT; |
| 2290 | |
| 2291 | qpnp_write_wrapper(chip, (u8 *)&cc_raw, |
| 2292 | chip->base + BMS1_SW_CC_THR0, 5); |
| 2293 | qpnp_write_wrapper(chip, (u8 *)&ocv_raw, |
| 2294 | chip->base + BMS1_OCV_THR0, 2); |
| 2295 | |
Xiaozhe Shi | f5d8783 | 2013-11-21 17:05:39 -0800 | [diff] [blame] | 2296 | enable_bms_irq(&chip->ocv_thr_irq); |
| 2297 | enable_bms_irq(&chip->sw_cc_thr_irq); |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 2298 | pr_debug("current sw_cc_raw = 0x%llx, current ocv = 0x%hx\n", |
| 2299 | current_shdw_cc_raw, (uint16_t)current_ocv_raw); |
| 2300 | pr_debug("target_cc_uah = %lld, raw64 = 0x%llx, raw 36 = 0x%llx, ocv_raw = 0x%hx\n", |
| 2301 | target_cc_uah, |
| 2302 | (uint64_t)cc_raw_64, cc_raw, |
| 2303 | (uint16_t)ocv_raw); |
| 2304 | } |
| 2305 | |
Xiaozhe Shi | 5e79103 | 2013-10-25 11:30:42 -0700 | [diff] [blame] | 2306 | #define BAD_SOC_THRESH -10 |
Xiaozhe Shi | f9f9924 | 2013-08-29 12:27:50 -0700 | [diff] [blame] | 2307 | static int calculate_raw_soc(struct qpnp_bms_chip *chip, |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 2308 | struct raw_soc_params *raw, |
Xiaozhe Shi | f9f9924 | 2013-08-29 12:27:50 -0700 | [diff] [blame] | 2309 | struct soc_params *params, |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 2310 | int batt_temp) |
| 2311 | { |
Xiaozhe Shi | d9ffdaf | 2013-09-19 16:23:21 -0700 | [diff] [blame] | 2312 | int soc, remaining_usable_charge_uah; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 2313 | |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 2314 | /* calculate remaining usable charge */ |
Xiaozhe Shi | f9f9924 | 2013-08-29 12:27:50 -0700 | [diff] [blame] | 2315 | remaining_usable_charge_uah = params->ocv_charge_uah |
| 2316 | - params->cc_uah |
| 2317 | - params->uuc_uah; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 2318 | pr_debug("RUC = %duAh\n", remaining_usable_charge_uah); |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 2319 | |
Xiaozhe Shi | fd8cd48 | 2013-02-12 10:00:38 -0800 | [diff] [blame] | 2320 | soc = DIV_ROUND_CLOSEST((remaining_usable_charge_uah * 100), |
Xiaozhe Shi | f9f9924 | 2013-08-29 12:27:50 -0700 | [diff] [blame] | 2321 | (params->fcc_uah - params->uuc_uah)); |
Xiaozhe Shi | fd8cd48 | 2013-02-12 10:00:38 -0800 | [diff] [blame] | 2322 | |
Xiaozhe Shi | 5e79103 | 2013-10-25 11:30:42 -0700 | [diff] [blame] | 2323 | if (chip->first_time_calc_soc && soc > BAD_SOC_THRESH && soc < 0) { |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 2324 | /* |
| 2325 | * first time calcualtion and the pon ocv is too low resulting |
| 2326 | * in a bad soc. Adjust ocv to get 0 soc |
| 2327 | */ |
| 2328 | pr_debug("soc is %d, adjusting pon ocv to make it 0\n", soc); |
Xiaozhe Shi | d9ffdaf | 2013-09-19 16:23:21 -0700 | [diff] [blame] | 2329 | chip->last_ocv_uv = find_ocv_for_pc(chip, batt_temp, |
| 2330 | find_pc_for_soc(chip, params, 0)); |
| 2331 | params->ocv_charge_uah = find_ocv_charge_for_soc(chip, |
| 2332 | params, 0); |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 2333 | |
Xiaozhe Shi | f9f9924 | 2013-08-29 12:27:50 -0700 | [diff] [blame] | 2334 | remaining_usable_charge_uah = params->ocv_charge_uah |
| 2335 | - params->cc_uah |
| 2336 | - params->uuc_uah; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 2337 | |
| 2338 | soc = DIV_ROUND_CLOSEST((remaining_usable_charge_uah * 100), |
Xiaozhe Shi | f9f9924 | 2013-08-29 12:27:50 -0700 | [diff] [blame] | 2339 | (params->fcc_uah |
| 2340 | - params->uuc_uah)); |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 2341 | pr_debug("DONE for O soc is %d, pon ocv adjusted to %duV\n", |
| 2342 | soc, chip->last_ocv_uv); |
| 2343 | } |
| 2344 | |
| 2345 | if (soc > 100) |
| 2346 | soc = 100; |
| 2347 | |
Xiaozhe Shi | 5e79103 | 2013-10-25 11:30:42 -0700 | [diff] [blame] | 2348 | if (soc > BAD_SOC_THRESH && soc < 0) { |
Xiaozhe Shi | cb386a2 | 2012-11-29 12:11:42 -0800 | [diff] [blame] | 2349 | pr_debug("bad rem_usb_chg = %d rem_chg %d, cc_uah %d, unusb_chg %d\n", |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 2350 | remaining_usable_charge_uah, |
Xiaozhe Shi | f9f9924 | 2013-08-29 12:27:50 -0700 | [diff] [blame] | 2351 | params->ocv_charge_uah, |
| 2352 | params->cc_uah, params->uuc_uah); |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 2353 | |
Xiaozhe Shi | cb386a2 | 2012-11-29 12:11:42 -0800 | [diff] [blame] | 2354 | pr_debug("for bad rem_usb_chg last_ocv_uv = %d batt_temp = %d fcc = %d soc =%d\n", |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 2355 | chip->last_ocv_uv, batt_temp, |
Xiaozhe Shi | f9f9924 | 2013-08-29 12:27:50 -0700 | [diff] [blame] | 2356 | params->fcc_uah, soc); |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 2357 | soc = 0; |
| 2358 | } |
| 2359 | |
Xiaozhe Shi | f9f9924 | 2013-08-29 12:27:50 -0700 | [diff] [blame] | 2360 | return soc; |
| 2361 | } |
| 2362 | |
| 2363 | #define SLEEP_RECALC_INTERVAL 3 |
| 2364 | static int calculate_state_of_charge(struct qpnp_bms_chip *chip, |
| 2365 | struct raw_soc_params *raw, |
| 2366 | int batt_temp) |
| 2367 | { |
| 2368 | struct soc_params params; |
| 2369 | int soc, previous_soc, shutdown_soc, new_calculated_soc; |
Xiaozhe Shi | d9ffdaf | 2013-09-19 16:23:21 -0700 | [diff] [blame] | 2370 | int remaining_usable_charge_uah; |
Xiaozhe Shi | f9f9924 | 2013-08-29 12:27:50 -0700 | [diff] [blame] | 2371 | |
| 2372 | calculate_soc_params(chip, raw, ¶ms, batt_temp); |
| 2373 | if (!is_battery_present(chip)) { |
| 2374 | pr_debug("battery gone, reporting 100\n"); |
| 2375 | new_calculated_soc = 100; |
| 2376 | goto done_calculating; |
| 2377 | } |
| 2378 | |
| 2379 | if (params.fcc_uah - params.uuc_uah <= 0) { |
| 2380 | pr_debug("FCC = %duAh, UUC = %duAh forcing soc = 0\n", |
| 2381 | params.fcc_uah, |
| 2382 | params.uuc_uah); |
| 2383 | new_calculated_soc = 0; |
| 2384 | goto done_calculating; |
| 2385 | } |
| 2386 | |
| 2387 | soc = calculate_raw_soc(chip, raw, ¶ms, batt_temp); |
| 2388 | |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 2389 | mutex_lock(&chip->soc_invalidation_mutex); |
| 2390 | shutdown_soc = chip->shutdown_soc; |
| 2391 | |
| 2392 | if (chip->first_time_calc_soc && soc != shutdown_soc |
Xiaozhe Shi | f9f9924 | 2013-08-29 12:27:50 -0700 | [diff] [blame] | 2393 | && !chip->shutdown_soc_invalid) { |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 2394 | /* |
| 2395 | * soc for the first time - use shutdown soc |
| 2396 | * to adjust pon ocv since it is a small percent away from |
| 2397 | * the real soc |
| 2398 | */ |
| 2399 | pr_debug("soc = %d before forcing shutdown_soc = %d\n", |
| 2400 | soc, shutdown_soc); |
Xiaozhe Shi | d9ffdaf | 2013-09-19 16:23:21 -0700 | [diff] [blame] | 2401 | chip->last_ocv_uv = find_ocv_for_pc(chip, batt_temp, |
| 2402 | find_pc_for_soc(chip, ¶ms, shutdown_soc)); |
| 2403 | params.ocv_charge_uah = find_ocv_charge_for_soc(chip, |
| 2404 | ¶ms, shutdown_soc); |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 2405 | |
| 2406 | remaining_usable_charge_uah = params.ocv_charge_uah |
| 2407 | - params.cc_uah |
| 2408 | - params.uuc_uah; |
| 2409 | |
| 2410 | soc = DIV_ROUND_CLOSEST((remaining_usable_charge_uah * 100), |
| 2411 | (params.fcc_uah |
| 2412 | - params.uuc_uah)); |
| 2413 | |
| 2414 | pr_debug("DONE for shutdown_soc = %d soc is %d, adjusted ocv to %duV\n", |
| 2415 | shutdown_soc, soc, chip->last_ocv_uv); |
| 2416 | } |
| 2417 | mutex_unlock(&chip->soc_invalidation_mutex); |
| 2418 | |
| 2419 | pr_debug("SOC before adjustment = %d\n", soc); |
| 2420 | new_calculated_soc = adjust_soc(chip, ¶ms, soc, batt_temp); |
| 2421 | |
Xiaozhe Shi | 445d249 | 2013-03-27 18:10:18 -0700 | [diff] [blame] | 2422 | /* always clamp soc due to BMS hw/sw immaturities */ |
| 2423 | new_calculated_soc = clamp_soc_based_on_voltage(chip, |
| 2424 | new_calculated_soc); |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 2425 | /* |
| 2426 | * If the battery is full, configure the cc threshold so the system |
| 2427 | * wakes up after SoC changes |
| 2428 | */ |
Xiaozhe Shi | f5d8783 | 2013-11-21 17:05:39 -0800 | [diff] [blame] | 2429 | if (is_battery_full(chip)) { |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 2430 | configure_soc_wakeup(chip, ¶ms, |
| 2431 | batt_temp, bound_soc(new_calculated_soc - 1)); |
Xiaozhe Shi | f5d8783 | 2013-11-21 17:05:39 -0800 | [diff] [blame] | 2432 | } else { |
| 2433 | disable_bms_irq(&chip->ocv_thr_irq); |
| 2434 | disable_bms_irq(&chip->sw_cc_thr_irq); |
| 2435 | } |
Xiaozhe Shi | fd8cd48 | 2013-02-12 10:00:38 -0800 | [diff] [blame] | 2436 | done_calculating: |
Xiaozhe Shi | fa6ea69 | 2013-05-31 11:15:13 -0700 | [diff] [blame] | 2437 | mutex_lock(&chip->last_soc_mutex); |
Xiaozhe Shi | e7fafe6 | 2013-06-05 15:25:16 -0700 | [diff] [blame] | 2438 | previous_soc = chip->calculated_soc; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 2439 | chip->calculated_soc = new_calculated_soc; |
Xiaozhe Shi | 04da099 | 2013-04-26 16:32:14 -0700 | [diff] [blame] | 2440 | pr_debug("CC based calculated SOC = %d\n", chip->calculated_soc); |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 2441 | if (chip->last_soc_invalid) { |
| 2442 | chip->last_soc_invalid = false; |
| 2443 | chip->last_soc = -EINVAL; |
| 2444 | } |
Xiaozhe Shi | 04da099 | 2013-04-26 16:32:14 -0700 | [diff] [blame] | 2445 | /* |
| 2446 | * Check if more than a long time has passed since the last |
| 2447 | * calculation (more than n times compared to the soc recalculation |
| 2448 | * rate, where n is defined by SLEEP_RECALC_INTERVAL). If this is true, |
| 2449 | * then the system must have gone through a long sleep, and SoC can be |
| 2450 | * allowed to become unbounded by the last reported SoC |
| 2451 | */ |
| 2452 | if (params.delta_time_s * 1000 > |
| 2453 | chip->calculate_soc_ms * SLEEP_RECALC_INTERVAL |
| 2454 | && !chip->first_time_calc_soc) { |
| 2455 | chip->last_soc_unbound = true; |
| 2456 | chip->last_soc_change_sec = chip->last_recalc_time; |
| 2457 | pr_debug("last_soc unbound because elapsed time = %d\n", |
| 2458 | params.delta_time_s); |
| 2459 | } |
| 2460 | mutex_unlock(&chip->last_soc_mutex); |
Xiaozhe Shi | 2737582 | 2013-08-22 11:40:15 -0700 | [diff] [blame] | 2461 | wake_up_interruptible(&chip->bms_wait_queue); |
Xiaozhe Shi | 83484e3 | 2013-05-16 10:59:59 -0700 | [diff] [blame] | 2462 | |
Abhijeet Dharmapurikar | 8e32249 | 2013-06-25 19:48:18 -0700 | [diff] [blame] | 2463 | if (new_calculated_soc != previous_soc && chip->bms_psy_registered) { |
Xiaozhe Shi | 83484e3 | 2013-05-16 10:59:59 -0700 | [diff] [blame] | 2464 | power_supply_changed(&chip->bms_psy); |
| 2465 | pr_debug("power supply changed\n"); |
| 2466 | } else { |
| 2467 | /* |
| 2468 | * Call report state of charge anyways to periodically update |
| 2469 | * reported SoC. This prevents reported SoC from being stuck |
| 2470 | * when calculated soc doesn't change. |
| 2471 | */ |
| 2472 | report_state_of_charge(chip); |
| 2473 | } |
| 2474 | |
Xiaozhe Shi | cdeee31 | 2012-12-18 15:10:18 -0800 | [diff] [blame] | 2475 | get_current_time(&chip->last_recalc_time); |
Xiaozhe Shi | 04da099 | 2013-04-26 16:32:14 -0700 | [diff] [blame] | 2476 | chip->first_time_calc_soc = 0; |
Xiaozhe Shi | 7063392 | 2013-09-23 15:50:53 -0700 | [diff] [blame] | 2477 | chip->first_time_calc_uuc = 0; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 2478 | return chip->calculated_soc; |
| 2479 | } |
| 2480 | |
Xiaozhe Shi | 79d6c1d | 2012-11-26 13:19:50 -0800 | [diff] [blame] | 2481 | static int calculate_soc_from_voltage(struct qpnp_bms_chip *chip) |
| 2482 | { |
| 2483 | int voltage_range_uv, voltage_remaining_uv, voltage_based_soc; |
Xiaozhe Shi | 3645896 | 2013-02-06 16:19:57 -0800 | [diff] [blame] | 2484 | int rc, vbat_uv; |
Xiaozhe Shi | 79d6c1d | 2012-11-26 13:19:50 -0800 | [diff] [blame] | 2485 | |
Siddartha Mohanadoss | 3cb2b6b | 2013-06-21 12:07:05 -0700 | [diff] [blame] | 2486 | rc = get_battery_voltage(chip, &vbat_uv); |
Xiaozhe Shi | 3645896 | 2013-02-06 16:19:57 -0800 | [diff] [blame] | 2487 | if (rc < 0) { |
| 2488 | pr_err("adc vbat failed err = %d\n", rc); |
| 2489 | return rc; |
| 2490 | } |
Xiaozhe Shi | 79d6c1d | 2012-11-26 13:19:50 -0800 | [diff] [blame] | 2491 | voltage_range_uv = chip->max_voltage_uv - chip->v_cutoff_uv; |
| 2492 | voltage_remaining_uv = vbat_uv - chip->v_cutoff_uv; |
| 2493 | voltage_based_soc = voltage_remaining_uv * 100 / voltage_range_uv; |
| 2494 | |
| 2495 | voltage_based_soc = clamp(voltage_based_soc, 0, 100); |
| 2496 | |
| 2497 | if (chip->prev_voltage_based_soc != voltage_based_soc |
Abhijeet Dharmapurikar | 8e32249 | 2013-06-25 19:48:18 -0700 | [diff] [blame] | 2498 | && chip->bms_psy_registered) { |
Xiaozhe Shi | 79d6c1d | 2012-11-26 13:19:50 -0800 | [diff] [blame] | 2499 | power_supply_changed(&chip->bms_psy); |
| 2500 | pr_debug("power supply changed\n"); |
| 2501 | } |
| 2502 | chip->prev_voltage_based_soc = voltage_based_soc; |
| 2503 | |
| 2504 | pr_debug("vbat used = %duv\n", vbat_uv); |
| 2505 | pr_debug("Calculated voltage based soc = %d\n", voltage_based_soc); |
| 2506 | return voltage_based_soc; |
Xiaozhe Shi | 781b0a2 | 2012-11-05 17:18:27 -0800 | [diff] [blame] | 2507 | } |
| 2508 | |
Xiaozhe Shi | f9f9924 | 2013-08-29 12:27:50 -0700 | [diff] [blame] | 2509 | static int recalculate_raw_soc(struct qpnp_bms_chip *chip) |
| 2510 | { |
| 2511 | int batt_temp, rc, soc; |
| 2512 | struct qpnp_vadc_result result; |
| 2513 | struct raw_soc_params raw; |
| 2514 | struct soc_params params; |
| 2515 | |
| 2516 | bms_stay_awake(&chip->soc_wake_source); |
| 2517 | if (chip->use_voltage_soc) { |
| 2518 | soc = calculate_soc_from_voltage(chip); |
| 2519 | } else { |
| 2520 | if (!chip->batfet_closed) |
Xiaozhe Shi | ffb7cfc | 2014-01-03 10:47:36 -0800 | [diff] [blame] | 2521 | qpnp_iadc_calibrate_for_trim(chip->iadc_dev, false); |
Xiaozhe Shi | f9f9924 | 2013-08-29 12:27:50 -0700 | [diff] [blame] | 2522 | rc = qpnp_vadc_read(chip->vadc_dev, LR_MUX1_BATT_THERM, |
| 2523 | &result); |
| 2524 | if (rc) { |
| 2525 | pr_err("error reading vadc LR_MUX1_BATT_THERM = %d, rc = %d\n", |
| 2526 | LR_MUX1_BATT_THERM, rc); |
| 2527 | soc = chip->calculated_soc; |
| 2528 | } else { |
| 2529 | pr_debug("batt_temp phy = %lld meas = 0x%llx\n", |
| 2530 | result.physical, |
| 2531 | result.measurement); |
| 2532 | batt_temp = (int)result.physical; |
| 2533 | |
| 2534 | mutex_lock(&chip->last_ocv_uv_mutex); |
| 2535 | read_soc_params_raw(chip, &raw, batt_temp); |
| 2536 | calculate_soc_params(chip, &raw, ¶ms, batt_temp); |
| 2537 | if (!is_battery_present(chip)) { |
| 2538 | pr_debug("battery gone\n"); |
| 2539 | soc = 0; |
| 2540 | } else if (params.fcc_uah - params.uuc_uah <= 0) { |
| 2541 | pr_debug("FCC = %duAh, UUC = %duAh forcing soc = 0\n", |
| 2542 | params.fcc_uah, |
| 2543 | params.uuc_uah); |
| 2544 | soc = 0; |
| 2545 | } else { |
| 2546 | soc = calculate_raw_soc(chip, &raw, |
| 2547 | ¶ms, batt_temp); |
| 2548 | } |
| 2549 | mutex_unlock(&chip->last_ocv_uv_mutex); |
| 2550 | } |
| 2551 | } |
| 2552 | bms_relax(&chip->soc_wake_source); |
| 2553 | return soc; |
| 2554 | } |
| 2555 | |
Xiaozhe Shi | cdeee31 | 2012-12-18 15:10:18 -0800 | [diff] [blame] | 2556 | static int recalculate_soc(struct qpnp_bms_chip *chip) |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 2557 | { |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 2558 | int batt_temp, rc, soc; |
| 2559 | struct qpnp_vadc_result result; |
| 2560 | struct raw_soc_params raw; |
| 2561 | |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 2562 | bms_stay_awake(&chip->soc_wake_source); |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 2563 | mutex_lock(&chip->vbat_monitor_mutex); |
Xiaozhe Shi | b5689fb | 2013-07-15 17:20:49 -0700 | [diff] [blame] | 2564 | if (chip->vbat_monitor_params.state_request != |
| 2565 | ADC_TM_HIGH_LOW_THR_DISABLE) |
Siddartha Mohanadoss | 88a3fde | 2013-06-24 16:18:52 -0700 | [diff] [blame] | 2566 | qpnp_adc_tm_channel_measure(chip->adc_tm_dev, |
| 2567 | &chip->vbat_monitor_params); |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 2568 | mutex_unlock(&chip->vbat_monitor_mutex); |
Xiaozhe Shi | 79d6c1d | 2012-11-26 13:19:50 -0800 | [diff] [blame] | 2569 | if (chip->use_voltage_soc) { |
| 2570 | soc = calculate_soc_from_voltage(chip); |
| 2571 | } else { |
Abhijeet Dharmapurikar | 84b13dd | 2013-07-08 18:43:56 -0700 | [diff] [blame] | 2572 | if (!chip->batfet_closed) |
Xiaozhe Shi | ffb7cfc | 2014-01-03 10:47:36 -0800 | [diff] [blame] | 2573 | qpnp_iadc_calibrate_for_trim(chip->iadc_dev, false); |
Siddartha Mohanadoss | 3cb2b6b | 2013-06-21 12:07:05 -0700 | [diff] [blame] | 2574 | rc = qpnp_vadc_read(chip->vadc_dev, LR_MUX1_BATT_THERM, |
| 2575 | &result); |
Xiaozhe Shi | 79d6c1d | 2012-11-26 13:19:50 -0800 | [diff] [blame] | 2576 | if (rc) { |
| 2577 | pr_err("error reading vadc LR_MUX1_BATT_THERM = %d, rc = %d\n", |
| 2578 | LR_MUX1_BATT_THERM, rc); |
Abhijeet Dharmapurikar | 713b60a | 2012-12-26 21:30:05 -0800 | [diff] [blame] | 2579 | soc = chip->calculated_soc; |
| 2580 | } else { |
| 2581 | pr_debug("batt_temp phy = %lld meas = 0x%llx\n", |
| 2582 | result.physical, |
| 2583 | result.measurement); |
| 2584 | batt_temp = (int)result.physical; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 2585 | |
Abhijeet Dharmapurikar | 713b60a | 2012-12-26 21:30:05 -0800 | [diff] [blame] | 2586 | mutex_lock(&chip->last_ocv_uv_mutex); |
| 2587 | read_soc_params_raw(chip, &raw, batt_temp); |
| 2588 | soc = calculate_state_of_charge(chip, &raw, batt_temp); |
| 2589 | mutex_unlock(&chip->last_ocv_uv_mutex); |
| 2590 | } |
Xiaozhe Shi | 79d6c1d | 2012-11-26 13:19:50 -0800 | [diff] [blame] | 2591 | } |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 2592 | bms_relax(&chip->soc_wake_source); |
Xiaozhe Shi | cdeee31 | 2012-12-18 15:10:18 -0800 | [diff] [blame] | 2593 | return soc; |
| 2594 | } |
| 2595 | |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 2596 | static void recalculate_work(struct work_struct *work) |
| 2597 | { |
| 2598 | struct qpnp_bms_chip *chip = container_of(work, |
| 2599 | struct qpnp_bms_chip, |
| 2600 | recalc_work); |
| 2601 | |
| 2602 | recalculate_soc(chip); |
| 2603 | } |
| 2604 | |
Xiaozhe Shi | cb487b1 | 2013-10-14 17:42:07 -0700 | [diff] [blame] | 2605 | static int get_calculation_delay_ms(struct qpnp_bms_chip *chip) |
| 2606 | { |
| 2607 | if (wake_lock_active(&chip->low_voltage_wake_lock)) |
| 2608 | return chip->low_voltage_calculate_soc_ms; |
| 2609 | else if (chip->calculated_soc < chip->low_soc_calc_threshold) |
| 2610 | return chip->low_soc_calculate_soc_ms; |
| 2611 | else |
| 2612 | return chip->calculate_soc_ms; |
| 2613 | } |
| 2614 | |
Xiaozhe Shi | cdeee31 | 2012-12-18 15:10:18 -0800 | [diff] [blame] | 2615 | static void calculate_soc_work(struct work_struct *work) |
| 2616 | { |
| 2617 | struct qpnp_bms_chip *chip = container_of(work, |
| 2618 | struct qpnp_bms_chip, |
| 2619 | calculate_soc_delayed_work.work); |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 2620 | |
Xiaozhe Shi | cb487b1 | 2013-10-14 17:42:07 -0700 | [diff] [blame] | 2621 | recalculate_soc(chip); |
| 2622 | schedule_delayed_work(&chip->calculate_soc_delayed_work, |
| 2623 | round_jiffies_relative(msecs_to_jiffies |
| 2624 | (get_calculation_delay_ms(chip)))); |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 2625 | } |
| 2626 | |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 2627 | static void configure_vbat_monitor_low(struct qpnp_bms_chip *chip) |
| 2628 | { |
| 2629 | mutex_lock(&chip->vbat_monitor_mutex); |
| 2630 | if (chip->vbat_monitor_params.state_request |
| 2631 | == ADC_TM_HIGH_LOW_THR_ENABLE) { |
| 2632 | /* |
| 2633 | * Battery is now around or below v_cutoff |
| 2634 | */ |
| 2635 | pr_debug("battery entered cutoff range\n"); |
| 2636 | if (!wake_lock_active(&chip->low_voltage_wake_lock)) { |
| 2637 | pr_debug("voltage low, holding wakelock\n"); |
| 2638 | wake_lock(&chip->low_voltage_wake_lock); |
| 2639 | cancel_delayed_work_sync( |
| 2640 | &chip->calculate_soc_delayed_work); |
| 2641 | schedule_delayed_work( |
| 2642 | &chip->calculate_soc_delayed_work, 0); |
| 2643 | } |
| 2644 | chip->vbat_monitor_params.state_request = |
| 2645 | ADC_TM_HIGH_THR_ENABLE; |
| 2646 | chip->vbat_monitor_params.high_thr = |
| 2647 | (chip->low_voltage_threshold + VBATT_ERROR_MARGIN); |
| 2648 | pr_debug("set low thr to %d and high to %d\n", |
| 2649 | chip->vbat_monitor_params.low_thr, |
| 2650 | chip->vbat_monitor_params.high_thr); |
| 2651 | chip->vbat_monitor_params.low_thr = 0; |
| 2652 | } else if (chip->vbat_monitor_params.state_request |
| 2653 | == ADC_TM_LOW_THR_ENABLE) { |
| 2654 | /* |
| 2655 | * Battery is in normal operation range. |
| 2656 | */ |
| 2657 | pr_debug("battery entered normal range\n"); |
| 2658 | if (wake_lock_active(&chip->cv_wake_lock)) { |
| 2659 | wake_unlock(&chip->cv_wake_lock); |
| 2660 | pr_debug("releasing cv wake lock\n"); |
| 2661 | } |
| 2662 | chip->in_cv_range = false; |
| 2663 | chip->vbat_monitor_params.state_request = |
| 2664 | ADC_TM_HIGH_LOW_THR_ENABLE; |
| 2665 | chip->vbat_monitor_params.high_thr = chip->max_voltage_uv |
| 2666 | - VBATT_ERROR_MARGIN; |
| 2667 | chip->vbat_monitor_params.low_thr = |
| 2668 | chip->low_voltage_threshold; |
| 2669 | pr_debug("set low thr to %d and high to %d\n", |
| 2670 | chip->vbat_monitor_params.low_thr, |
| 2671 | chip->vbat_monitor_params.high_thr); |
| 2672 | } |
Siddartha Mohanadoss | 88a3fde | 2013-06-24 16:18:52 -0700 | [diff] [blame] | 2673 | qpnp_adc_tm_channel_measure(chip->adc_tm_dev, |
| 2674 | &chip->vbat_monitor_params); |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 2675 | mutex_unlock(&chip->vbat_monitor_mutex); |
| 2676 | } |
| 2677 | |
| 2678 | #define CV_LOW_THRESHOLD_HYST_UV 100000 |
| 2679 | static void configure_vbat_monitor_high(struct qpnp_bms_chip *chip) |
| 2680 | { |
| 2681 | mutex_lock(&chip->vbat_monitor_mutex); |
| 2682 | if (chip->vbat_monitor_params.state_request |
| 2683 | == ADC_TM_HIGH_LOW_THR_ENABLE) { |
| 2684 | /* |
| 2685 | * Battery is around vddmax |
| 2686 | */ |
| 2687 | pr_debug("battery entered vddmax range\n"); |
| 2688 | chip->in_cv_range = true; |
| 2689 | if (!wake_lock_active(&chip->cv_wake_lock)) { |
| 2690 | wake_lock(&chip->cv_wake_lock); |
| 2691 | pr_debug("holding cv wake lock\n"); |
| 2692 | } |
| 2693 | schedule_work(&chip->recalc_work); |
| 2694 | chip->vbat_monitor_params.state_request = |
| 2695 | ADC_TM_LOW_THR_ENABLE; |
| 2696 | chip->vbat_monitor_params.low_thr = |
| 2697 | (chip->max_voltage_uv - CV_LOW_THRESHOLD_HYST_UV); |
| 2698 | chip->vbat_monitor_params.high_thr = chip->max_voltage_uv * 2; |
| 2699 | pr_debug("set low thr to %d and high to %d\n", |
| 2700 | chip->vbat_monitor_params.low_thr, |
| 2701 | chip->vbat_monitor_params.high_thr); |
| 2702 | } else if (chip->vbat_monitor_params.state_request |
| 2703 | == ADC_TM_HIGH_THR_ENABLE) { |
| 2704 | /* |
| 2705 | * Battery is in normal operation range. |
| 2706 | */ |
| 2707 | pr_debug("battery entered normal range\n"); |
| 2708 | if (wake_lock_active(&chip->low_voltage_wake_lock)) { |
| 2709 | pr_debug("voltage high, releasing wakelock\n"); |
| 2710 | wake_unlock(&chip->low_voltage_wake_lock); |
| 2711 | } |
| 2712 | chip->vbat_monitor_params.state_request = |
| 2713 | ADC_TM_HIGH_LOW_THR_ENABLE; |
| 2714 | chip->vbat_monitor_params.high_thr = |
| 2715 | chip->max_voltage_uv - VBATT_ERROR_MARGIN; |
| 2716 | chip->vbat_monitor_params.low_thr = |
| 2717 | chip->low_voltage_threshold; |
| 2718 | pr_debug("set low thr to %d and high to %d\n", |
| 2719 | chip->vbat_monitor_params.low_thr, |
| 2720 | chip->vbat_monitor_params.high_thr); |
| 2721 | } |
Siddartha Mohanadoss | 88a3fde | 2013-06-24 16:18:52 -0700 | [diff] [blame] | 2722 | qpnp_adc_tm_channel_measure(chip->adc_tm_dev, |
| 2723 | &chip->vbat_monitor_params); |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 2724 | mutex_unlock(&chip->vbat_monitor_mutex); |
| 2725 | } |
| 2726 | |
| 2727 | static void btm_notify_vbat(enum qpnp_tm_state state, void *ctx) |
| 2728 | { |
| 2729 | struct qpnp_bms_chip *chip = ctx; |
| 2730 | int vbat_uv; |
| 2731 | struct qpnp_vadc_result result; |
| 2732 | int rc; |
| 2733 | |
Siddartha Mohanadoss | 3cb2b6b | 2013-06-21 12:07:05 -0700 | [diff] [blame] | 2734 | rc = qpnp_vadc_read(chip->vadc_dev, VBAT_SNS, &result); |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 2735 | pr_debug("vbat = %lld, raw = 0x%x\n", result.physical, result.adc_code); |
| 2736 | |
Siddartha Mohanadoss | 3cb2b6b | 2013-06-21 12:07:05 -0700 | [diff] [blame] | 2737 | get_battery_voltage(chip, &vbat_uv); |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 2738 | pr_debug("vbat is at %d, state is at %d\n", vbat_uv, state); |
| 2739 | |
| 2740 | if (state == ADC_TM_LOW_STATE) { |
| 2741 | pr_debug("low voltage btm notification triggered\n"); |
| 2742 | if (vbat_uv - VBATT_ERROR_MARGIN |
| 2743 | < chip->vbat_monitor_params.low_thr) { |
| 2744 | configure_vbat_monitor_low(chip); |
| 2745 | } else { |
| 2746 | pr_debug("faulty btm trigger, discarding\n"); |
Siddartha Mohanadoss | 88a3fde | 2013-06-24 16:18:52 -0700 | [diff] [blame] | 2747 | qpnp_adc_tm_channel_measure(chip->adc_tm_dev, |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 2748 | &chip->vbat_monitor_params); |
| 2749 | } |
| 2750 | } else if (state == ADC_TM_HIGH_STATE) { |
| 2751 | pr_debug("high voltage btm notification triggered\n"); |
| 2752 | if (vbat_uv + VBATT_ERROR_MARGIN |
| 2753 | > chip->vbat_monitor_params.high_thr) { |
| 2754 | configure_vbat_monitor_high(chip); |
| 2755 | } else { |
| 2756 | pr_debug("faulty btm trigger, discarding\n"); |
Siddartha Mohanadoss | 88a3fde | 2013-06-24 16:18:52 -0700 | [diff] [blame] | 2757 | qpnp_adc_tm_channel_measure(chip->adc_tm_dev, |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 2758 | &chip->vbat_monitor_params); |
| 2759 | } |
| 2760 | } else { |
| 2761 | pr_debug("unknown voltage notification state: %d\n", state); |
| 2762 | } |
Abhijeet Dharmapurikar | 8e32249 | 2013-06-25 19:48:18 -0700 | [diff] [blame] | 2763 | if (chip->bms_psy_registered) |
Xiaozhe Shi | fa120db | 2013-06-06 15:57:19 -0700 | [diff] [blame] | 2764 | power_supply_changed(&chip->bms_psy); |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 2765 | } |
| 2766 | |
| 2767 | static int reset_vbat_monitoring(struct qpnp_bms_chip *chip) |
| 2768 | { |
| 2769 | int rc; |
| 2770 | |
| 2771 | chip->vbat_monitor_params.state_request = ADC_TM_HIGH_LOW_THR_DISABLE; |
Xiaozhe Shi | b5689fb | 2013-07-15 17:20:49 -0700 | [diff] [blame] | 2772 | |
Siddartha Mohanadoss | 88a3fde | 2013-06-24 16:18:52 -0700 | [diff] [blame] | 2773 | rc = qpnp_adc_tm_channel_measure(chip->adc_tm_dev, |
| 2774 | &chip->vbat_monitor_params); |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 2775 | if (rc) { |
Xiaozhe Shi | b5689fb | 2013-07-15 17:20:49 -0700 | [diff] [blame] | 2776 | pr_err("tm disable failed: %d\n", rc); |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 2777 | return rc; |
| 2778 | } |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 2779 | if (wake_lock_active(&chip->low_voltage_wake_lock)) { |
| 2780 | pr_debug("battery removed, releasing wakelock\n"); |
| 2781 | wake_unlock(&chip->low_voltage_wake_lock); |
| 2782 | } |
| 2783 | if (chip->in_cv_range) { |
| 2784 | pr_debug("battery removed, removing in_cv_range state\n"); |
| 2785 | chip->in_cv_range = false; |
| 2786 | } |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 2787 | return 0; |
| 2788 | } |
| 2789 | |
| 2790 | static int setup_vbat_monitoring(struct qpnp_bms_chip *chip) |
| 2791 | { |
| 2792 | int rc; |
| 2793 | |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 2794 | chip->vbat_monitor_params.low_thr = chip->low_voltage_threshold; |
| 2795 | chip->vbat_monitor_params.high_thr = chip->max_voltage_uv |
| 2796 | - VBATT_ERROR_MARGIN; |
| 2797 | chip->vbat_monitor_params.state_request = ADC_TM_HIGH_LOW_THR_ENABLE; |
| 2798 | chip->vbat_monitor_params.channel = VBAT_SNS; |
| 2799 | chip->vbat_monitor_params.btm_ctx = (void *)chip; |
| 2800 | chip->vbat_monitor_params.timer_interval = ADC_MEAS1_INTERVAL_1S; |
| 2801 | chip->vbat_monitor_params.threshold_notification = &btm_notify_vbat; |
| 2802 | pr_debug("set low thr to %d and high to %d\n", |
| 2803 | chip->vbat_monitor_params.low_thr, |
| 2804 | chip->vbat_monitor_params.high_thr); |
Xiaozhe Shi | b5689fb | 2013-07-15 17:20:49 -0700 | [diff] [blame] | 2805 | |
| 2806 | if (!is_battery_present(chip)) { |
| 2807 | pr_debug("no battery inserted, do not enable vbat monitoring\n"); |
| 2808 | chip->vbat_monitor_params.state_request = |
| 2809 | ADC_TM_HIGH_LOW_THR_DISABLE; |
| 2810 | } else { |
Siddartha Mohanadoss | 88a3fde | 2013-06-24 16:18:52 -0700 | [diff] [blame] | 2811 | rc = qpnp_adc_tm_channel_measure(chip->adc_tm_dev, |
| 2812 | &chip->vbat_monitor_params); |
Xiaozhe Shi | b5689fb | 2013-07-15 17:20:49 -0700 | [diff] [blame] | 2813 | if (rc) { |
| 2814 | pr_err("tm setup failed: %d\n", rc); |
Siddartha Mohanadoss | 88a3fde | 2013-06-24 16:18:52 -0700 | [diff] [blame] | 2815 | return rc; |
Xiaozhe Shi | b5689fb | 2013-07-15 17:20:49 -0700 | [diff] [blame] | 2816 | } |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 2817 | } |
Siddartha Mohanadoss | 88a3fde | 2013-06-24 16:18:52 -0700 | [diff] [blame] | 2818 | |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 2819 | pr_debug("setup complete\n"); |
| 2820 | return 0; |
| 2821 | } |
| 2822 | |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 2823 | static void readjust_fcc_table(struct qpnp_bms_chip *chip) |
| 2824 | { |
| 2825 | struct single_row_lut *temp, *old; |
| 2826 | int i, fcc, ratio; |
| 2827 | |
| 2828 | if (!chip->enable_fcc_learning) |
| 2829 | return; |
| 2830 | |
| 2831 | if (!chip->fcc_temp_lut) { |
| 2832 | pr_err("The static fcc lut table is NULL\n"); |
| 2833 | return; |
| 2834 | } |
| 2835 | |
Xiaozhe Shi | 81f66b5 | 2013-09-20 11:43:52 -0700 | [diff] [blame] | 2836 | temp = devm_kzalloc(chip->dev, sizeof(struct single_row_lut), |
| 2837 | GFP_KERNEL); |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 2838 | if (!temp) { |
| 2839 | pr_err("Cannot allocate memory for adjusted fcc table\n"); |
| 2840 | return; |
| 2841 | } |
| 2842 | |
| 2843 | fcc = interpolate_fcc(chip->fcc_temp_lut, chip->fcc_new_batt_temp); |
| 2844 | |
| 2845 | temp->cols = chip->fcc_temp_lut->cols; |
| 2846 | for (i = 0; i < chip->fcc_temp_lut->cols; i++) { |
| 2847 | temp->x[i] = chip->fcc_temp_lut->x[i]; |
| 2848 | ratio = div_u64(chip->fcc_temp_lut->y[i] * 1000, fcc); |
| 2849 | temp->y[i] = (ratio * chip->fcc_new_mah); |
| 2850 | temp->y[i] /= 1000; |
| 2851 | } |
| 2852 | |
| 2853 | old = chip->adjusted_fcc_temp_lut; |
| 2854 | chip->adjusted_fcc_temp_lut = temp; |
Xiaozhe Shi | 81f66b5 | 2013-09-20 11:43:52 -0700 | [diff] [blame] | 2855 | devm_kfree(chip->dev, old); |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 2856 | } |
| 2857 | |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 2858 | static int read_fcc_data_from_backup(struct qpnp_bms_chip *chip) |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 2859 | { |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 2860 | int rc, i; |
| 2861 | u8 fcc = 0, chgcyl = 0; |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 2862 | |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 2863 | for (i = 0; i < chip->min_fcc_learning_samples; i++) { |
| 2864 | rc = qpnp_read_wrapper(chip, &fcc, |
| 2865 | chip->base + BMS_FCC_BASE_REG + i, 1); |
| 2866 | rc |= qpnp_read_wrapper(chip, &chgcyl, |
| 2867 | chip->base + BMS_CHGCYL_BASE_REG + i, 1); |
| 2868 | if (rc) { |
| 2869 | pr_err("Unable to read FCC data\n"); |
| 2870 | return rc; |
| 2871 | } |
| 2872 | if (fcc == 0 || (fcc == 0xFF && chgcyl == 0xFF)) { |
| 2873 | /* FCC invalid/not present */ |
| 2874 | chip->fcc_learning_samples[i].fcc_new = 0; |
| 2875 | chip->fcc_learning_samples[i].chargecycles = 0; |
| 2876 | } else { |
| 2877 | /* valid FCC data */ |
| 2878 | chip->fcc_sample_count++; |
| 2879 | chip->fcc_learning_samples[i].fcc_new = |
| 2880 | fcc * chip->fcc_resolution; |
| 2881 | chip->fcc_learning_samples[i].chargecycles = |
| 2882 | chgcyl * CHGCYL_RESOLUTION; |
| 2883 | } |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 2884 | } |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 2885 | |
| 2886 | return 0; |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 2887 | } |
| 2888 | |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 2889 | static int discard_backup_fcc_data(struct qpnp_bms_chip *chip) |
| 2890 | { |
| 2891 | int rc = 0, i; |
| 2892 | u8 temp_u8 = 0; |
| 2893 | |
| 2894 | chip->fcc_sample_count = 0; |
| 2895 | for (i = 0; i < chip->min_fcc_learning_samples; i++) { |
| 2896 | rc = qpnp_write_wrapper(chip, &temp_u8, |
| 2897 | chip->base + BMS_FCC_BASE_REG + i, 1); |
| 2898 | rc |= qpnp_write_wrapper(chip, &temp_u8, |
| 2899 | chip->base + BMS_CHGCYL_BASE_REG + i, 1); |
| 2900 | if (rc) { |
| 2901 | pr_err("Unable to clear FCC data\n"); |
| 2902 | return rc; |
| 2903 | } |
| 2904 | } |
| 2905 | |
| 2906 | return 0; |
| 2907 | } |
| 2908 | |
| 2909 | static void |
| 2910 | average_fcc_samples_and_readjust_fcc_table(struct qpnp_bms_chip *chip) |
| 2911 | { |
| 2912 | int i, temp_fcc_avg = 0, temp_fcc_delta = 0, new_fcc_avg = 0; |
| 2913 | struct fcc_sample *ft; |
| 2914 | |
| 2915 | for (i = 0; i < chip->min_fcc_learning_samples; i++) |
| 2916 | temp_fcc_avg += chip->fcc_learning_samples[i].fcc_new; |
| 2917 | |
| 2918 | temp_fcc_avg /= chip->min_fcc_learning_samples; |
| 2919 | temp_fcc_delta = div_u64(temp_fcc_avg * DELTA_FCC_PERCENT, 100); |
| 2920 | |
| 2921 | /* fix the fcc if its an outlier i.e. > 5% of the average */ |
| 2922 | for (i = 0; i < chip->min_fcc_learning_samples; i++) { |
| 2923 | ft = &chip->fcc_learning_samples[i]; |
| 2924 | if (abs(ft->fcc_new - temp_fcc_avg) > temp_fcc_delta) |
| 2925 | new_fcc_avg += temp_fcc_avg; |
| 2926 | else |
| 2927 | new_fcc_avg += ft->fcc_new; |
| 2928 | } |
| 2929 | new_fcc_avg /= chip->min_fcc_learning_samples; |
| 2930 | |
| 2931 | chip->fcc_new_mah = new_fcc_avg; |
| 2932 | chip->fcc_new_batt_temp = FCC_DEFAULT_TEMP; |
| 2933 | pr_info("FCC update: New fcc_mah=%d, fcc_batt_temp=%d\n", |
| 2934 | new_fcc_avg, FCC_DEFAULT_TEMP); |
| 2935 | readjust_fcc_table(chip); |
| 2936 | } |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 2937 | |
| 2938 | static void backup_charge_cycle(struct qpnp_bms_chip *chip) |
| 2939 | { |
| 2940 | int rc = 0; |
| 2941 | |
| 2942 | if (chip->charge_increase >= 0) { |
| 2943 | rc = qpnp_write_wrapper(chip, &chip->charge_increase, |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 2944 | chip->base + CHARGE_INCREASE_STORAGE, 1); |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 2945 | if (rc) |
| 2946 | pr_err("Unable to backup charge_increase\n"); |
| 2947 | } |
| 2948 | |
| 2949 | if (chip->charge_cycles >= 0) { |
| 2950 | rc = qpnp_write_wrapper(chip, (u8 *)&chip->charge_cycles, |
| 2951 | chip->base + CHARGE_CYCLE_STORAGE_LSB, 2); |
| 2952 | if (rc) |
| 2953 | pr_err("Unable to backup charge_cycles\n"); |
| 2954 | } |
| 2955 | } |
| 2956 | |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 2957 | static bool chargecycles_in_range(struct qpnp_bms_chip *chip) |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 2958 | { |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 2959 | int i, min_cycle, max_cycle, valid_range; |
| 2960 | |
| 2961 | /* find the smallest and largest charge cycle */ |
| 2962 | max_cycle = min_cycle = chip->fcc_learning_samples[0].chargecycles; |
| 2963 | for (i = 1; i < chip->min_fcc_learning_samples; i++) { |
| 2964 | if (min_cycle > chip->fcc_learning_samples[i].chargecycles) |
| 2965 | min_cycle = chip->fcc_learning_samples[i].chargecycles; |
| 2966 | if (max_cycle < chip->fcc_learning_samples[i].chargecycles) |
| 2967 | max_cycle = chip->fcc_learning_samples[i].chargecycles; |
| 2968 | } |
| 2969 | |
| 2970 | /* check if chargecyles are in range to continue with FCC update */ |
| 2971 | valid_range = DIV_ROUND_UP(VALID_FCC_CHGCYL_RANGE, |
| 2972 | CHGCYL_RESOLUTION) * CHGCYL_RESOLUTION; |
| 2973 | if (abs(max_cycle - min_cycle) > valid_range) |
| 2974 | return false; |
| 2975 | |
| 2976 | return true; |
| 2977 | } |
| 2978 | |
| 2979 | static int read_chgcycle_data_from_backup(struct qpnp_bms_chip *chip) |
| 2980 | { |
| 2981 | int rc; |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 2982 | uint16_t temp_u16 = 0; |
| 2983 | u8 temp_u8 = 0; |
| 2984 | |
| 2985 | rc = qpnp_read_wrapper(chip, &temp_u8, |
| 2986 | chip->base + CHARGE_INCREASE_STORAGE, 1); |
| 2987 | if (!rc && temp_u8 != 0xFF) |
| 2988 | chip->charge_increase = temp_u8; |
| 2989 | |
| 2990 | rc = qpnp_read_wrapper(chip, (u8 *)&temp_u16, |
| 2991 | chip->base + CHARGE_CYCLE_STORAGE_LSB, 2); |
| 2992 | if (!rc && temp_u16 != 0xFFFF) |
| 2993 | chip->charge_cycles = temp_u16; |
| 2994 | |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 2995 | return rc; |
| 2996 | } |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 2997 | |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 2998 | static void |
| 2999 | attempt_learning_new_fcc(struct qpnp_bms_chip *chip) |
| 3000 | { |
| 3001 | pr_debug("Total FCC sample count=%d\n", chip->fcc_sample_count); |
| 3002 | |
| 3003 | /* update FCC if we have the required samples */ |
| 3004 | if ((chip->fcc_sample_count == chip->min_fcc_learning_samples) && |
| 3005 | chargecycles_in_range(chip)) |
| 3006 | average_fcc_samples_and_readjust_fcc_table(chip); |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 3007 | } |
| 3008 | |
| 3009 | static int calculate_real_soc(struct qpnp_bms_chip *chip, |
| 3010 | int batt_temp, struct raw_soc_params *raw, int cc_uah) |
| 3011 | { |
| 3012 | int fcc_uah, rc_uah; |
| 3013 | |
| 3014 | fcc_uah = calculate_fcc(chip, batt_temp); |
| 3015 | rc_uah = calculate_ocv_charge(chip, raw, fcc_uah); |
| 3016 | |
| 3017 | return ((rc_uah - cc_uah) * 100) / fcc_uah; |
| 3018 | } |
| 3019 | |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 3020 | #define MAX_U8_VALUE ((u8)(~0U)) |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 3021 | |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 3022 | static int backup_new_fcc(struct qpnp_bms_chip *chip, int fcc_mah, |
| 3023 | int chargecycles) |
| 3024 | { |
| 3025 | int rc, min_cycle, i; |
| 3026 | u8 fcc_new, chgcyl, pos = 0; |
| 3027 | struct fcc_sample *ft; |
| 3028 | |
| 3029 | if ((fcc_mah > (chip->fcc_resolution * MAX_U8_VALUE)) || |
| 3030 | (chargecycles > (CHGCYL_RESOLUTION * MAX_U8_VALUE))) { |
| 3031 | pr_warn("FCC/Chgcyl beyond storage limit. FCC=%d, chgcyl=%d\n", |
| 3032 | fcc_mah, chargecycles); |
| 3033 | return -EINVAL; |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 3034 | } |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 3035 | |
| 3036 | if (chip->fcc_sample_count == chip->min_fcc_learning_samples) { |
| 3037 | /* search best location - oldest entry */ |
| 3038 | min_cycle = chip->fcc_learning_samples[0].chargecycles; |
| 3039 | for (i = 1; i < chip->min_fcc_learning_samples; i++) { |
| 3040 | if (min_cycle > |
| 3041 | chip->fcc_learning_samples[i].chargecycles) |
| 3042 | pos = i; |
| 3043 | } |
| 3044 | } else { |
| 3045 | /* find an empty location */ |
| 3046 | for (i = 0; i < chip->min_fcc_learning_samples; i++) { |
| 3047 | ft = &chip->fcc_learning_samples[i]; |
| 3048 | if (ft->fcc_new == 0 || (ft->fcc_new == 0xFF && |
| 3049 | ft->chargecycles == 0xFF)) { |
| 3050 | pos = i; |
| 3051 | break; |
| 3052 | } |
| 3053 | } |
| 3054 | chip->fcc_sample_count++; |
| 3055 | } |
| 3056 | chip->fcc_learning_samples[pos].fcc_new = fcc_mah; |
| 3057 | chip->fcc_learning_samples[pos].chargecycles = chargecycles; |
| 3058 | |
| 3059 | fcc_new = DIV_ROUND_UP(fcc_mah, chip->fcc_resolution); |
| 3060 | rc = qpnp_write_wrapper(chip, (u8 *)&fcc_new, |
| 3061 | chip->base + BMS_FCC_BASE_REG + pos, 1); |
| 3062 | if (rc) |
| 3063 | return rc; |
| 3064 | |
| 3065 | chgcyl = DIV_ROUND_UP(chargecycles, CHGCYL_RESOLUTION); |
| 3066 | rc = qpnp_write_wrapper(chip, (u8 *)&chgcyl, |
| 3067 | chip->base + BMS_CHGCYL_BASE_REG + pos, 1); |
| 3068 | if (rc) |
| 3069 | return rc; |
| 3070 | |
| 3071 | pr_debug("Backup new FCC: fcc_new=%d, chargecycle=%d, pos=%d\n", |
| 3072 | fcc_new, chgcyl, pos); |
| 3073 | |
| 3074 | return rc; |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 3075 | } |
| 3076 | |
| 3077 | static void update_fcc_learning_table(struct qpnp_bms_chip *chip, |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 3078 | int new_fcc_uah, int chargecycles, int batt_temp) |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 3079 | { |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 3080 | int rc, fcc_default, fcc_temp; |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 3081 | |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 3082 | /* convert the fcc at batt_temp to new fcc at FCC_DEFAULT_TEMP */ |
| 3083 | fcc_default = calculate_fcc(chip, FCC_DEFAULT_TEMP) / 1000; |
| 3084 | fcc_temp = calculate_fcc(chip, batt_temp) / 1000; |
| 3085 | new_fcc_uah = (new_fcc_uah / fcc_temp) * fcc_default; |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 3086 | |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 3087 | rc = backup_new_fcc(chip, new_fcc_uah / 1000, chargecycles); |
| 3088 | if (rc) { |
| 3089 | pr_err("Unable to backup new FCC\n"); |
| 3090 | return; |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 3091 | } |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 3092 | /* check if FCC can be updated */ |
| 3093 | attempt_learning_new_fcc(chip); |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 3094 | } |
| 3095 | |
| 3096 | static bool is_new_fcc_valid(int new_fcc_uah, int fcc_uah) |
| 3097 | { |
| 3098 | if ((new_fcc_uah >= (fcc_uah / 2)) && |
| 3099 | ((new_fcc_uah * 100) <= (fcc_uah * 105))) |
| 3100 | return true; |
| 3101 | |
| 3102 | pr_debug("FCC rejected - not within valid limit\n"); |
| 3103 | return false; |
| 3104 | } |
| 3105 | |
| 3106 | static void fcc_learning_config(struct qpnp_bms_chip *chip, bool start) |
| 3107 | { |
| 3108 | int rc, batt_temp; |
| 3109 | struct raw_soc_params raw; |
| 3110 | struct qpnp_vadc_result result; |
| 3111 | int fcc_uah, new_fcc_uah, delta_cc_uah, delta_soc; |
| 3112 | |
Siddartha Mohanadoss | 3cb2b6b | 2013-06-21 12:07:05 -0700 | [diff] [blame] | 3113 | rc = qpnp_vadc_read(chip->vadc_dev, LR_MUX1_BATT_THERM, &result); |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 3114 | if (rc) { |
| 3115 | pr_err("Unable to read batt_temp\n"); |
| 3116 | return; |
| 3117 | } else { |
| 3118 | batt_temp = (int)result.physical; |
| 3119 | } |
| 3120 | |
| 3121 | rc = read_soc_params_raw(chip, &raw, batt_temp); |
| 3122 | if (rc) { |
| 3123 | pr_err("Unable to read CC, cannot update FCC\n"); |
| 3124 | return; |
| 3125 | } |
| 3126 | |
| 3127 | if (start) { |
| 3128 | chip->start_pc = interpolate_pc(chip->pc_temp_ocv_lut, |
| 3129 | batt_temp / 10, raw.last_good_ocv_uv / 1000); |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 3130 | chip->start_cc_uah = calculate_cc(chip, raw.cc, CC, NORESET); |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 3131 | chip->start_real_soc = calculate_real_soc(chip, |
| 3132 | batt_temp, &raw, chip->start_cc_uah); |
| 3133 | pr_debug("start_pc=%d, start_cc=%d, start_soc=%d real_soc=%d\n", |
| 3134 | chip->start_pc, chip->start_cc_uah, |
| 3135 | chip->start_soc, chip->start_real_soc); |
| 3136 | } else { |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 3137 | chip->end_cc_uah = calculate_cc(chip, raw.cc, CC, NORESET); |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 3138 | delta_soc = 100 - chip->start_real_soc; |
| 3139 | delta_cc_uah = abs(chip->end_cc_uah - chip->start_cc_uah); |
| 3140 | new_fcc_uah = div_u64(delta_cc_uah * 100, delta_soc); |
| 3141 | fcc_uah = calculate_fcc(chip, batt_temp); |
| 3142 | pr_debug("start_soc=%d, start_pc=%d, start_real_soc=%d, start_cc=%d, end_cc=%d, new_fcc=%d\n", |
| 3143 | chip->start_soc, chip->start_pc, chip->start_real_soc, |
| 3144 | chip->start_cc_uah, chip->end_cc_uah, new_fcc_uah); |
| 3145 | |
| 3146 | if (is_new_fcc_valid(new_fcc_uah, fcc_uah)) |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 3147 | update_fcc_learning_table(chip, new_fcc_uah, |
| 3148 | chip->charge_cycles, batt_temp); |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 3149 | } |
| 3150 | } |
| 3151 | |
Abhijeet Dharmapurikar | 84b13dd | 2013-07-08 18:43:56 -0700 | [diff] [blame] | 3152 | #define MAX_CAL_TRIES 200 |
| 3153 | #define MIN_CAL_UA 3000 |
| 3154 | static void batfet_open_work(struct work_struct *work) |
| 3155 | { |
| 3156 | int i; |
| 3157 | int rc; |
| 3158 | int result_ua; |
| 3159 | u8 orig_delay, sample_delay; |
| 3160 | struct qpnp_bms_chip *chip = container_of(work, |
| 3161 | struct qpnp_bms_chip, |
| 3162 | batfet_open_work); |
| 3163 | |
| 3164 | rc = qpnp_read_wrapper(chip, &orig_delay, |
| 3165 | chip->base + BMS1_S1_DELAY_CTL, 1); |
| 3166 | |
| 3167 | sample_delay = 0x0; |
| 3168 | rc = qpnp_write_wrapper(chip, &sample_delay, |
| 3169 | chip->base + BMS1_S1_DELAY_CTL, 1); |
| 3170 | |
| 3171 | /* |
| 3172 | * In certain PMICs there is a coupling issue which causes |
| 3173 | * bad calibration value that result in a huge battery current |
| 3174 | * even when the BATFET is open. Do continious calibrations until |
| 3175 | * we hit reasonable cal values which result in low battery current |
| 3176 | */ |
| 3177 | |
| 3178 | for (i = 0; (!chip->batfet_closed) && i < MAX_CAL_TRIES; i++) { |
Siddartha Mohanadoss | 55d0bca | 2013-06-24 08:29:34 -0700 | [diff] [blame] | 3179 | rc = qpnp_iadc_calibrate_for_trim(chip->iadc_dev, false); |
Abhijeet Dharmapurikar | 84b13dd | 2013-07-08 18:43:56 -0700 | [diff] [blame] | 3180 | /* |
| 3181 | * Wait 20mS after calibration and before reading battery |
| 3182 | * current. The BMS h/w uses calibration values in the |
| 3183 | * next sampling of vsense. |
| 3184 | */ |
| 3185 | msleep(20); |
| 3186 | rc |= get_battery_current(chip, &result_ua); |
| 3187 | if (rc == 0 && abs(result_ua) <= MIN_CAL_UA) { |
| 3188 | pr_debug("good cal at %d attempt\n", i); |
| 3189 | break; |
| 3190 | } |
| 3191 | } |
| 3192 | pr_debug("batfet_closed = %d i = %d result_ua = %d\n", |
| 3193 | chip->batfet_closed, i, result_ua); |
| 3194 | |
| 3195 | rc = qpnp_write_wrapper(chip, &orig_delay, |
| 3196 | chip->base + BMS1_S1_DELAY_CTL, 1); |
| 3197 | } |
| 3198 | |
Xiaozhe Shi | 890fbf4 | 2013-05-02 16:42:53 -0700 | [diff] [blame] | 3199 | static void charging_began(struct qpnp_bms_chip *chip) |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 3200 | { |
Xiaozhe Shi | 890fbf4 | 2013-05-02 16:42:53 -0700 | [diff] [blame] | 3201 | mutex_lock(&chip->last_soc_mutex); |
| 3202 | chip->charge_start_tm_sec = 0; |
| 3203 | chip->catch_up_time_sec = 0; |
| 3204 | mutex_unlock(&chip->last_soc_mutex); |
| 3205 | |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 3206 | chip->start_soc = report_state_of_charge(chip); |
| 3207 | |
Xiaozhe Shi | 890fbf4 | 2013-05-02 16:42:53 -0700 | [diff] [blame] | 3208 | mutex_lock(&chip->last_ocv_uv_mutex); |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 3209 | if (chip->enable_fcc_learning) |
| 3210 | fcc_learning_config(chip, true); |
Xiaozhe Shi | 890fbf4 | 2013-05-02 16:42:53 -0700 | [diff] [blame] | 3211 | chip->soc_at_cv = -EINVAL; |
| 3212 | chip->prev_chg_soc = -EINVAL; |
| 3213 | mutex_unlock(&chip->last_ocv_uv_mutex); |
| 3214 | } |
| 3215 | |
| 3216 | static void charging_ended(struct qpnp_bms_chip *chip) |
| 3217 | { |
| 3218 | mutex_lock(&chip->last_soc_mutex); |
| 3219 | chip->charge_start_tm_sec = 0; |
| 3220 | chip->catch_up_time_sec = 0; |
| 3221 | mutex_unlock(&chip->last_soc_mutex); |
| 3222 | |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 3223 | chip->end_soc = report_state_of_charge(chip); |
| 3224 | |
Xiaozhe Shi | 890fbf4 | 2013-05-02 16:42:53 -0700 | [diff] [blame] | 3225 | mutex_lock(&chip->last_ocv_uv_mutex); |
| 3226 | chip->soc_at_cv = -EINVAL; |
| 3227 | chip->prev_chg_soc = -EINVAL; |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 3228 | |
| 3229 | /* update the chargecycles */ |
| 3230 | if (chip->end_soc > chip->start_soc) { |
| 3231 | chip->charge_increase += (chip->end_soc - chip->start_soc); |
| 3232 | if (chip->charge_increase > 100) { |
| 3233 | chip->charge_cycles++; |
| 3234 | chip->charge_increase = chip->charge_increase % 100; |
| 3235 | } |
| 3236 | if (chip->enable_fcc_learning) |
| 3237 | backup_charge_cycle(chip); |
| 3238 | } |
| 3239 | |
Xiaozhe Shi | 83484e3 | 2013-05-16 10:59:59 -0700 | [diff] [blame] | 3240 | if (get_battery_status(chip) == POWER_SUPPLY_STATUS_FULL) { |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 3241 | if (chip->enable_fcc_learning && |
| 3242 | (chip->start_soc <= chip->min_fcc_learning_soc) && |
| 3243 | (chip->start_pc <= chip->min_fcc_ocv_pc)) |
| 3244 | fcc_learning_config(chip, false); |
Xiaozhe Shi | 890fbf4 | 2013-05-02 16:42:53 -0700 | [diff] [blame] | 3245 | chip->done_charging = true; |
Xiaozhe Shi | 83484e3 | 2013-05-16 10:59:59 -0700 | [diff] [blame] | 3246 | chip->last_soc_invalid = true; |
Xiaozhe Shi | cc48e99 | 2013-05-28 16:42:24 -0700 | [diff] [blame] | 3247 | } else if (chip->charging_adjusted_ocv > 0) { |
| 3248 | pr_debug("Charging stopped before full, adjusted OCV = %d\n", |
| 3249 | chip->charging_adjusted_ocv); |
| 3250 | chip->last_ocv_uv = chip->charging_adjusted_ocv; |
Xiaozhe Shi | 83484e3 | 2013-05-16 10:59:59 -0700 | [diff] [blame] | 3251 | } |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 3252 | |
Xiaozhe Shi | cc48e99 | 2013-05-28 16:42:24 -0700 | [diff] [blame] | 3253 | chip->charging_adjusted_ocv = -EINVAL; |
| 3254 | |
Xiaozhe Shi | 890fbf4 | 2013-05-02 16:42:53 -0700 | [diff] [blame] | 3255 | mutex_unlock(&chip->last_ocv_uv_mutex); |
| 3256 | } |
| 3257 | |
| 3258 | static void battery_status_check(struct qpnp_bms_chip *chip) |
| 3259 | { |
| 3260 | int status = get_battery_status(chip); |
| 3261 | |
Xiaozhe Shi | bda8499 | 2013-09-05 10:39:11 -0700 | [diff] [blame] | 3262 | mutex_lock(&chip->status_lock); |
Xiaozhe Shi | 890fbf4 | 2013-05-02 16:42:53 -0700 | [diff] [blame] | 3263 | if (chip->battery_status != status) { |
Xiaozhe Shi | 30e9480 | 2013-08-19 16:40:53 -0700 | [diff] [blame] | 3264 | pr_debug("status = %d, shadow status = %d\n", |
| 3265 | status, chip->battery_status); |
Xiaozhe Shi | 890fbf4 | 2013-05-02 16:42:53 -0700 | [diff] [blame] | 3266 | if (status == POWER_SUPPLY_STATUS_CHARGING) { |
| 3267 | pr_debug("charging started\n"); |
| 3268 | charging_began(chip); |
| 3269 | } else if (chip->battery_status |
| 3270 | == POWER_SUPPLY_STATUS_CHARGING) { |
| 3271 | pr_debug("charging ended\n"); |
| 3272 | charging_ended(chip); |
| 3273 | } |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 3274 | |
| 3275 | if (status == POWER_SUPPLY_STATUS_FULL) { |
| 3276 | pr_debug("battery full\n"); |
Xiaozhe Shi | bda8499 | 2013-09-05 10:39:11 -0700 | [diff] [blame] | 3277 | recalculate_soc(chip); |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 3278 | } else if (chip->battery_status |
| 3279 | == POWER_SUPPLY_STATUS_FULL) { |
| 3280 | pr_debug("battery not full any more\n"); |
| 3281 | disable_bms_irq(&chip->ocv_thr_irq); |
| 3282 | disable_bms_irq(&chip->sw_cc_thr_irq); |
| 3283 | } |
| 3284 | |
Xiaozhe Shi | 890fbf4 | 2013-05-02 16:42:53 -0700 | [diff] [blame] | 3285 | chip->battery_status = status; |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 3286 | /* battery charge status has changed, so force a soc |
Xiaozhe Shi | 890fbf4 | 2013-05-02 16:42:53 -0700 | [diff] [blame] | 3287 | * recalculation to update the SoC */ |
| 3288 | schedule_work(&chip->recalc_work); |
| 3289 | } |
Xiaozhe Shi | bda8499 | 2013-09-05 10:39:11 -0700 | [diff] [blame] | 3290 | mutex_unlock(&chip->status_lock); |
Xiaozhe Shi | 890fbf4 | 2013-05-02 16:42:53 -0700 | [diff] [blame] | 3291 | } |
| 3292 | |
Abhijeet Dharmapurikar | 604461d | 2013-07-09 13:34:33 -0700 | [diff] [blame] | 3293 | #define CALIB_WRKARND_DIG_MAJOR_MAX 0x03 |
Abhijeet Dharmapurikar | 84b13dd | 2013-07-08 18:43:56 -0700 | [diff] [blame] | 3294 | static void batfet_status_check(struct qpnp_bms_chip *chip) |
| 3295 | { |
| 3296 | bool batfet_closed; |
| 3297 | |
Abhijeet Dharmapurikar | 84b13dd | 2013-07-08 18:43:56 -0700 | [diff] [blame] | 3298 | batfet_closed = is_batfet_closed(chip); |
| 3299 | if (chip->batfet_closed != batfet_closed) { |
| 3300 | chip->batfet_closed = batfet_closed; |
Xiaozhe Shi | ffb7cfc | 2014-01-03 10:47:36 -0800 | [diff] [blame] | 3301 | if (chip->iadc_bms_revision2 > CALIB_WRKARND_DIG_MAJOR_MAX) |
| 3302 | return; |
Abhijeet Dharmapurikar | 84b13dd | 2013-07-08 18:43:56 -0700 | [diff] [blame] | 3303 | if (batfet_closed == false) { |
| 3304 | /* batfet opened */ |
| 3305 | schedule_work(&chip->batfet_open_work); |
Siddartha Mohanadoss | 55d0bca | 2013-06-24 08:29:34 -0700 | [diff] [blame] | 3306 | qpnp_iadc_skip_calibration(chip->iadc_dev); |
Abhijeet Dharmapurikar | 84b13dd | 2013-07-08 18:43:56 -0700 | [diff] [blame] | 3307 | } else { |
| 3308 | /* batfet closed */ |
Siddartha Mohanadoss | 55d0bca | 2013-06-24 08:29:34 -0700 | [diff] [blame] | 3309 | qpnp_iadc_calibrate_for_trim(chip->iadc_dev, true); |
| 3310 | qpnp_iadc_resume_calibration(chip->iadc_dev); |
Abhijeet Dharmapurikar | 84b13dd | 2013-07-08 18:43:56 -0700 | [diff] [blame] | 3311 | } |
| 3312 | } |
| 3313 | } |
Abhijeet Dharmapurikar | 604461d | 2013-07-09 13:34:33 -0700 | [diff] [blame] | 3314 | |
Xiaozhe Shi | 890fbf4 | 2013-05-02 16:42:53 -0700 | [diff] [blame] | 3315 | static void battery_insertion_check(struct qpnp_bms_chip *chip) |
| 3316 | { |
Xiaozhe Shi | 90f3a41 | 2013-08-21 10:31:35 -0700 | [diff] [blame] | 3317 | int present = (int)is_battery_present(chip); |
Xiaozhe Shi | 24f91a0 | 2013-08-29 17:15:05 -0700 | [diff] [blame] | 3318 | int insertion_ocv_uv = get_battery_insertion_ocv_uv(chip); |
| 3319 | int insertion_ocv_taken = (insertion_ocv_uv > 0); |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 3320 | |
| 3321 | mutex_lock(&chip->vbat_monitor_mutex); |
Xiaozhe Shi | 24f91a0 | 2013-08-29 17:15:05 -0700 | [diff] [blame] | 3322 | if (chip->battery_present != present |
| 3323 | && (present == insertion_ocv_taken |
| 3324 | || chip->battery_present == -EINVAL)) { |
| 3325 | pr_debug("status = %d, shadow status = %d, insertion_ocv_uv = %d\n", |
| 3326 | present, chip->battery_present, |
| 3327 | insertion_ocv_uv); |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 3328 | if (chip->battery_present != -EINVAL) { |
| 3329 | if (present) { |
Xiaozhe Shi | 24f91a0 | 2013-08-29 17:15:05 -0700 | [diff] [blame] | 3330 | chip->insertion_ocv_uv = insertion_ocv_uv; |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 3331 | setup_vbat_monitoring(chip); |
| 3332 | chip->new_battery = true; |
| 3333 | } else { |
| 3334 | reset_vbat_monitoring(chip); |
| 3335 | } |
| 3336 | } |
| 3337 | chip->battery_present = present; |
| 3338 | /* a new battery was inserted or removed, so force a soc |
| 3339 | * recalculation to update the SoC */ |
| 3340 | schedule_work(&chip->recalc_work); |
| 3341 | } |
| 3342 | mutex_unlock(&chip->vbat_monitor_mutex); |
| 3343 | } |
| 3344 | |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 3345 | /* Returns capacity as a SoC percentage between 0 and 100 */ |
| 3346 | static int get_prop_bms_capacity(struct qpnp_bms_chip *chip) |
| 3347 | { |
Xiaozhe Shi | 79d6c1d | 2012-11-26 13:19:50 -0800 | [diff] [blame] | 3348 | return report_state_of_charge(chip); |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 3349 | } |
| 3350 | |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 3351 | static void qpnp_bms_external_power_changed(struct power_supply *psy) |
| 3352 | { |
Xiaozhe Shi | 890fbf4 | 2013-05-02 16:42:53 -0700 | [diff] [blame] | 3353 | struct qpnp_bms_chip *chip = container_of(psy, struct qpnp_bms_chip, |
| 3354 | bms_psy); |
| 3355 | |
| 3356 | battery_insertion_check(chip); |
Abhijeet Dharmapurikar | 84b13dd | 2013-07-08 18:43:56 -0700 | [diff] [blame] | 3357 | batfet_status_check(chip); |
Xiaozhe Shi | 890fbf4 | 2013-05-02 16:42:53 -0700 | [diff] [blame] | 3358 | battery_status_check(chip); |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 3359 | } |
| 3360 | |
| 3361 | static int qpnp_bms_power_get_property(struct power_supply *psy, |
| 3362 | enum power_supply_property psp, |
| 3363 | union power_supply_propval *val) |
| 3364 | { |
| 3365 | struct qpnp_bms_chip *chip = container_of(psy, struct qpnp_bms_chip, |
| 3366 | bms_psy); |
| 3367 | |
| 3368 | switch (psp) { |
| 3369 | case POWER_SUPPLY_PROP_CAPACITY: |
| 3370 | val->intval = get_prop_bms_capacity(chip); |
| 3371 | break; |
Xiaozhe Shi | bda8499 | 2013-09-05 10:39:11 -0700 | [diff] [blame] | 3372 | case POWER_SUPPLY_PROP_STATUS: |
| 3373 | val->intval = chip->battery_status; |
| 3374 | break; |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 3375 | case POWER_SUPPLY_PROP_CURRENT_NOW: |
| 3376 | val->intval = get_prop_bms_current_now(chip); |
| 3377 | break; |
Xiaozhe Shi | 6dc56f1 | 2013-05-02 15:56:55 -0700 | [diff] [blame] | 3378 | case POWER_SUPPLY_PROP_RESISTANCE: |
| 3379 | val->intval = get_prop_bms_batt_resistance(chip); |
| 3380 | break; |
Xiaozhe Shi | fb37f3b | 2013-05-20 16:56:19 -0700 | [diff] [blame] | 3381 | case POWER_SUPPLY_PROP_CHARGE_COUNTER: |
| 3382 | val->intval = get_prop_bms_charge_counter(chip); |
| 3383 | break; |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 3384 | case POWER_SUPPLY_PROP_CHARGE_COUNTER_SHADOW: |
| 3385 | val->intval = get_prop_bms_charge_counter_shadow(chip); |
| 3386 | break; |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 3387 | case POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN: |
| 3388 | val->intval = get_prop_bms_charge_full_design(chip); |
| 3389 | break; |
Anirudh Ghayal | c9d981a | 2013-06-24 09:50:33 +0530 | [diff] [blame] | 3390 | case POWER_SUPPLY_PROP_CHARGE_FULL: |
| 3391 | val->intval = get_prop_bms_charge_full(chip); |
| 3392 | break; |
Anirudh Ghayal | 9dd582d | 2013-06-07 17:48:58 +0530 | [diff] [blame] | 3393 | case POWER_SUPPLY_PROP_CYCLE_COUNT: |
| 3394 | val->intval = chip->charge_cycles; |
| 3395 | break; |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 3396 | default: |
| 3397 | return -EINVAL; |
| 3398 | } |
| 3399 | return 0; |
| 3400 | } |
| 3401 | |
Xiaozhe Shi | bdf1474 | 2012-12-05 12:41:48 -0800 | [diff] [blame] | 3402 | #define OCV_USE_LIMIT_EN BIT(7) |
| 3403 | static int set_ocv_voltage_thresholds(struct qpnp_bms_chip *chip, |
| 3404 | int low_voltage_threshold, |
| 3405 | int high_voltage_threshold) |
| 3406 | { |
| 3407 | uint16_t low_voltage_raw, high_voltage_raw; |
| 3408 | int rc; |
| 3409 | |
| 3410 | low_voltage_raw = convert_vbatt_uv_to_raw(chip, |
| 3411 | low_voltage_threshold); |
| 3412 | high_voltage_raw = convert_vbatt_uv_to_raw(chip, |
| 3413 | high_voltage_threshold); |
| 3414 | rc = qpnp_write_wrapper(chip, (u8 *)&low_voltage_raw, |
| 3415 | chip->base + BMS1_OCV_USE_LOW_LIMIT_THR0, 2); |
| 3416 | if (rc) { |
| 3417 | pr_err("Failed to set ocv low voltage threshold: %d\n", rc); |
| 3418 | return rc; |
| 3419 | } |
| 3420 | rc = qpnp_write_wrapper(chip, (u8 *)&high_voltage_raw, |
| 3421 | chip->base + BMS1_OCV_USE_HIGH_LIMIT_THR0, 2); |
| 3422 | if (rc) { |
| 3423 | pr_err("Failed to set ocv high voltage threshold: %d\n", rc); |
| 3424 | return rc; |
| 3425 | } |
| 3426 | rc = qpnp_masked_write(chip, BMS1_OCV_USE_LIMIT_CTL, |
| 3427 | OCV_USE_LIMIT_EN, OCV_USE_LIMIT_EN); |
| 3428 | if (rc) { |
| 3429 | pr_err("Failed to enabled ocv voltage thresholds: %d\n", rc); |
| 3430 | return rc; |
| 3431 | } |
| 3432 | pr_debug("ocv low threshold set to %d uv or 0x%x raw\n", |
| 3433 | low_voltage_threshold, low_voltage_raw); |
| 3434 | pr_debug("ocv high threshold set to %d uv or 0x%x raw\n", |
| 3435 | high_voltage_threshold, high_voltage_raw); |
| 3436 | return 0; |
| 3437 | } |
| 3438 | |
Xiaozhe Shi | f9f9924 | 2013-08-29 12:27:50 -0700 | [diff] [blame] | 3439 | static int read_shutdown_iavg_ma(struct qpnp_bms_chip *chip) |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3440 | { |
Xiaozhe Shi | f9f9924 | 2013-08-29 12:27:50 -0700 | [diff] [blame] | 3441 | u8 iavg; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3442 | int rc; |
Xiaozhe Shi | 12b25be | 2013-08-29 11:51:59 -0700 | [diff] [blame] | 3443 | |
Xiaozhe Shi | f9f9924 | 2013-08-29 12:27:50 -0700 | [diff] [blame] | 3444 | rc = qpnp_read_wrapper(chip, &iavg, chip->base + IAVG_STORAGE_REG, 1); |
| 3445 | if (rc) { |
| 3446 | pr_err("failed to read addr = %d %d assuming %d\n", |
| 3447 | chip->base + IAVG_STORAGE_REG, rc, |
Xiaozhe Shi | 68a1bb2 | 2013-09-23 14:52:00 -0700 | [diff] [blame] | 3448 | MIN_IAVG_MA); |
| 3449 | return MIN_IAVG_MA; |
Xiaozhe Shi | f9f9924 | 2013-08-29 12:27:50 -0700 | [diff] [blame] | 3450 | } else if (iavg == IAVG_INVALID) { |
| 3451 | pr_err("invalid iavg read from BMS1_DATA_REG_1, using %d\n", |
Xiaozhe Shi | 68a1bb2 | 2013-09-23 14:52:00 -0700 | [diff] [blame] | 3452 | MIN_IAVG_MA); |
| 3453 | return MIN_IAVG_MA; |
Xiaozhe Shi | f9f9924 | 2013-08-29 12:27:50 -0700 | [diff] [blame] | 3454 | } else { |
| 3455 | if (iavg == 0) |
Xiaozhe Shi | 68a1bb2 | 2013-09-23 14:52:00 -0700 | [diff] [blame] | 3456 | return MIN_IAVG_MA; |
Xiaozhe Shi | f9f9924 | 2013-08-29 12:27:50 -0700 | [diff] [blame] | 3457 | else |
Xiaozhe Shi | 68a1bb2 | 2013-09-23 14:52:00 -0700 | [diff] [blame] | 3458 | return MIN_IAVG_MA + IAVG_STEP_SIZE_MA * iavg; |
Xiaozhe Shi | f9f9924 | 2013-08-29 12:27:50 -0700 | [diff] [blame] | 3459 | } |
| 3460 | } |
| 3461 | |
| 3462 | static int read_shutdown_soc(struct qpnp_bms_chip *chip) |
| 3463 | { |
| 3464 | u8 stored_soc; |
| 3465 | int rc, shutdown_soc; |
| 3466 | |
| 3467 | /* |
| 3468 | * The previous SOC is stored in the first 7 bits of the register as |
| 3469 | * (Shutdown SOC + 1). This allows for register reset values of both |
| 3470 | * 0x00 and 0x7F. |
| 3471 | */ |
| 3472 | rc = qpnp_read_wrapper(chip, &stored_soc, chip->soc_storage_addr, 1); |
Xiaozhe Shi | 12b25be | 2013-08-29 11:51:59 -0700 | [diff] [blame] | 3473 | if (rc) { |
| 3474 | pr_err("failed to read addr = %d %d\n", |
| 3475 | chip->soc_storage_addr, rc); |
Xiaozhe Shi | f9f9924 | 2013-08-29 12:27:50 -0700 | [diff] [blame] | 3476 | return SOC_INVALID; |
Xiaozhe Shi | 12b25be | 2013-08-29 11:51:59 -0700 | [diff] [blame] | 3477 | } |
| 3478 | |
Xiaozhe Shi | f9f9924 | 2013-08-29 12:27:50 -0700 | [diff] [blame] | 3479 | if ((stored_soc >> 1) > 0) |
| 3480 | shutdown_soc = (stored_soc >> 1) - 1; |
| 3481 | else |
| 3482 | shutdown_soc = SOC_INVALID; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3483 | |
Xiaozhe Shi | f9f9924 | 2013-08-29 12:27:50 -0700 | [diff] [blame] | 3484 | pr_debug("stored soc = 0x%02x, shutdown_soc = %d\n", |
| 3485 | stored_soc, shutdown_soc); |
| 3486 | return shutdown_soc; |
| 3487 | } |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3488 | |
Xiaozhe Shi | f9f9924 | 2013-08-29 12:27:50 -0700 | [diff] [blame] | 3489 | #define BAT_REMOVED_OFFMODE_BIT BIT(6) |
| 3490 | static bool is_battery_replaced_in_offmode(struct qpnp_bms_chip *chip) |
| 3491 | { |
| 3492 | u8 batt_pres; |
| 3493 | int rc; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3494 | |
Xiaozhe Shi | f9f9924 | 2013-08-29 12:27:50 -0700 | [diff] [blame] | 3495 | if (chip->batt_pres_addr) { |
Xiaozhe Shi | 12b25be | 2013-08-29 11:51:59 -0700 | [diff] [blame] | 3496 | rc = qpnp_read_wrapper(chip, &batt_pres, |
| 3497 | chip->batt_pres_addr, 1); |
| 3498 | pr_debug("offmode removed: %02x\n", batt_pres); |
Xiaozhe Shi | f9f9924 | 2013-08-29 12:27:50 -0700 | [diff] [blame] | 3499 | if (!rc && (batt_pres & BAT_REMOVED_OFFMODE_BIT)) |
| 3500 | return true; |
| 3501 | } |
| 3502 | return false; |
| 3503 | } |
| 3504 | |
| 3505 | static void load_shutdown_data(struct qpnp_bms_chip *chip) |
| 3506 | { |
| 3507 | int calculated_soc, shutdown_soc; |
| 3508 | bool invalid_stored_soc; |
| 3509 | bool offmode_battery_replaced; |
| 3510 | bool shutdown_soc_out_of_limit; |
| 3511 | |
| 3512 | /* |
| 3513 | * Read the saved shutdown SoC from the configured register and |
| 3514 | * check if the value has been reset |
| 3515 | */ |
| 3516 | shutdown_soc = read_shutdown_soc(chip); |
| 3517 | invalid_stored_soc = (shutdown_soc == SOC_INVALID); |
| 3518 | |
| 3519 | /* |
| 3520 | * Do a quick run of SoC calculation to find whether the shutdown soc |
| 3521 | * is close enough. |
| 3522 | */ |
| 3523 | calculated_soc = recalculate_raw_soc(chip); |
| 3524 | shutdown_soc_out_of_limit = (abs(shutdown_soc - calculated_soc) |
| 3525 | > chip->shutdown_soc_valid_limit); |
| 3526 | pr_debug("calculated_soc = %d, valid_limit = %d\n", |
| 3527 | calculated_soc, chip->shutdown_soc_valid_limit); |
| 3528 | |
| 3529 | /* |
| 3530 | * Check if the battery has been replaced while the system was powered |
| 3531 | * down. |
| 3532 | */ |
| 3533 | offmode_battery_replaced = is_battery_replaced_in_offmode(chip); |
| 3534 | |
| 3535 | /* Invalidate the shutdown SoC if any of these conditions hold true */ |
| 3536 | if (chip->ignore_shutdown_soc |
| 3537 | || invalid_stored_soc |
| 3538 | || offmode_battery_replaced |
| 3539 | || shutdown_soc_out_of_limit) { |
| 3540 | chip->battery_removed = true; |
| 3541 | chip->shutdown_soc_invalid = true; |
Xiaozhe Shi | c92cfd9 | 2013-10-25 11:36:42 -0700 | [diff] [blame] | 3542 | chip->shutdown_iavg_ma = MIN_IAVG_MA; |
Xiaozhe Shi | f9f9924 | 2013-08-29 12:27:50 -0700 | [diff] [blame] | 3543 | pr_debug("Ignoring shutdown SoC: invalid = %d, offmode = %d, out_of_limit = %d\n", |
| 3544 | invalid_stored_soc, offmode_battery_replaced, |
| 3545 | shutdown_soc_out_of_limit); |
| 3546 | } else { |
| 3547 | chip->shutdown_iavg_ma = read_shutdown_iavg_ma(chip); |
| 3548 | chip->shutdown_soc = shutdown_soc; |
Xiaozhe Shi | 7c41a29 | 2013-08-16 16:50:17 -0700 | [diff] [blame] | 3549 | } |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 3550 | |
Xiaozhe Shi | f9f9924 | 2013-08-29 12:27:50 -0700 | [diff] [blame] | 3551 | pr_debug("raw_soc = %d shutdown_soc = %d shutdown_iavg = %d shutdown_soc_invalid = %d, battery_removed = %d\n", |
| 3552 | calculated_soc, |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3553 | chip->shutdown_soc, |
| 3554 | chip->shutdown_iavg_ma, |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 3555 | chip->shutdown_soc_invalid, |
| 3556 | chip->battery_removed); |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3557 | } |
| 3558 | |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 3559 | static irqreturn_t bms_ocv_thr_irq_handler(int irq, void *_chip) |
| 3560 | { |
| 3561 | struct qpnp_bms_chip *chip = _chip; |
| 3562 | |
| 3563 | pr_debug("ocv_thr irq triggered\n"); |
| 3564 | bms_stay_awake(&chip->soc_wake_source); |
| 3565 | schedule_work(&chip->recalc_work); |
| 3566 | return IRQ_HANDLED; |
| 3567 | } |
| 3568 | |
| 3569 | static irqreturn_t bms_sw_cc_thr_irq_handler(int irq, void *_chip) |
| 3570 | { |
| 3571 | struct qpnp_bms_chip *chip = _chip; |
| 3572 | |
| 3573 | pr_debug("sw_cc_thr irq triggered\n"); |
Anirudh Ghayal | 1166eef | 2013-12-23 19:05:33 +0530 | [diff] [blame] | 3574 | disable_bms_irq_nosync(&chip->sw_cc_thr_irq); |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 3575 | bms_stay_awake(&chip->soc_wake_source); |
| 3576 | schedule_work(&chip->recalc_work); |
| 3577 | return IRQ_HANDLED; |
| 3578 | } |
| 3579 | |
Xiaozhe Shi | af203c2 | 2013-06-19 12:01:38 -0700 | [diff] [blame] | 3580 | static int64_t read_battery_id(struct qpnp_bms_chip *chip) |
Xiaozhe Shi | 73a6569 | 2012-09-18 17:51:57 -0700 | [diff] [blame] | 3581 | { |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3582 | int rc; |
| 3583 | struct qpnp_vadc_result result; |
| 3584 | |
Siddartha Mohanadoss | 3cb2b6b | 2013-06-21 12:07:05 -0700 | [diff] [blame] | 3585 | rc = qpnp_vadc_read(chip->vadc_dev, LR_MUX2_BAT_ID, &result); |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3586 | if (rc) { |
| 3587 | pr_err("error reading batt id channel = %d, rc = %d\n", |
| 3588 | LR_MUX2_BAT_ID, rc); |
| 3589 | return rc; |
| 3590 | } |
Xiaozhe Shi | af203c2 | 2013-06-19 12:01:38 -0700 | [diff] [blame] | 3591 | |
| 3592 | return result.physical; |
Xiaozhe Shi | 73a6569 | 2012-09-18 17:51:57 -0700 | [diff] [blame] | 3593 | } |
| 3594 | |
| 3595 | static int set_battery_data(struct qpnp_bms_chip *chip) |
| 3596 | { |
| 3597 | int64_t battery_id; |
Xiaozhe Shi | 81f66b5 | 2013-09-20 11:43:52 -0700 | [diff] [blame] | 3598 | int rc = 0, dt_data = false; |
Xiaozhe Shi | 77a5b05 | 2012-12-14 16:37:45 -0800 | [diff] [blame] | 3599 | struct bms_battery_data *batt_data; |
Xiaozhe Shi | af203c2 | 2013-06-19 12:01:38 -0700 | [diff] [blame] | 3600 | struct device_node *node; |
Xiaozhe Shi | 73a6569 | 2012-09-18 17:51:57 -0700 | [diff] [blame] | 3601 | |
Xiaozhe Shi | 77a5b05 | 2012-12-14 16:37:45 -0800 | [diff] [blame] | 3602 | if (chip->batt_type == BATT_DESAY) { |
| 3603 | batt_data = &desay_5200_data; |
| 3604 | } else if (chip->batt_type == BATT_PALLADIUM) { |
| 3605 | batt_data = &palladium_1500_data; |
| 3606 | } else if (chip->batt_type == BATT_OEM) { |
| 3607 | batt_data = &oem_batt_data; |
Wu Fenglin | 2ac88aa | 2013-04-25 12:43:40 +0800 | [diff] [blame] | 3608 | } else if (chip->batt_type == BATT_QRD_4V35_2000MAH) { |
| 3609 | batt_data = &QRD_4v35_2000mAh_data; |
tingting | f50326f | 2013-06-05 15:07:24 +0800 | [diff] [blame] | 3610 | } else if (chip->batt_type == BATT_QRD_4V2_1300MAH) { |
| 3611 | batt_data = &qrd_4v2_1300mah_data; |
Xiaozhe Shi | 73a6569 | 2012-09-18 17:51:57 -0700 | [diff] [blame] | 3612 | } else { |
Xiaozhe Shi | 77a5b05 | 2012-12-14 16:37:45 -0800 | [diff] [blame] | 3613 | battery_id = read_battery_id(chip); |
| 3614 | if (battery_id < 0) { |
| 3615 | pr_err("cannot read battery id err = %lld\n", |
| 3616 | battery_id); |
| 3617 | return battery_id; |
| 3618 | } |
| 3619 | |
Xiaozhe Shi | af203c2 | 2013-06-19 12:01:38 -0700 | [diff] [blame] | 3620 | node = of_find_node_by_name(chip->spmi->dev.of_node, |
| 3621 | "qcom,battery-data"); |
Xiaozhe Shi | 81f66b5 | 2013-09-20 11:43:52 -0700 | [diff] [blame] | 3622 | if (!node) { |
| 3623 | pr_warn("No available batterydata, using palladium 1500\n"); |
| 3624 | batt_data = &palladium_1500_data; |
| 3625 | goto assign_data; |
| 3626 | } |
| 3627 | batt_data = devm_kzalloc(chip->dev, |
| 3628 | sizeof(struct bms_battery_data), GFP_KERNEL); |
| 3629 | if (!batt_data) { |
| 3630 | pr_err("Could not alloc battery data\n"); |
| 3631 | batt_data = &palladium_1500_data; |
| 3632 | goto assign_data; |
| 3633 | } |
| 3634 | batt_data->fcc_temp_lut = devm_kzalloc(chip->dev, |
| 3635 | sizeof(struct single_row_lut), |
| 3636 | GFP_KERNEL); |
| 3637 | batt_data->pc_temp_ocv_lut = devm_kzalloc(chip->dev, |
| 3638 | sizeof(struct pc_temp_ocv_lut), |
| 3639 | GFP_KERNEL); |
| 3640 | batt_data->rbatt_sf_lut = devm_kzalloc(chip->dev, |
| 3641 | sizeof(struct sf_lut), |
| 3642 | GFP_KERNEL); |
Xiaozhe Shi | af203c2 | 2013-06-19 12:01:38 -0700 | [diff] [blame] | 3643 | |
Xiaozhe Shi | 81f66b5 | 2013-09-20 11:43:52 -0700 | [diff] [blame] | 3644 | batt_data->max_voltage_uv = -1; |
| 3645 | batt_data->cutoff_uv = -1; |
| 3646 | batt_data->iterm_ua = -1; |
Xiaozhe Shi | 23174ea | 2013-07-30 17:51:09 -0700 | [diff] [blame] | 3647 | |
Xiaozhe Shi | 81f66b5 | 2013-09-20 11:43:52 -0700 | [diff] [blame] | 3648 | /* |
| 3649 | * if the alloced luts are 0s, of_batterydata_read_data ignores |
| 3650 | * them. |
| 3651 | */ |
| 3652 | rc = of_batterydata_read_data(node, batt_data, battery_id); |
| 3653 | if (rc == 0 && batt_data->fcc_temp_lut |
| 3654 | && batt_data->pc_temp_ocv_lut |
| 3655 | && batt_data->rbatt_sf_lut) { |
| 3656 | dt_data = true; |
Xiaozhe Shi | 77a5b05 | 2012-12-14 16:37:45 -0800 | [diff] [blame] | 3657 | } else { |
Xiaozhe Shi | 81f66b5 | 2013-09-20 11:43:52 -0700 | [diff] [blame] | 3658 | pr_err("battery data load failed, using palladium 1500\n"); |
| 3659 | devm_kfree(chip->dev, batt_data->fcc_temp_lut); |
| 3660 | devm_kfree(chip->dev, batt_data->pc_temp_ocv_lut); |
| 3661 | devm_kfree(chip->dev, batt_data->rbatt_sf_lut); |
| 3662 | devm_kfree(chip->dev, batt_data); |
Xiaozhe Shi | 77a5b05 | 2012-12-14 16:37:45 -0800 | [diff] [blame] | 3663 | batt_data = &palladium_1500_data; |
| 3664 | } |
Xiaozhe Shi | 73a6569 | 2012-09-18 17:51:57 -0700 | [diff] [blame] | 3665 | } |
| 3666 | |
Xiaozhe Shi | 81f66b5 | 2013-09-20 11:43:52 -0700 | [diff] [blame] | 3667 | assign_data: |
Xiaozhe Shi | 976618f | 2013-04-30 10:49:30 -0700 | [diff] [blame] | 3668 | chip->fcc_mah = batt_data->fcc; |
Xiaozhe Shi | 77a5b05 | 2012-12-14 16:37:45 -0800 | [diff] [blame] | 3669 | chip->fcc_temp_lut = batt_data->fcc_temp_lut; |
| 3670 | chip->fcc_sf_lut = batt_data->fcc_sf_lut; |
| 3671 | chip->pc_temp_ocv_lut = batt_data->pc_temp_ocv_lut; |
| 3672 | chip->pc_sf_lut = batt_data->pc_sf_lut; |
| 3673 | chip->rbatt_sf_lut = batt_data->rbatt_sf_lut; |
| 3674 | chip->default_rbatt_mohm = batt_data->default_rbatt_mohm; |
Xiaozhe Shi | 1a10aff | 2013-04-01 15:40:05 -0700 | [diff] [blame] | 3675 | chip->rbatt_capacitive_mohm = batt_data->rbatt_capacitive_mohm; |
Xiaozhe Shi | 0ac7a00 | 2013-03-26 13:14:03 -0700 | [diff] [blame] | 3676 | chip->flat_ocv_threshold_uv = batt_data->flat_ocv_threshold_uv; |
Xiaozhe Shi | 77a5b05 | 2012-12-14 16:37:45 -0800 | [diff] [blame] | 3677 | |
Xiaozhe Shi | af203c2 | 2013-06-19 12:01:38 -0700 | [diff] [blame] | 3678 | /* Override battery properties if specified in the battery profile */ |
Xiaozhe Shi | 23174ea | 2013-07-30 17:51:09 -0700 | [diff] [blame] | 3679 | if (batt_data->max_voltage_uv >= 0 && dt_data) |
Xiaozhe Shi | af203c2 | 2013-06-19 12:01:38 -0700 | [diff] [blame] | 3680 | chip->max_voltage_uv = batt_data->max_voltage_uv; |
Xiaozhe Shi | 23174ea | 2013-07-30 17:51:09 -0700 | [diff] [blame] | 3681 | if (batt_data->cutoff_uv >= 0 && dt_data) |
Xiaozhe Shi | af203c2 | 2013-06-19 12:01:38 -0700 | [diff] [blame] | 3682 | chip->v_cutoff_uv = batt_data->cutoff_uv; |
Xiaozhe Shi | 23174ea | 2013-07-30 17:51:09 -0700 | [diff] [blame] | 3683 | if (batt_data->iterm_ua >= 0 && dt_data) |
Xiaozhe Shi | af203c2 | 2013-06-19 12:01:38 -0700 | [diff] [blame] | 3684 | chip->chg_term_ua = batt_data->iterm_ua; |
| 3685 | |
Xiaozhe Shi | 77a5b05 | 2012-12-14 16:37:45 -0800 | [diff] [blame] | 3686 | if (chip->pc_temp_ocv_lut == NULL) { |
Xiaozhe Shi | 81f66b5 | 2013-09-20 11:43:52 -0700 | [diff] [blame] | 3687 | pr_err("temp ocv lut table has not been loaded\n"); |
| 3688 | if (dt_data) { |
| 3689 | devm_kfree(chip->dev, batt_data->fcc_temp_lut); |
| 3690 | devm_kfree(chip->dev, batt_data->pc_temp_ocv_lut); |
| 3691 | devm_kfree(chip->dev, batt_data->rbatt_sf_lut); |
| 3692 | devm_kfree(chip->dev, batt_data); |
| 3693 | } |
Xiaozhe Shi | 77a5b05 | 2012-12-14 16:37:45 -0800 | [diff] [blame] | 3694 | return -EINVAL; |
| 3695 | } |
Xiaozhe Shi | 81f66b5 | 2013-09-20 11:43:52 -0700 | [diff] [blame] | 3696 | |
| 3697 | if (dt_data) |
| 3698 | devm_kfree(chip->dev, batt_data); |
| 3699 | |
Xiaozhe Shi | 77a5b05 | 2012-12-14 16:37:45 -0800 | [diff] [blame] | 3700 | return 0; |
Xiaozhe Shi | 73a6569 | 2012-09-18 17:51:57 -0700 | [diff] [blame] | 3701 | } |
| 3702 | |
Siddartha Mohanadoss | 88a3fde | 2013-06-24 16:18:52 -0700 | [diff] [blame] | 3703 | static int bms_get_adc(struct qpnp_bms_chip *chip, |
| 3704 | struct spmi_device *spmi) |
| 3705 | { |
| 3706 | int rc = 0; |
| 3707 | |
| 3708 | chip->vadc_dev = qpnp_get_vadc(&spmi->dev, "bms"); |
| 3709 | if (IS_ERR(chip->vadc_dev)) { |
| 3710 | rc = PTR_ERR(chip->vadc_dev); |
| 3711 | if (rc != -EPROBE_DEFER) |
| 3712 | pr_err("vadc property missing, rc=%d\n", rc); |
| 3713 | return rc; |
| 3714 | } |
| 3715 | |
| 3716 | chip->iadc_dev = qpnp_get_iadc(&spmi->dev, "bms"); |
| 3717 | if (IS_ERR(chip->iadc_dev)) { |
| 3718 | rc = PTR_ERR(chip->iadc_dev); |
| 3719 | if (rc != -EPROBE_DEFER) |
| 3720 | pr_err("iadc property missing, rc=%d\n", rc); |
| 3721 | return rc; |
| 3722 | } |
| 3723 | |
| 3724 | chip->adc_tm_dev = qpnp_get_adc_tm(&spmi->dev, "bms"); |
| 3725 | if (IS_ERR(chip->adc_tm_dev)) { |
| 3726 | rc = PTR_ERR(chip->adc_tm_dev); |
| 3727 | if (rc != -EPROBE_DEFER) |
| 3728 | pr_err("adc-tm not ready, defer probe\n"); |
| 3729 | return rc; |
| 3730 | } |
| 3731 | |
| 3732 | return 0; |
| 3733 | } |
| 3734 | |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3735 | #define SPMI_PROP_READ(chip_prop, qpnp_spmi_property, retval) \ |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 3736 | do { \ |
Xiaozhe Shi | 2e47668 | 2013-07-22 14:57:22 -0700 | [diff] [blame] | 3737 | if (retval) \ |
| 3738 | break; \ |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3739 | retval = of_property_read_u32(chip->spmi->dev.of_node, \ |
Xiaozhe Shi | 9bd2462 | 2013-01-23 15:54:54 -0800 | [diff] [blame] | 3740 | "qcom," qpnp_spmi_property, \ |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 3741 | &chip->chip_prop); \ |
| 3742 | if (retval) { \ |
| 3743 | pr_err("Error reading " #qpnp_spmi_property \ |
| 3744 | " property %d\n", rc); \ |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 3745 | } \ |
| 3746 | } while (0) |
| 3747 | |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 3748 | #define SPMI_PROP_READ_BOOL(chip_prop, qpnp_spmi_property) \ |
| 3749 | do { \ |
| 3750 | chip->chip_prop = of_property_read_bool(chip->spmi->dev.of_node,\ |
| 3751 | "qcom," qpnp_spmi_property); \ |
| 3752 | } while (0) |
| 3753 | |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3754 | static inline int bms_read_properties(struct qpnp_bms_chip *chip) |
| 3755 | { |
Xiaozhe Shi | 2e47668 | 2013-07-22 14:57:22 -0700 | [diff] [blame] | 3756 | int rc = 0; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3757 | |
Xiaozhe Shi | d0a7954 | 2012-11-06 10:00:38 -0800 | [diff] [blame] | 3758 | SPMI_PROP_READ(r_sense_uohm, "r-sense-uohm", rc); |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3759 | SPMI_PROP_READ(v_cutoff_uv, "v-cutoff-uv", rc); |
| 3760 | SPMI_PROP_READ(max_voltage_uv, "max-voltage-uv", rc); |
| 3761 | SPMI_PROP_READ(r_conn_mohm, "r-conn-mohm", rc); |
| 3762 | SPMI_PROP_READ(chg_term_ua, "chg-term-ua", rc); |
| 3763 | SPMI_PROP_READ(shutdown_soc_valid_limit, |
| 3764 | "shutdown-soc-valid-limit", rc); |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3765 | SPMI_PROP_READ(adjust_soc_low_threshold, |
| 3766 | "adjust-soc-low-threshold", rc); |
| 3767 | SPMI_PROP_READ(batt_type, "batt-type", rc); |
| 3768 | SPMI_PROP_READ(low_soc_calc_threshold, |
| 3769 | "low-soc-calculate-soc-threshold", rc); |
| 3770 | SPMI_PROP_READ(low_soc_calculate_soc_ms, |
| 3771 | "low-soc-calculate-soc-ms", rc); |
Xiaozhe Shi | cb487b1 | 2013-10-14 17:42:07 -0700 | [diff] [blame] | 3772 | SPMI_PROP_READ(low_voltage_calculate_soc_ms, |
| 3773 | "low-voltage-calculate-soc-ms", rc); |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3774 | SPMI_PROP_READ(calculate_soc_ms, "calculate-soc-ms", rc); |
Xiaozhe Shi | 0ac7a00 | 2013-03-26 13:14:03 -0700 | [diff] [blame] | 3775 | SPMI_PROP_READ(high_ocv_correction_limit_uv, |
| 3776 | "high-ocv-correction-limit-uv", rc); |
| 3777 | SPMI_PROP_READ(low_ocv_correction_limit_uv, |
| 3778 | "low-ocv-correction-limit-uv", rc); |
| 3779 | SPMI_PROP_READ(hold_soc_est, |
| 3780 | "hold-soc-est", rc); |
| 3781 | SPMI_PROP_READ(ocv_high_threshold_uv, |
| 3782 | "ocv-voltage-high-threshold-uv", rc); |
Xiaozhe Shi | bdf1474 | 2012-12-05 12:41:48 -0800 | [diff] [blame] | 3783 | SPMI_PROP_READ(ocv_low_threshold_uv, |
| 3784 | "ocv-voltage-low-threshold-uv", rc); |
Xiaozhe Shi | 4be8578 | 2013-02-22 17:33:40 -0800 | [diff] [blame] | 3785 | SPMI_PROP_READ(low_voltage_threshold, "low-voltage-threshold", rc); |
Xiaozhe Shi | 535494d | 2013-04-05 12:27:51 -0700 | [diff] [blame] | 3786 | SPMI_PROP_READ(temperature_margin, "tm-temp-margin", rc); |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3787 | |
Xiaozhe Shi | 2e47668 | 2013-07-22 14:57:22 -0700 | [diff] [blame] | 3788 | chip->use_external_rsense = of_property_read_bool( |
| 3789 | chip->spmi->dev.of_node, |
| 3790 | "qcom,use-external-rsense"); |
| 3791 | chip->ignore_shutdown_soc = of_property_read_bool( |
| 3792 | chip->spmi->dev.of_node, |
| 3793 | "qcom,ignore-shutdown-soc"); |
| 3794 | chip->use_voltage_soc = of_property_read_bool(chip->spmi->dev.of_node, |
| 3795 | "qcom,use-voltage-soc"); |
| 3796 | chip->use_ocv_thresholds = of_property_read_bool( |
| 3797 | chip->spmi->dev.of_node, |
| 3798 | "qcom,use-ocv-thresholds"); |
| 3799 | |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3800 | if (chip->adjust_soc_low_threshold >= 45) |
| 3801 | chip->adjust_soc_low_threshold = 45; |
| 3802 | |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 3803 | SPMI_PROP_READ_BOOL(enable_fcc_learning, "enable-fcc-learning"); |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 3804 | if (chip->enable_fcc_learning) { |
| 3805 | SPMI_PROP_READ(min_fcc_learning_soc, |
| 3806 | "min-fcc-learning-soc", rc); |
| 3807 | SPMI_PROP_READ(min_fcc_ocv_pc, |
| 3808 | "min-fcc-ocv-pc", rc); |
| 3809 | SPMI_PROP_READ(min_fcc_learning_samples, |
| 3810 | "min-fcc-learning-samples", rc); |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 3811 | SPMI_PROP_READ(fcc_resolution, |
| 3812 | "fcc-resolution", rc); |
| 3813 | if (chip->min_fcc_learning_samples > MAX_FCC_CYCLES) |
| 3814 | chip->min_fcc_learning_samples = MAX_FCC_CYCLES; |
| 3815 | chip->fcc_learning_samples = devm_kzalloc(&chip->spmi->dev, |
| 3816 | (sizeof(struct fcc_sample) * |
| 3817 | chip->min_fcc_learning_samples), GFP_KERNEL); |
Xiaozhe Shi | 81f66b5 | 2013-09-20 11:43:52 -0700 | [diff] [blame] | 3818 | if (chip->fcc_learning_samples == NULL) |
| 3819 | return -ENOMEM; |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 3820 | pr_debug("min-fcc-soc=%d, min-fcc-pc=%d, min-fcc-cycles=%d\n", |
| 3821 | chip->min_fcc_learning_soc, chip->min_fcc_ocv_pc, |
| 3822 | chip->min_fcc_learning_samples); |
| 3823 | } |
| 3824 | |
Xiaozhe Shi | 2e47668 | 2013-07-22 14:57:22 -0700 | [diff] [blame] | 3825 | if (rc) { |
| 3826 | pr_err("Missing required properties.\n"); |
| 3827 | return rc; |
| 3828 | } |
| 3829 | |
Xiaozhe Shi | d0a7954 | 2012-11-06 10:00:38 -0800 | [diff] [blame] | 3830 | pr_debug("dts data: r_sense_uohm:%d, v_cutoff_uv:%d, max_v:%d\n", |
| 3831 | chip->r_sense_uohm, chip->v_cutoff_uv, |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3832 | chip->max_voltage_uv); |
| 3833 | pr_debug("r_conn:%d, shutdown_soc: %d, adjust_soc_low:%d\n", |
| 3834 | chip->r_conn_mohm, chip->shutdown_soc_valid_limit, |
| 3835 | chip->adjust_soc_low_threshold); |
Xiaozhe Shi | 561ebf7 | 2013-03-25 13:51:27 -0700 | [diff] [blame] | 3836 | pr_debug("chg_term_ua:%d, batt_type:%d\n", |
| 3837 | chip->chg_term_ua, |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3838 | chip->batt_type); |
Xiaozhe Shi | 781b0a2 | 2012-11-05 17:18:27 -0800 | [diff] [blame] | 3839 | pr_debug("ignore_shutdown_soc:%d, use_voltage_soc:%d\n", |
Xiaozhe Shi | 79d6c1d | 2012-11-26 13:19:50 -0800 | [diff] [blame] | 3840 | chip->ignore_shutdown_soc, chip->use_voltage_soc); |
Xiaozhe Shi | dffbe69 | 2012-12-11 15:35:46 -0800 | [diff] [blame] | 3841 | pr_debug("use external rsense: %d\n", chip->use_external_rsense); |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3842 | return 0; |
| 3843 | } |
| 3844 | |
| 3845 | static inline void bms_initialize_constants(struct qpnp_bms_chip *chip) |
| 3846 | { |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3847 | chip->prev_pc_unusable = -EINVAL; |
| 3848 | chip->soc_at_cv = -EINVAL; |
| 3849 | chip->calculated_soc = -EINVAL; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 3850 | chip->last_soc = -EINVAL; |
Xiaozhe Shi | 7edde5d | 2012-09-26 11:23:09 -0700 | [diff] [blame] | 3851 | chip->last_soc_est = -EINVAL; |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 3852 | chip->battery_present = -EINVAL; |
Xiaozhe Shi | 890fbf4 | 2013-05-02 16:42:53 -0700 | [diff] [blame] | 3853 | chip->battery_status = POWER_SUPPLY_STATUS_UNKNOWN; |
Xiaozhe Shi | f36d286 | 2013-01-04 10:17:35 -0800 | [diff] [blame] | 3854 | chip->last_cc_uah = INT_MIN; |
Abhijeet Dharmapurikar | 15f30fb | 2012-12-27 17:20:29 -0800 | [diff] [blame] | 3855 | chip->ocv_reading_at_100 = OCV_RAW_UNINITIALIZED; |
| 3856 | chip->prev_last_good_ocv_raw = OCV_RAW_UNINITIALIZED; |
Xiaozhe Shi | e118c69 | 2012-09-24 15:17:43 -0700 | [diff] [blame] | 3857 | chip->first_time_calc_soc = 1; |
| 3858 | chip->first_time_calc_uuc = 1; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 3859 | } |
| 3860 | |
Abhijeet Dharmapurikar | 3bd4bbf | 2013-07-01 12:06:37 -0700 | [diff] [blame] | 3861 | #define SPMI_FIND_IRQ(chip, irq_name) \ |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 3862 | do { \ |
| 3863 | chip->irq_name##_irq.irq = spmi_get_irq_byname(chip->spmi, \ |
| 3864 | resource, #irq_name); \ |
| 3865 | if (chip->irq_name##_irq.irq < 0) { \ |
| 3866 | pr_err("Unable to get " #irq_name " irq\n"); \ |
| 3867 | return -ENXIO; \ |
| 3868 | } \ |
Abhijeet Dharmapurikar | 3bd4bbf | 2013-07-01 12:06:37 -0700 | [diff] [blame] | 3869 | } while (0) |
| 3870 | |
| 3871 | static int bms_find_irqs(struct qpnp_bms_chip *chip, |
| 3872 | struct spmi_resource *resource) |
| 3873 | { |
| 3874 | SPMI_FIND_IRQ(chip, sw_cc_thr); |
| 3875 | SPMI_FIND_IRQ(chip, ocv_thr); |
| 3876 | return 0; |
| 3877 | } |
| 3878 | |
| 3879 | #define SPMI_REQUEST_IRQ(chip, rc, irq_name) \ |
| 3880 | do { \ |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 3881 | rc = devm_request_irq(chip->dev, chip->irq_name##_irq.irq, \ |
| 3882 | bms_##irq_name##_irq_handler, \ |
| 3883 | IRQF_TRIGGER_RISING, #irq_name, chip); \ |
| 3884 | if (rc < 0) { \ |
| 3885 | pr_err("Unable to request " #irq_name " irq: %d\n", rc);\ |
| 3886 | return -ENXIO; \ |
| 3887 | } \ |
Xiaozhe Shi | f511a6e | 2014-02-20 14:37:18 -0800 | [diff] [blame] | 3888 | chip->irq_name##_irq.ready = true; \ |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 3889 | } while (0) |
| 3890 | |
Abhijeet Dharmapurikar | 3bd4bbf | 2013-07-01 12:06:37 -0700 | [diff] [blame] | 3891 | static int bms_request_irqs(struct qpnp_bms_chip *chip) |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 3892 | { |
| 3893 | int rc; |
| 3894 | |
Abhijeet Dharmapurikar | 3bd4bbf | 2013-07-01 12:06:37 -0700 | [diff] [blame] | 3895 | SPMI_REQUEST_IRQ(chip, rc, sw_cc_thr); |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 3896 | enable_irq_wake(chip->sw_cc_thr_irq.irq); |
Abhijeet Dharmapurikar | 3bd4bbf | 2013-07-01 12:06:37 -0700 | [diff] [blame] | 3897 | SPMI_REQUEST_IRQ(chip, rc, ocv_thr); |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 3898 | enable_irq_wake(chip->ocv_thr_irq.irq); |
| 3899 | return 0; |
| 3900 | } |
| 3901 | |
Xiaozhe Shi | c40b397 | 2012-11-30 14:11:16 -0800 | [diff] [blame] | 3902 | #define REG_OFFSET_PERP_TYPE 0x04 |
| 3903 | #define REG_OFFSET_PERP_SUBTYPE 0x05 |
| 3904 | #define BMS_BMS_TYPE 0xD |
Xiaozhe Shi | ef6274c | 2013-03-06 15:23:52 -0800 | [diff] [blame] | 3905 | #define BMS_BMS1_SUBTYPE 0x1 |
Xiaozhe Shi | c40b397 | 2012-11-30 14:11:16 -0800 | [diff] [blame] | 3906 | #define BMS_IADC_TYPE 0x8 |
Xiaozhe Shi | ef6274c | 2013-03-06 15:23:52 -0800 | [diff] [blame] | 3907 | #define BMS_IADC1_SUBTYPE 0x3 |
| 3908 | #define BMS_IADC2_SUBTYPE 0x5 |
Xiaozhe Shi | c40b397 | 2012-11-30 14:11:16 -0800 | [diff] [blame] | 3909 | |
| 3910 | static int register_spmi(struct qpnp_bms_chip *chip, struct spmi_device *spmi) |
| 3911 | { |
| 3912 | struct spmi_resource *spmi_resource; |
| 3913 | struct resource *resource; |
| 3914 | int rc; |
| 3915 | u8 type, subtype; |
| 3916 | |
| 3917 | chip->dev = &(spmi->dev); |
| 3918 | chip->spmi = spmi; |
| 3919 | |
| 3920 | spmi_for_each_container_dev(spmi_resource, spmi) { |
| 3921 | if (!spmi_resource) { |
| 3922 | pr_err("qpnp_bms: spmi resource absent\n"); |
| 3923 | return -ENXIO; |
| 3924 | } |
| 3925 | |
| 3926 | resource = spmi_get_resource(spmi, spmi_resource, |
| 3927 | IORESOURCE_MEM, 0); |
| 3928 | if (!(resource && resource->start)) { |
| 3929 | pr_err("node %s IO resource absent!\n", |
| 3930 | spmi->dev.of_node->full_name); |
| 3931 | return -ENXIO; |
| 3932 | } |
| 3933 | |
Xiaozhe Shi | 7c41a29 | 2013-08-16 16:50:17 -0700 | [diff] [blame] | 3934 | pr_debug("Node name = %s\n", spmi_resource->of_node->name); |
| 3935 | |
| 3936 | if (strcmp("qcom,batt-pres-status", |
| 3937 | spmi_resource->of_node->name) == 0) { |
| 3938 | chip->batt_pres_addr = resource->start; |
| 3939 | continue; |
Xiaozhe Shi | 12b25be | 2013-08-29 11:51:59 -0700 | [diff] [blame] | 3940 | } else if (strcmp("qcom,soc-storage-reg", |
| 3941 | spmi_resource->of_node->name) == 0) { |
| 3942 | chip->soc_storage_addr = resource->start; |
| 3943 | continue; |
Xiaozhe Shi | 7c41a29 | 2013-08-16 16:50:17 -0700 | [diff] [blame] | 3944 | } |
| 3945 | |
Xiaozhe Shi | c40b397 | 2012-11-30 14:11:16 -0800 | [diff] [blame] | 3946 | rc = qpnp_read_wrapper(chip, &type, |
| 3947 | resource->start + REG_OFFSET_PERP_TYPE, 1); |
| 3948 | if (rc) { |
| 3949 | pr_err("Peripheral type read failed rc=%d\n", rc); |
| 3950 | return rc; |
| 3951 | } |
| 3952 | rc = qpnp_read_wrapper(chip, &subtype, |
| 3953 | resource->start + REG_OFFSET_PERP_SUBTYPE, 1); |
| 3954 | if (rc) { |
| 3955 | pr_err("Peripheral subtype read failed rc=%d\n", rc); |
| 3956 | return rc; |
| 3957 | } |
| 3958 | |
Xiaozhe Shi | ef6274c | 2013-03-06 15:23:52 -0800 | [diff] [blame] | 3959 | if (type == BMS_BMS_TYPE && subtype == BMS_BMS1_SUBTYPE) { |
Xiaozhe Shi | c40b397 | 2012-11-30 14:11:16 -0800 | [diff] [blame] | 3960 | chip->base = resource->start; |
Abhijeet Dharmapurikar | 3bd4bbf | 2013-07-01 12:06:37 -0700 | [diff] [blame] | 3961 | rc = bms_find_irqs(chip, spmi_resource); |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 3962 | if (rc) { |
Abhijeet Dharmapurikar | 3bd4bbf | 2013-07-01 12:06:37 -0700 | [diff] [blame] | 3963 | pr_err("Could not find irqs\n"); |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 3964 | return rc; |
| 3965 | } |
Xiaozhe Shi | c40b397 | 2012-11-30 14:11:16 -0800 | [diff] [blame] | 3966 | } else if (type == BMS_IADC_TYPE |
Xiaozhe Shi | ef6274c | 2013-03-06 15:23:52 -0800 | [diff] [blame] | 3967 | && (subtype == BMS_IADC1_SUBTYPE |
| 3968 | || subtype == BMS_IADC2_SUBTYPE)) { |
Xiaozhe Shi | c40b397 | 2012-11-30 14:11:16 -0800 | [diff] [blame] | 3969 | chip->iadc_base = resource->start; |
| 3970 | } else { |
| 3971 | pr_err("Invalid peripheral start=0x%x type=0x%x, subtype=0x%x\n", |
| 3972 | resource->start, type, subtype); |
| 3973 | } |
| 3974 | } |
| 3975 | |
| 3976 | if (chip->base == 0) { |
| 3977 | dev_err(&spmi->dev, "BMS peripheral was not registered\n"); |
| 3978 | return -EINVAL; |
| 3979 | } |
| 3980 | if (chip->iadc_base == 0) { |
| 3981 | dev_err(&spmi->dev, "BMS_IADC peripheral was not registered\n"); |
| 3982 | return -EINVAL; |
| 3983 | } |
Xiaozhe Shi | 12b25be | 2013-08-29 11:51:59 -0700 | [diff] [blame] | 3984 | if (chip->soc_storage_addr == 0) { |
| 3985 | /* default to dvdd backed BMS data reg0 */ |
| 3986 | chip->soc_storage_addr = chip->base + SOC_STORAGE_REG; |
| 3987 | } |
Xiaozhe Shi | c40b397 | 2012-11-30 14:11:16 -0800 | [diff] [blame] | 3988 | |
Xiaozhe Shi | 12b25be | 2013-08-29 11:51:59 -0700 | [diff] [blame] | 3989 | pr_debug("bms-base = 0x%04x, iadc-base = 0x%04x, bat-pres-reg = 0x%04x, soc-storage-reg = 0x%04x\n", |
| 3990 | chip->base, chip->iadc_base, |
| 3991 | chip->batt_pres_addr, chip->soc_storage_addr); |
Xiaozhe Shi | c40b397 | 2012-11-30 14:11:16 -0800 | [diff] [blame] | 3992 | return 0; |
| 3993 | } |
| 3994 | |
Abhijeet Dharmapurikar | 604461d | 2013-07-09 13:34:33 -0700 | [diff] [blame] | 3995 | #define ADC_CH_SEL_MASK 0x7 |
| 3996 | #define ADC_INT_RSNSN_CTL_MASK 0x3 |
| 3997 | #define ADC_INT_RSNSN_CTL_VALUE_EXT_RENSE 0x2 |
| 3998 | #define FAST_AVG_EN_MASK 0x80 |
| 3999 | #define FAST_AVG_EN_VALUE_EXT_RSENSE 0x80 |
Xiaozhe Shi | c40b397 | 2012-11-30 14:11:16 -0800 | [diff] [blame] | 4000 | static int read_iadc_channel_select(struct qpnp_bms_chip *chip) |
| 4001 | { |
| 4002 | u8 iadc_channel_select; |
Xiaozhe Shi | 767fdb6 | 2013-01-10 15:09:08 -0800 | [diff] [blame] | 4003 | int32_t rds_rsense_nohm; |
Xiaozhe Shi | c40b397 | 2012-11-30 14:11:16 -0800 | [diff] [blame] | 4004 | int rc; |
| 4005 | |
| 4006 | rc = qpnp_read_wrapper(chip, &iadc_channel_select, |
| 4007 | chip->iadc_base + IADC1_BMS_ADC_CH_SEL_CTL, 1); |
| 4008 | if (rc) { |
| 4009 | pr_err("Error reading bms_iadc channel register %d\n", rc); |
| 4010 | return rc; |
| 4011 | } |
| 4012 | |
| 4013 | iadc_channel_select &= ADC_CH_SEL_MASK; |
Xiaozhe Shi | 767fdb6 | 2013-01-10 15:09:08 -0800 | [diff] [blame] | 4014 | if (iadc_channel_select != EXTERNAL_RSENSE |
| 4015 | && iadc_channel_select != INTERNAL_RSENSE) { |
| 4016 | pr_err("IADC1_BMS_IADC configured incorrectly. Selected channel = %d\n", |
| 4017 | iadc_channel_select); |
| 4018 | return -EINVAL; |
| 4019 | } |
| 4020 | |
| 4021 | if (chip->use_external_rsense) { |
| 4022 | pr_debug("External rsense selected\n"); |
| 4023 | if (iadc_channel_select == INTERNAL_RSENSE) { |
| 4024 | pr_debug("Internal rsense detected; Changing rsense to external\n"); |
Xiaozhe Shi | dffbe69 | 2012-12-11 15:35:46 -0800 | [diff] [blame] | 4025 | rc = qpnp_masked_write_iadc(chip, |
| 4026 | IADC1_BMS_ADC_CH_SEL_CTL, |
| 4027 | ADC_CH_SEL_MASK, |
| 4028 | EXTERNAL_RSENSE); |
| 4029 | if (rc) { |
| 4030 | pr_err("Unable to set IADC1_BMS channel %x to %x: %d\n", |
| 4031 | IADC1_BMS_ADC_CH_SEL_CTL, |
| 4032 | EXTERNAL_RSENSE, rc); |
| 4033 | return rc; |
| 4034 | } |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 4035 | reset_cc(chip, CLEAR_CC | CLEAR_SHDW_CC); |
Xiaozhe Shi | 80ba88d | 2013-04-05 10:23:34 -0700 | [diff] [blame] | 4036 | chip->software_cc_uah = 0; |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 4037 | chip->software_shdw_cc_uah = 0; |
Xiaozhe Shi | dffbe69 | 2012-12-11 15:35:46 -0800 | [diff] [blame] | 4038 | } |
Xiaozhe Shi | 767fdb6 | 2013-01-10 15:09:08 -0800 | [diff] [blame] | 4039 | } else { |
| 4040 | pr_debug("Internal rsense selected\n"); |
| 4041 | if (iadc_channel_select == EXTERNAL_RSENSE) { |
| 4042 | pr_debug("External rsense detected; Changing rsense to internal\n"); |
Xiaozhe Shi | dffbe69 | 2012-12-11 15:35:46 -0800 | [diff] [blame] | 4043 | rc = qpnp_masked_write_iadc(chip, |
| 4044 | IADC1_BMS_ADC_CH_SEL_CTL, |
| 4045 | ADC_CH_SEL_MASK, |
| 4046 | INTERNAL_RSENSE); |
| 4047 | if (rc) { |
| 4048 | pr_err("Unable to set IADC1_BMS channel %x to %x: %d\n", |
| 4049 | IADC1_BMS_ADC_CH_SEL_CTL, |
| 4050 | INTERNAL_RSENSE, rc); |
| 4051 | return rc; |
| 4052 | } |
Xiaozhe Shi | f3da862 | 2013-06-10 14:50:56 -0700 | [diff] [blame] | 4053 | reset_cc(chip, CLEAR_CC | CLEAR_SHDW_CC); |
| 4054 | chip->software_shdw_cc_uah = 0; |
Xiaozhe Shi | dffbe69 | 2012-12-11 15:35:46 -0800 | [diff] [blame] | 4055 | } |
Xiaozhe Shi | 767fdb6 | 2013-01-10 15:09:08 -0800 | [diff] [blame] | 4056 | |
Siddartha Mohanadoss | 55d0bca | 2013-06-24 08:29:34 -0700 | [diff] [blame] | 4057 | rc = qpnp_iadc_get_rsense(chip->iadc_dev, &rds_rsense_nohm); |
Xiaozhe Shi | 767fdb6 | 2013-01-10 15:09:08 -0800 | [diff] [blame] | 4058 | if (rc) { |
| 4059 | pr_err("Unable to read RDS resistance value from IADC; rc = %d\n", |
| 4060 | rc); |
| 4061 | return rc; |
| 4062 | } |
Xiaozhe Shi | d0a7954 | 2012-11-06 10:00:38 -0800 | [diff] [blame] | 4063 | chip->r_sense_uohm = rds_rsense_nohm/1000; |
| 4064 | pr_debug("rds_rsense = %d nOhm, saved as %d uOhm\n", |
| 4065 | rds_rsense_nohm, chip->r_sense_uohm); |
Xiaozhe Shi | c40b397 | 2012-11-30 14:11:16 -0800 | [diff] [blame] | 4066 | } |
Abhijeet Dharmapurikar | 604461d | 2013-07-09 13:34:33 -0700 | [diff] [blame] | 4067 | /* prevent shorting of leads by IADC_BMS when external Rsense is used */ |
| 4068 | if (chip->use_external_rsense) { |
| 4069 | if (chip->iadc_bms_revision2 > CALIB_WRKARND_DIG_MAJOR_MAX) { |
| 4070 | rc = qpnp_masked_write_iadc(chip, |
| 4071 | IADC1_BMS_ADC_INT_RSNSN_CTL, |
| 4072 | ADC_INT_RSNSN_CTL_MASK, |
| 4073 | ADC_INT_RSNSN_CTL_VALUE_EXT_RENSE); |
| 4074 | if (rc) { |
| 4075 | pr_err("Unable to set batfet config %x to %x: %d\n", |
| 4076 | IADC1_BMS_ADC_INT_RSNSN_CTL, |
| 4077 | ADC_INT_RSNSN_CTL_VALUE_EXT_RENSE, rc); |
| 4078 | return rc; |
| 4079 | } |
| 4080 | } else { |
| 4081 | /* In older PMICS use FAST_AVG_EN register bit 7 */ |
| 4082 | rc = qpnp_masked_write_iadc(chip, |
| 4083 | IADC1_BMS_FAST_AVG_EN, |
| 4084 | FAST_AVG_EN_MASK, |
| 4085 | FAST_AVG_EN_VALUE_EXT_RSENSE); |
| 4086 | if (rc) { |
| 4087 | pr_err("Unable to set batfet config %x to %x: %d\n", |
| 4088 | IADC1_BMS_FAST_AVG_EN, |
| 4089 | FAST_AVG_EN_VALUE_EXT_RSENSE, rc); |
| 4090 | return rc; |
| 4091 | } |
| 4092 | } |
| 4093 | } |
| 4094 | |
Xiaozhe Shi | c40b397 | 2012-11-30 14:11:16 -0800 | [diff] [blame] | 4095 | return 0; |
| 4096 | } |
| 4097 | |
Xiaozhe Shi | 535494d | 2013-04-05 12:27:51 -0700 | [diff] [blame] | 4098 | static int refresh_die_temp_monitor(struct qpnp_bms_chip *chip) |
| 4099 | { |
| 4100 | struct qpnp_vadc_result result; |
| 4101 | int rc; |
| 4102 | |
Siddartha Mohanadoss | 3cb2b6b | 2013-06-21 12:07:05 -0700 | [diff] [blame] | 4103 | rc = qpnp_vadc_read(chip->vadc_dev, DIE_TEMP, &result); |
Xiaozhe Shi | 535494d | 2013-04-05 12:27:51 -0700 | [diff] [blame] | 4104 | |
| 4105 | pr_debug("low = %lld, high = %lld\n", |
| 4106 | result.physical - chip->temperature_margin, |
| 4107 | result.physical + chip->temperature_margin); |
| 4108 | chip->die_temp_monitor_params.high_temp = result.physical |
| 4109 | + chip->temperature_margin; |
| 4110 | chip->die_temp_monitor_params.low_temp = result.physical |
| 4111 | - chip->temperature_margin; |
| 4112 | chip->die_temp_monitor_params.state_request = |
| 4113 | ADC_TM_HIGH_LOW_THR_ENABLE; |
Siddartha Mohanadoss | 88a3fde | 2013-06-24 16:18:52 -0700 | [diff] [blame] | 4114 | return qpnp_adc_tm_channel_measure(chip->adc_tm_dev, |
| 4115 | &chip->die_temp_monitor_params); |
Xiaozhe Shi | 535494d | 2013-04-05 12:27:51 -0700 | [diff] [blame] | 4116 | } |
| 4117 | |
| 4118 | static void btm_notify_die_temp(enum qpnp_tm_state state, void *ctx) |
| 4119 | { |
| 4120 | struct qpnp_bms_chip *chip = ctx; |
| 4121 | struct qpnp_vadc_result result; |
| 4122 | int rc; |
| 4123 | |
Siddartha Mohanadoss | 3cb2b6b | 2013-06-21 12:07:05 -0700 | [diff] [blame] | 4124 | rc = qpnp_vadc_read(chip->vadc_dev, DIE_TEMP, &result); |
Xiaozhe Shi | 535494d | 2013-04-05 12:27:51 -0700 | [diff] [blame] | 4125 | |
| 4126 | if (state == ADC_TM_LOW_STATE) |
| 4127 | pr_debug("low state triggered\n"); |
| 4128 | else if (state == ADC_TM_HIGH_STATE) |
| 4129 | pr_debug("high state triggered\n"); |
| 4130 | pr_debug("die temp = %lld, raw = 0x%x\n", |
| 4131 | result.physical, result.adc_code); |
| 4132 | schedule_work(&chip->recalc_work); |
| 4133 | refresh_die_temp_monitor(chip); |
| 4134 | } |
| 4135 | |
| 4136 | static int setup_die_temp_monitoring(struct qpnp_bms_chip *chip) |
| 4137 | { |
Siddartha Mohanadoss | 88a3fde | 2013-06-24 16:18:52 -0700 | [diff] [blame] | 4138 | int rc; |
| 4139 | |
Xiaozhe Shi | 535494d | 2013-04-05 12:27:51 -0700 | [diff] [blame] | 4140 | chip->die_temp_monitor_params.channel = DIE_TEMP; |
| 4141 | chip->die_temp_monitor_params.btm_ctx = (void *)chip; |
| 4142 | chip->die_temp_monitor_params.timer_interval = ADC_MEAS1_INTERVAL_1S; |
| 4143 | chip->die_temp_monitor_params.threshold_notification = |
| 4144 | &btm_notify_die_temp; |
Siddartha Mohanadoss | 88a3fde | 2013-06-24 16:18:52 -0700 | [diff] [blame] | 4145 | rc = refresh_die_temp_monitor(chip); |
Xiaozhe Shi | 535494d | 2013-04-05 12:27:51 -0700 | [diff] [blame] | 4146 | if (rc) { |
| 4147 | pr_err("tm setup failed: %d\n", rc); |
| 4148 | return rc; |
| 4149 | } |
| 4150 | pr_debug("setup complete\n"); |
| 4151 | return 0; |
| 4152 | } |
| 4153 | |
Xiaozhe Shi | c40b397 | 2012-11-30 14:11:16 -0800 | [diff] [blame] | 4154 | static int __devinit qpnp_bms_probe(struct spmi_device *spmi) |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 4155 | { |
| 4156 | struct qpnp_bms_chip *chip; |
Xiaozhe Shi | 77ec38d | 2013-04-29 16:41:58 -0700 | [diff] [blame] | 4157 | bool warm_reset; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 4158 | int rc, vbatt; |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 4159 | |
Xiaozhe Shi | 81f66b5 | 2013-09-20 11:43:52 -0700 | [diff] [blame] | 4160 | chip = devm_kzalloc(&spmi->dev, sizeof(struct qpnp_bms_chip), |
| 4161 | GFP_KERNEL); |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 4162 | |
| 4163 | if (chip == NULL) { |
| 4164 | pr_err("kzalloc() failed.\n"); |
| 4165 | return -ENOMEM; |
| 4166 | } |
| 4167 | |
Siddartha Mohanadoss | 88a3fde | 2013-06-24 16:18:52 -0700 | [diff] [blame] | 4168 | rc = bms_get_adc(chip, spmi); |
| 4169 | if (rc < 0) |
Xiaozhe Shi | c40b397 | 2012-11-30 14:11:16 -0800 | [diff] [blame] | 4170 | goto error_read; |
Xiaozhe Shi | c40b397 | 2012-11-30 14:11:16 -0800 | [diff] [blame] | 4171 | |
Xiaozhe Shi | 3eaf0b6 | 2013-07-11 09:48:08 -0700 | [diff] [blame] | 4172 | mutex_init(&chip->bms_output_lock); |
| 4173 | mutex_init(&chip->last_ocv_uv_mutex); |
| 4174 | mutex_init(&chip->vbat_monitor_mutex); |
| 4175 | mutex_init(&chip->soc_invalidation_mutex); |
| 4176 | mutex_init(&chip->last_soc_mutex); |
Xiaozhe Shi | bda8499 | 2013-09-05 10:39:11 -0700 | [diff] [blame] | 4177 | mutex_init(&chip->status_lock); |
Xiaozhe Shi | 2737582 | 2013-08-22 11:40:15 -0700 | [diff] [blame] | 4178 | init_waitqueue_head(&chip->bms_wait_queue); |
Xiaozhe Shi | 3eaf0b6 | 2013-07-11 09:48:08 -0700 | [diff] [blame] | 4179 | |
Xiaozhe Shi | 77ec38d | 2013-04-29 16:41:58 -0700 | [diff] [blame] | 4180 | warm_reset = qpnp_pon_is_warm_reset(); |
| 4181 | rc = warm_reset; |
| 4182 | if (rc < 0) |
| 4183 | goto error_read; |
| 4184 | |
Xiaozhe Shi | c40b397 | 2012-11-30 14:11:16 -0800 | [diff] [blame] | 4185 | rc = register_spmi(chip, spmi); |
| 4186 | if (rc) { |
| 4187 | pr_err("error registering spmi resource %d\n", rc); |
| 4188 | goto error_resource; |
| 4189 | } |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 4190 | |
| 4191 | rc = qpnp_read_wrapper(chip, &chip->revision1, |
Abhijeet Dharmapurikar | 604461d | 2013-07-09 13:34:33 -0700 | [diff] [blame] | 4192 | chip->base + REVISION1, 1); |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 4193 | if (rc) { |
| 4194 | pr_err("error reading version register %d\n", rc); |
| 4195 | goto error_read; |
| 4196 | } |
| 4197 | |
| 4198 | rc = qpnp_read_wrapper(chip, &chip->revision2, |
Abhijeet Dharmapurikar | 604461d | 2013-07-09 13:34:33 -0700 | [diff] [blame] | 4199 | chip->base + REVISION2, 1); |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 4200 | if (rc) { |
| 4201 | pr_err("Error reading version register %d\n", rc); |
| 4202 | goto error_read; |
| 4203 | } |
Xiaozhe Shi | a045a56 | 2012-11-28 16:55:39 -0800 | [diff] [blame] | 4204 | pr_debug("BMS version: %hhu.%hhu\n", chip->revision2, chip->revision1); |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 4205 | |
Abhijeet Dharmapurikar | 604461d | 2013-07-09 13:34:33 -0700 | [diff] [blame] | 4206 | rc = qpnp_read_wrapper(chip, &chip->iadc_bms_revision2, |
| 4207 | chip->iadc_base + REVISION2, 1); |
| 4208 | if (rc) { |
| 4209 | pr_err("Error reading version register %d\n", rc); |
| 4210 | goto error_read; |
| 4211 | } |
| 4212 | |
| 4213 | rc = qpnp_read_wrapper(chip, &chip->iadc_bms_revision1, |
| 4214 | chip->iadc_base + REVISION1, 1); |
| 4215 | if (rc) { |
| 4216 | pr_err("Error reading version register %d\n", rc); |
| 4217 | goto error_read; |
| 4218 | } |
| 4219 | pr_debug("IADC_BMS version: %hhu.%hhu\n", |
| 4220 | chip->iadc_bms_revision2, chip->iadc_bms_revision1); |
| 4221 | |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 4222 | rc = bms_read_properties(chip); |
| 4223 | if (rc) { |
| 4224 | pr_err("Unable to read all bms properties, rc = %d\n", rc); |
| 4225 | goto error_read; |
| 4226 | } |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 4227 | |
Xiaozhe Shi | dffbe69 | 2012-12-11 15:35:46 -0800 | [diff] [blame] | 4228 | rc = read_iadc_channel_select(chip); |
| 4229 | if (rc) { |
| 4230 | pr_err("Unable to get iadc selected channel = %d\n", rc); |
| 4231 | goto error_read; |
| 4232 | } |
| 4233 | |
Xiaozhe Shi | bdf1474 | 2012-12-05 12:41:48 -0800 | [diff] [blame] | 4234 | if (chip->use_ocv_thresholds) { |
| 4235 | rc = set_ocv_voltage_thresholds(chip, |
| 4236 | chip->ocv_low_threshold_uv, |
| 4237 | chip->ocv_high_threshold_uv); |
| 4238 | if (rc) { |
| 4239 | pr_err("Could not set ocv voltage thresholds: %d\n", |
| 4240 | rc); |
| 4241 | goto error_read; |
| 4242 | } |
| 4243 | } |
| 4244 | |
Xiaozhe Shi | c40b397 | 2012-11-30 14:11:16 -0800 | [diff] [blame] | 4245 | rc = set_battery_data(chip); |
| 4246 | if (rc) { |
| 4247 | pr_err("Bad battery data %d\n", rc); |
| 4248 | goto error_read; |
| 4249 | } |
| 4250 | |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 4251 | bms_initialize_constants(chip); |
| 4252 | |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 4253 | wakeup_source_init(&chip->soc_wake_source.source, "qpnp_soc_wake"); |
Xiaozhe Shi | 4be8578 | 2013-02-22 17:33:40 -0800 | [diff] [blame] | 4254 | wake_lock_init(&chip->low_voltage_wake_lock, WAKE_LOCK_SUSPEND, |
| 4255 | "qpnp_low_voltage_lock"); |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 4256 | wake_lock_init(&chip->cv_wake_lock, WAKE_LOCK_SUSPEND, |
| 4257 | "qpnp_cv_lock"); |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 4258 | INIT_DELAYED_WORK(&chip->calculate_soc_delayed_work, |
| 4259 | calculate_soc_work); |
Xiaozhe Shi | 5cf7a67 | 2013-02-06 17:18:05 -0800 | [diff] [blame] | 4260 | INIT_WORK(&chip->recalc_work, recalculate_work); |
Abhijeet Dharmapurikar | 84b13dd | 2013-07-08 18:43:56 -0700 | [diff] [blame] | 4261 | INIT_WORK(&chip->batfet_open_work, batfet_open_work); |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 4262 | |
Xiaozhe Shi | f9f9924 | 2013-08-29 12:27:50 -0700 | [diff] [blame] | 4263 | dev_set_drvdata(&spmi->dev, chip); |
| 4264 | device_init_wakeup(&spmi->dev, 1); |
| 4265 | |
| 4266 | load_shutdown_data(chip); |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 4267 | |
Anirudh Ghayal | 9dd582d | 2013-06-07 17:48:58 +0530 | [diff] [blame] | 4268 | if (chip->enable_fcc_learning) { |
Anirudh Ghayal | e0c0293 | 2013-07-08 16:26:35 +0530 | [diff] [blame] | 4269 | if (chip->battery_removed) { |
| 4270 | rc = discard_backup_fcc_data(chip); |
| 4271 | if (rc) |
| 4272 | pr_err("Could not discard backed-up FCC data\n"); |
| 4273 | } else { |
| 4274 | rc = read_chgcycle_data_from_backup(chip); |
| 4275 | if (rc) |
| 4276 | pr_err("Unable to restore charge-cycle data\n"); |
| 4277 | |
| 4278 | rc = read_fcc_data_from_backup(chip); |
| 4279 | if (rc) |
| 4280 | pr_err("Unable to restore FCC-learning data\n"); |
| 4281 | else |
| 4282 | attempt_learning_new_fcc(chip); |
Anirudh Ghayal | 9dd582d | 2013-06-07 17:48:58 +0530 | [diff] [blame] | 4283 | } |
| 4284 | } |
Anirudh Ghayal | d71d9f8 | 2013-06-05 11:11:46 +0530 | [diff] [blame] | 4285 | |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 4286 | rc = setup_vbat_monitoring(chip); |
| 4287 | if (rc < 0) { |
| 4288 | pr_err("failed to set up voltage notifications: %d\n", rc); |
| 4289 | goto error_setup; |
Xiaozhe Shi | d5d2141 | 2013-02-06 17:14:41 -0800 | [diff] [blame] | 4290 | } |
| 4291 | |
Xiaozhe Shi | 535494d | 2013-04-05 12:27:51 -0700 | [diff] [blame] | 4292 | rc = setup_die_temp_monitoring(chip); |
| 4293 | if (rc < 0) { |
| 4294 | pr_err("failed to set up die temp notifications: %d\n", rc); |
| 4295 | goto error_setup; |
| 4296 | } |
| 4297 | |
Xu Kai | 870f8e8 | 2014-01-16 19:21:01 +0800 | [diff] [blame] | 4298 | rc = bms_request_irqs(chip); |
| 4299 | if (rc) { |
| 4300 | pr_err("error requesting bms irqs, rc = %d\n", rc); |
| 4301 | goto error_setup; |
| 4302 | } |
| 4303 | |
Xiaozhe Shi | e7fafe6 | 2013-06-05 15:25:16 -0700 | [diff] [blame] | 4304 | battery_insertion_check(chip); |
Abhijeet Dharmapurikar | 84b13dd | 2013-07-08 18:43:56 -0700 | [diff] [blame] | 4305 | batfet_status_check(chip); |
Xiaozhe Shi | e7fafe6 | 2013-06-05 15:25:16 -0700 | [diff] [blame] | 4306 | battery_status_check(chip); |
| 4307 | |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 4308 | calculate_soc_work(&(chip->calculate_soc_delayed_work.work)); |
| 4309 | |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 4310 | /* setup & register the battery power supply */ |
| 4311 | chip->bms_psy.name = "bms"; |
| 4312 | chip->bms_psy.type = POWER_SUPPLY_TYPE_BMS; |
| 4313 | chip->bms_psy.properties = msm_bms_power_props; |
| 4314 | chip->bms_psy.num_properties = ARRAY_SIZE(msm_bms_power_props); |
| 4315 | chip->bms_psy.get_property = qpnp_bms_power_get_property; |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 4316 | chip->bms_psy.external_power_changed = |
| 4317 | qpnp_bms_external_power_changed; |
| 4318 | chip->bms_psy.supplied_to = qpnp_bms_supplicants; |
| 4319 | chip->bms_psy.num_supplicants = ARRAY_SIZE(qpnp_bms_supplicants); |
| 4320 | |
| 4321 | rc = power_supply_register(chip->dev, &chip->bms_psy); |
| 4322 | |
| 4323 | if (rc < 0) { |
| 4324 | pr_err("power_supply_register bms failed rc = %d\n", rc); |
| 4325 | goto unregister_dc; |
| 4326 | } |
| 4327 | |
Abhijeet Dharmapurikar | 8e32249 | 2013-06-25 19:48:18 -0700 | [diff] [blame] | 4328 | chip->bms_psy_registered = true; |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 4329 | vbatt = 0; |
Siddartha Mohanadoss | 3cb2b6b | 2013-06-21 12:07:05 -0700 | [diff] [blame] | 4330 | rc = get_battery_voltage(chip, &vbatt); |
Xiaozhe Shi | 3645896 | 2013-02-06 16:19:57 -0800 | [diff] [blame] | 4331 | if (rc) { |
| 4332 | pr_err("error reading vbat_sns adc channel = %d, rc = %d\n", |
| 4333 | VBAT_SNS, rc); |
| 4334 | goto unregister_dc; |
| 4335 | } |
Xiaozhe Shi | cd7e530 | 2012-10-17 12:29:53 -0700 | [diff] [blame] | 4336 | |
Xiaozhe Shi | 77ec38d | 2013-04-29 16:41:58 -0700 | [diff] [blame] | 4337 | pr_info("probe success: soc =%d vbatt = %d ocv = %d r_sense_uohm = %u warm_reset = %d\n", |
| 4338 | get_prop_bms_capacity(chip), vbatt, chip->last_ocv_uv, |
| 4339 | chip->r_sense_uohm, warm_reset); |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 4340 | return 0; |
| 4341 | |
| 4342 | unregister_dc: |
Abhijeet Dharmapurikar | 8e32249 | 2013-06-25 19:48:18 -0700 | [diff] [blame] | 4343 | chip->bms_psy_registered = false; |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 4344 | power_supply_unregister(&chip->bms_psy); |
| 4345 | error_setup: |
| 4346 | dev_set_drvdata(&spmi->dev, NULL); |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 4347 | wakeup_source_trash(&chip->soc_wake_source.source); |
Xiaozhe Shi | 4be8578 | 2013-02-22 17:33:40 -0800 | [diff] [blame] | 4348 | wake_lock_destroy(&chip->low_voltage_wake_lock); |
Xiaozhe Shi | a6618a2 | 2013-03-27 10:26:29 -0700 | [diff] [blame] | 4349 | wake_lock_destroy(&chip->cv_wake_lock); |
Xiaozhe Shi | c40b397 | 2012-11-30 14:11:16 -0800 | [diff] [blame] | 4350 | error_resource: |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 4351 | error_read: |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 4352 | return rc; |
| 4353 | } |
| 4354 | |
Xiaozhe Shi | 81f66b5 | 2013-09-20 11:43:52 -0700 | [diff] [blame] | 4355 | static int qpnp_bms_remove(struct spmi_device *spmi) |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 4356 | { |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 4357 | dev_set_drvdata(&spmi->dev, NULL); |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 4358 | return 0; |
| 4359 | } |
| 4360 | |
Xiaozhe Shi | d6168d8 | 2013-04-18 16:06:17 -0700 | [diff] [blame] | 4361 | static int bms_suspend(struct device *dev) |
| 4362 | { |
| 4363 | struct qpnp_bms_chip *chip = dev_get_drvdata(dev); |
| 4364 | |
| 4365 | cancel_delayed_work_sync(&chip->calculate_soc_delayed_work); |
Xiaozhe Shi | 04da099 | 2013-04-26 16:32:14 -0700 | [diff] [blame] | 4366 | chip->was_charging_at_sleep = is_battery_charging(chip); |
Xiaozhe Shi | d6168d8 | 2013-04-18 16:06:17 -0700 | [diff] [blame] | 4367 | return 0; |
| 4368 | } |
| 4369 | |
Xiaozhe Shi | cdeee31 | 2012-12-18 15:10:18 -0800 | [diff] [blame] | 4370 | static int bms_resume(struct device *dev) |
| 4371 | { |
| 4372 | int rc; |
Xiaozhe Shi | d6168d8 | 2013-04-18 16:06:17 -0700 | [diff] [blame] | 4373 | int soc_calc_period; |
Xiaozhe Shi | d921f9f7 | 2013-05-23 18:55:15 -0700 | [diff] [blame] | 4374 | int time_until_next_recalc = 0; |
Xiaozhe Shi | cdeee31 | 2012-12-18 15:10:18 -0800 | [diff] [blame] | 4375 | unsigned long time_since_last_recalc; |
| 4376 | unsigned long tm_now_sec; |
| 4377 | struct qpnp_bms_chip *chip = dev_get_drvdata(dev); |
| 4378 | |
| 4379 | rc = get_current_time(&tm_now_sec); |
| 4380 | if (rc) { |
| 4381 | pr_err("Could not read current time: %d\n", rc); |
Xiaozhe Shi | d921f9f7 | 2013-05-23 18:55:15 -0700 | [diff] [blame] | 4382 | } else { |
Xiaozhe Shi | cb487b1 | 2013-10-14 17:42:07 -0700 | [diff] [blame] | 4383 | soc_calc_period = get_calculation_delay_ms(chip); |
Xiaozhe Shi | d921f9f7 | 2013-05-23 18:55:15 -0700 | [diff] [blame] | 4384 | time_since_last_recalc = tm_now_sec - chip->last_recalc_time; |
| 4385 | pr_debug("Time since last recalc: %lu\n", |
| 4386 | time_since_last_recalc); |
Xiaozhe Shi | d6168d8 | 2013-04-18 16:06:17 -0700 | [diff] [blame] | 4387 | time_until_next_recalc = max(0, soc_calc_period |
| 4388 | - (int)(time_since_last_recalc * 1000)); |
Xiaozhe Shi | cdeee31 | 2012-12-18 15:10:18 -0800 | [diff] [blame] | 4389 | } |
Xiaozhe Shi | d921f9f7 | 2013-05-23 18:55:15 -0700 | [diff] [blame] | 4390 | |
Xiaozhe Shi | 1ae8a95 | 2013-02-14 12:23:31 -0800 | [diff] [blame] | 4391 | if (time_until_next_recalc == 0) |
| 4392 | bms_stay_awake(&chip->soc_wake_source); |
Xiaozhe Shi | d921f9f7 | 2013-05-23 18:55:15 -0700 | [diff] [blame] | 4393 | schedule_delayed_work(&chip->calculate_soc_delayed_work, |
| 4394 | round_jiffies_relative(msecs_to_jiffies |
| 4395 | (time_until_next_recalc))); |
Xiaozhe Shi | cdeee31 | 2012-12-18 15:10:18 -0800 | [diff] [blame] | 4396 | return 0; |
| 4397 | } |
| 4398 | |
| 4399 | static const struct dev_pm_ops qpnp_bms_pm_ops = { |
| 4400 | .resume = bms_resume, |
Xiaozhe Shi | d6168d8 | 2013-04-18 16:06:17 -0700 | [diff] [blame] | 4401 | .suspend = bms_suspend, |
Xiaozhe Shi | cdeee31 | 2012-12-18 15:10:18 -0800 | [diff] [blame] | 4402 | }; |
| 4403 | |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 4404 | static struct spmi_driver qpnp_bms_driver = { |
| 4405 | .probe = qpnp_bms_probe, |
| 4406 | .remove = __devexit_p(qpnp_bms_remove), |
| 4407 | .driver = { |
| 4408 | .name = QPNP_BMS_DEV_NAME, |
| 4409 | .owner = THIS_MODULE, |
| 4410 | .of_match_table = qpnp_bms_match_table, |
Xiaozhe Shi | cdeee31 | 2012-12-18 15:10:18 -0800 | [diff] [blame] | 4411 | .pm = &qpnp_bms_pm_ops, |
Xiaozhe Shi | b19f703 | 2012-08-16 12:14:16 -0700 | [diff] [blame] | 4412 | }, |
| 4413 | }; |
| 4414 | |
| 4415 | static int __init qpnp_bms_init(void) |
| 4416 | { |
| 4417 | pr_info("QPNP BMS INIT\n"); |
| 4418 | return spmi_driver_register(&qpnp_bms_driver); |
| 4419 | } |
| 4420 | |
| 4421 | static void __exit qpnp_bms_exit(void) |
| 4422 | { |
| 4423 | pr_info("QPNP BMS EXIT\n"); |
| 4424 | return spmi_driver_unregister(&qpnp_bms_driver); |
| 4425 | } |
| 4426 | |
| 4427 | module_init(qpnp_bms_init); |
| 4428 | module_exit(qpnp_bms_exit); |
| 4429 | |
| 4430 | MODULE_DESCRIPTION("QPNP BMS Driver"); |
| 4431 | MODULE_LICENSE("GPL v2"); |
| 4432 | MODULE_ALIAS("platform:" QPNP_BMS_DEV_NAME); |