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gerrit-public.fairphone.software / fp2-dev / platform / bionic / 7c83a1ed81a15f3e75836c1ac7d500a952f02e10 / . / libc / arch-arm / generic / bionic / memcpy.S
blob: 6890a550245a3b56bdb156f3d160ec16095e7bf0 [file] [log] [blame]
Christopher Ferris7c83a1e2013-02-26 01:30:00 -0800[diff] [blame^]1/*
2 * Copyright (C) 2008 The Android Open Source Project
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in
12 * the documentation and/or other materials provided with the
13 * distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
18 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
19 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
22 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
25 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#include <machine/cpu-features.h>
30#include <machine/asm.h>
31
32 /*
33 * Optimized memcpy() for ARM.
34 *
35 * note that memcpy() always returns the destination pointer,
36 * so we have to preserve R0.
37 */
38
39ENTRY(memcpy)
40 /* The stack must always be 64-bits aligned to be compliant with the
41 * ARM ABI. Since we have to save R0, we might as well save R4
42 * which we can use for better pipelining of the reads below
43 */
44 .save {r0, r4, lr}
45 stmfd sp!, {r0, r4, lr}
46 /* Making room for r5-r11 which will be spilled later */
47 .pad #28
48 sub sp, sp, #28
49
50 // preload the destination because we'll align it to a cache line
51 // with small writes. Also start the source "pump".
52 PLD (r0, #0)
53 PLD (r1, #0)
54 PLD (r1, #32)
55
56 /* it simplifies things to take care of len<4 early */
57 cmp r2, #4
58 blo copy_last_3_and_return
59
60 /* compute the offset to align the source
61 * offset = (4-(src&3))&3 = -src & 3
62 */
63 rsb r3, r1, #0
64 ands r3, r3, #3
65 beq src_aligned
66
67 /* align source to 32 bits. We need to insert 2 instructions between
68 * a ldr[b|h] and str[b|h] because byte and half-word instructions
69 * stall 2 cycles.
70 */
71 movs r12, r3, lsl #31
72 sub r2, r2, r3 /* we know that r3 <= r2 because r2 >= 4 */
73 ldrmib r3, [r1], #1
74 ldrcsb r4, [r1], #1
75 ldrcsb r12,[r1], #1
76 strmib r3, [r0], #1
77 strcsb r4, [r0], #1
78 strcsb r12,[r0], #1
79
80src_aligned:
81
82 /* see if src and dst are aligned together (congruent) */
83 eor r12, r0, r1
84 tst r12, #3
85 bne non_congruent
86
87 /* Use post-incriment mode for stm to spill r5-r11 to reserved stack
88 * frame. Don't update sp.
89 */
90 stmea sp, {r5-r11}
91
92 /* align the destination to a cache-line */
93 rsb r3, r0, #0
94 ands r3, r3, #0x1C
95 beq congruent_aligned32
96 cmp r3, r2
97 andhi r3, r2, #0x1C
98
99 /* conditionally copies 0 to 7 words (length in r3) */
100 movs r12, r3, lsl #28
101 ldmcsia r1!, {r4, r5, r6, r7} /* 16 bytes */
102 ldmmiia r1!, {r8, r9} /* 8 bytes */
103 stmcsia r0!, {r4, r5, r6, r7}
104 stmmiia r0!, {r8, r9}
105 tst r3, #0x4
106 ldrne r10,[r1], #4 /* 4 bytes */
107 strne r10,[r0], #4
108 sub r2, r2, r3
109
110congruent_aligned32:
111 /*
112 * here source is aligned to 32 bytes.
113 */
114
115cached_aligned32:
116 subs r2, r2, #32
117 blo less_than_32_left
118
119 /*
120 * We preload a cache-line up to 64 bytes ahead. On the 926, this will
121 * stall only until the requested world is fetched, but the linefill
122 * continues in the the background.
123 * While the linefill is going, we write our previous cache-line
124 * into the write-buffer (which should have some free space).
125 * When the linefill is done, the writebuffer will
126 * start dumping its content into memory
127 *
128 * While all this is going, we then load a full cache line into
129 * 8 registers, this cache line should be in the cache by now
130 * (or partly in the cache).
131 *
132 * This code should work well regardless of the source/dest alignment.
133 *
134 */
135
136 // Align the preload register to a cache-line because the cpu does
137 // "critical word first" (the first word requested is loaded first).
138 bic r12, r1, #0x1F
139 add r12, r12, #64
140
1411: ldmia r1!, { r4-r11 }
142 PLD (r12, #64)
143 subs r2, r2, #32
144
145 // NOTE: if r12 is more than 64 ahead of r1, the following ldrhi
146 // for ARM9 preload will not be safely guarded by the preceding subs.
147 // When it is safely guarded the only possibility to have SIGSEGV here
148 // is because the caller overstates the length.
149 ldrhi r3, [r12], #32 /* cheap ARM9 preload */
150 stmia r0!, { r4-r11 }
151 bhs 1b
152
153 add r2, r2, #32
154
155
156
157
158less_than_32_left:
159 /*
160 * less than 32 bytes left at this point (length in r2)
161 */
162
163 /* skip all this if there is nothing to do, which should
164 * be a common case (if not executed the code below takes
165 * about 16 cycles)
166 */
167 tst r2, #0x1F
168 beq 1f
169
170 /* conditionnaly copies 0 to 31 bytes */
171 movs r12, r2, lsl #28
172 ldmcsia r1!, {r4, r5, r6, r7} /* 16 bytes */
173 ldmmiia r1!, {r8, r9} /* 8 bytes */
174 stmcsia r0!, {r4, r5, r6, r7}
175 stmmiia r0!, {r8, r9}
176 movs r12, r2, lsl #30
177 ldrcs r3, [r1], #4 /* 4 bytes */
178 ldrmih r4, [r1], #2 /* 2 bytes */
179 strcs r3, [r0], #4
180 strmih r4, [r0], #2
181 tst r2, #0x1
182 ldrneb r3, [r1] /* last byte */
183 strneb r3, [r0]
184
185 /* we're done! restore everything and return */
1861: ldmfd sp!, {r5-r11}
187 ldmfd sp!, {r0, r4, lr}
188 bx lr
189
190 /********************************************************************/
191
192non_congruent:
193 /*
194 * here source is aligned to 4 bytes
195 * but destination is not.
196 *
197 * in the code below r2 is the number of bytes read
198 * (the number of bytes written is always smaller, because we have
199 * partial words in the shift queue)
200 */
201 cmp r2, #4
202 blo copy_last_3_and_return
203
204 /* Use post-incriment mode for stm to spill r5-r11 to reserved stack
205 * frame. Don't update sp.
206 */
207 stmea sp, {r5-r11}
208
209 /* compute shifts needed to align src to dest */
210 rsb r5, r0, #0
211 and r5, r5, #3 /* r5 = # bytes in partial words */
212 mov r12, r5, lsl #3 /* r12 = right */
213 rsb lr, r12, #32 /* lr = left */
214
215 /* read the first word */
216 ldr r3, [r1], #4
217 sub r2, r2, #4
218
219 /* write a partial word (0 to 3 bytes), such that destination
220 * becomes aligned to 32 bits (r5 = nb of words to copy for alignment)
221 */
222 movs r5, r5, lsl #31
223 strmib r3, [r0], #1
224 movmi r3, r3, lsr #8
225 strcsb r3, [r0], #1
226 movcs r3, r3, lsr #8
227 strcsb r3, [r0], #1
228 movcs r3, r3, lsr #8
229
230 cmp r2, #4
231 blo partial_word_tail
232
233 /* Align destination to 32 bytes (cache line boundary) */
2341: tst r0, #0x1c
235 beq 2f
236 ldr r5, [r1], #4
237 sub r2, r2, #4
238 orr r4, r3, r5, lsl lr
239 mov r3, r5, lsr r12
240 str r4, [r0], #4
241 cmp r2, #4
242 bhs 1b
243 blo partial_word_tail
244
245 /* copy 32 bytes at a time */
2462: subs r2, r2, #32
247 blo less_than_thirtytwo
248
249 /* Use immediate mode for the shifts, because there is an extra cycle
250 * for register shifts, which could account for up to 50% of
251 * performance hit.
252 */
253
254 cmp r12, #24
255 beq loop24
256 cmp r12, #8
257 beq loop8
258
259loop16:
260 ldr r12, [r1], #4
2611: mov r4, r12
262 ldmia r1!, { r5,r6,r7, r8,r9,r10,r11}
263 PLD (r1, #64)
264 subs r2, r2, #32
265 ldrhs r12, [r1], #4
266 orr r3, r3, r4, lsl #16
267 mov r4, r4, lsr #16
268 orr r4, r4, r5, lsl #16
269 mov r5, r5, lsr #16
270 orr r5, r5, r6, lsl #16
271 mov r6, r6, lsr #16
272 orr r6, r6, r7, lsl #16
273 mov r7, r7, lsr #16
274 orr r7, r7, r8, lsl #16
275 mov r8, r8, lsr #16
276 orr r8, r8, r9, lsl #16
277 mov r9, r9, lsr #16
278 orr r9, r9, r10, lsl #16
279 mov r10, r10, lsr #16
280 orr r10, r10, r11, lsl #16
281 stmia r0!, {r3,r4,r5,r6, r7,r8,r9,r10}
282 mov r3, r11, lsr #16
283 bhs 1b
284 b less_than_thirtytwo
285
286loop8:
287 ldr r12, [r1], #4
2881: mov r4, r12
289 ldmia r1!, { r5,r6,r7, r8,r9,r10,r11}
290 PLD (r1, #64)
291 subs r2, r2, #32
292 ldrhs r12, [r1], #4
293 orr r3, r3, r4, lsl #24
294 mov r4, r4, lsr #8
295 orr r4, r4, r5, lsl #24
296 mov r5, r5, lsr #8
297 orr r5, r5, r6, lsl #24
298 mov r6, r6, lsr #8
299 orr r6, r6, r7, lsl #24
300 mov r7, r7, lsr #8
301 orr r7, r7, r8, lsl #24
302 mov r8, r8, lsr #8
303 orr r8, r8, r9, lsl #24
304 mov r9, r9, lsr #8
305 orr r9, r9, r10, lsl #24
306 mov r10, r10, lsr #8
307 orr r10, r10, r11, lsl #24
308 stmia r0!, {r3,r4,r5,r6, r7,r8,r9,r10}
309 mov r3, r11, lsr #8
310 bhs 1b
311 b less_than_thirtytwo
312
313loop24:
314 ldr r12, [r1], #4
3151: mov r4, r12
316 ldmia r1!, { r5,r6,r7, r8,r9,r10,r11}
317 PLD (r1, #64)
318 subs r2, r2, #32
319 ldrhs r12, [r1], #4
320 orr r3, r3, r4, lsl #8
321 mov r4, r4, lsr #24
322 orr r4, r4, r5, lsl #8
323 mov r5, r5, lsr #24
324 orr r5, r5, r6, lsl #8
325 mov r6, r6, lsr #24
326 orr r6, r6, r7, lsl #8
327 mov r7, r7, lsr #24
328 orr r7, r7, r8, lsl #8
329 mov r8, r8, lsr #24
330 orr r8, r8, r9, lsl #8
331 mov r9, r9, lsr #24
332 orr r9, r9, r10, lsl #8
333 mov r10, r10, lsr #24
334 orr r10, r10, r11, lsl #8
335 stmia r0!, {r3,r4,r5,r6, r7,r8,r9,r10}
336 mov r3, r11, lsr #24
337 bhs 1b
338
339
340less_than_thirtytwo:
341 /* copy the last 0 to 31 bytes of the source */
342 rsb r12, lr, #32 /* we corrupted r12, recompute it */
343 add r2, r2, #32
344 cmp r2, #4
345 blo partial_word_tail
346
3471: ldr r5, [r1], #4
348 sub r2, r2, #4
349 orr r4, r3, r5, lsl lr
350 mov r3, r5, lsr r12
351 str r4, [r0], #4
352 cmp r2, #4
353 bhs 1b
354
355partial_word_tail:
356 /* we have a partial word in the input buffer */
357 movs r5, lr, lsl #(31-3)
358 strmib r3, [r0], #1
359 movmi r3, r3, lsr #8
360 strcsb r3, [r0], #1
361 movcs r3, r3, lsr #8
362 strcsb r3, [r0], #1
363
364 /* Refill spilled registers from the stack. Don't update sp. */
365 ldmfd sp, {r5-r11}
366
367copy_last_3_and_return:
368 movs r2, r2, lsl #31 /* copy remaining 0, 1, 2 or 3 bytes */
369 ldrmib r2, [r1], #1
370 ldrcsb r3, [r1], #1
371 ldrcsb r12,[r1]
372 strmib r2, [r0], #1
373 strcsb r3, [r0], #1
374 strcsb r12,[r0]
375
376 /* we're done! restore sp and spilled registers and return */
377 add sp, sp, #28
378 ldmfd sp!, {r0, r4, lr}
379 bx lr
380END(memcpy)