commit e3c01dac83e6eea7f82fe81ed89cfbdd9791dbc9
author Carl Shapiro <cshapiro@google.com> Thu May 20 22:54:18 2010 -0700
committer Carl Shapiro <cshapiro@google.com> Fri May 21 16:17:32 2010 -0700
tree 5ac4bca0a836db33243aeb22ba5d49aadcba2d58
parent 2b908f67d0150c11057497f0dc551e3369105184

Remove unused labels, variables, and functions.  Enable warnings.

Change-Id: Icbe24eaf1ad499f28b68b6a5f05368271a0a7e86

vm/compiler/codegen/arm/Assemble.c

diff --git a/vm/compiler/codegen/arm/Assemble.c b/vm/compiler/codegen/arm/Assemble.c
index 05d311b..3c00ece 100644
--- a/vm/compiler/codegen/arm/Assemble.c
+++ b/vm/compiler/codegen/arm/Assemble.c
@@ -1420,6 +1420,7 @@
  * Attempt to enqueue a work order to patch an inline cache for a predicted
  * chaining cell for virtual/interface calls.
  */
+#if !defined(WITH_SELF_VERIFICATION)
 static bool inlineCachePatchEnqueue(PredictedChainingCell *cellAddr,
                                     PredictedChainingCell *newContent)
 {
@@ -1474,6 +1475,7 @@
     dvmUnlockMutex(&gDvmJit.compilerICPatchLock);
     return result;
 }
+#endif
 
 /*
  * This method is called from the invoke templates for virtual and interface
@@ -1641,8 +1643,6 @@
     int cellSize;
     u4* pChainCells;
     u4* pStart;
-    u4 thumb1;
-    u4 thumb2;
     u4 newInst;
     int i,j;
     PredictedChainingCell *predChainCell;
@@ -2246,7 +2246,6 @@
         //LOGD("*** THUMB2 - Addr: 0x%x Insn: 0x%x", lr, insn);
 
         int opcode12 = (insn >> 20) & 0xFFF;
-        int opcode6 = (insn >> 6) & 0x3F;
         int opcode4 = (insn >> 8) & 0xF;
         int imm2 = (insn >> 4) & 0x3;
         int imm8 = insn & 0xFF;