| Ben Cheng | ba4fc8b | 2009-06-01 13:00:29 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2009 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #ifndef _DALVIK_VM_COMPILER_IR |
| 18 | #define _DALVIK_VM_COMPILER_IR |
| 19 | |
| Ben Cheng | 4238ec2 | 2009-08-24 16:32:22 -0700 | [diff] [blame] | 20 | #include "codegen/Optimizer.h" |
| 21 | |
| Bill Buzbee | 1465db5 | 2009-09-23 17:17:35 -0700 | [diff] [blame] | 22 | typedef enum RegisterClass { |
| 23 | kCoreReg, |
| 24 | kFPReg, |
| 25 | kAnyReg, |
| 26 | } RegisterClass; |
| 27 | |
| 28 | typedef enum RegLocationType { |
| 29 | kLocDalvikFrame = 0, |
| 30 | kLocPhysReg, |
| 31 | kLocRetval, // Return region in interpState |
| 32 | kLocSpill, |
| 33 | } RegLocationType; |
| 34 | |
| 35 | typedef struct RegLocation { |
| 36 | RegLocationType location:2; |
| 37 | unsigned wide:1; |
| 38 | unsigned fp:1; // Hint for float/double |
| 39 | u1 lowReg:6; // First physical register |
| 40 | u1 highReg:6; // 2nd physical register (if wide) |
| 41 | s2 sRegLow; // SSA name for low Dalvik word |
| 42 | } RegLocation; |
| 43 | |
| 44 | #define INVALID_SREG (-1) |
| 45 | #define INVALID_REG (-1) |
| 46 | |
| Ben Cheng | ba4fc8b | 2009-06-01 13:00:29 -0700 | [diff] [blame] | 47 | typedef enum BBType { |
| 48 | /* For coding convenience reasons chaining cell types should appear first */ |
| Bill Buzbee | 1465db5 | 2009-09-23 17:17:35 -0700 | [diff] [blame] | 49 | kChainingCellNormal = 0, |
| 50 | kChainingCellHot, |
| 51 | kChainingCellInvokeSingleton, |
| 52 | kChainingCellInvokePredicted, |
| 53 | kChainingCellBackwardBranch, |
| Ben Cheng | cec26f6 | 2010-01-15 15:29:33 -0800 | [diff] [blame] | 54 | kChainingCellGap, |
| 55 | /* Don't insert new fields between Gap and Last */ |
| 56 | kChainingCellLast = kChainingCellGap + 1, |
| Bill Buzbee | 1465db5 | 2009-09-23 17:17:35 -0700 | [diff] [blame] | 57 | kEntryBlock, |
| 58 | kDalvikByteCode, |
| 59 | kExitBlock, |
| 60 | kPCReconstruction, |
| 61 | kExceptionHandling, |
| Ben Cheng | ba4fc8b | 2009-06-01 13:00:29 -0700 | [diff] [blame] | 62 | } BBType; |
| 63 | |
| Bill Buzbee | 46cd5b6 | 2009-06-05 15:36:06 -0700 | [diff] [blame] | 64 | typedef struct ChainCellCounts { |
| 65 | union { |
| Ben Cheng | cec26f6 | 2010-01-15 15:29:33 -0800 | [diff] [blame] | 66 | u1 count[kChainingCellLast]; /* include one more space for the gap # */ |
| Bill Buzbee | 46cd5b6 | 2009-06-05 15:36:06 -0700 | [diff] [blame] | 67 | u4 dummyForAlignment; |
| 68 | } u; |
| 69 | } ChainCellCounts; |
| 70 | |
| Ben Cheng | ba4fc8b | 2009-06-01 13:00:29 -0700 | [diff] [blame] | 71 | typedef struct LIR { |
| 72 | int offset; |
| 73 | struct LIR *next; |
| 74 | struct LIR *prev; |
| 75 | struct LIR *target; |
| 76 | } LIR; |
| 77 | |
| Ben Cheng | 4238ec2 | 2009-08-24 16:32:22 -0700 | [diff] [blame] | 78 | enum ExtendedMIROpcode { |
| Bill Buzbee | 1465db5 | 2009-09-23 17:17:35 -0700 | [diff] [blame] | 79 | kMirOpFirst = 256, |
| 80 | kMirOpPhi = kMirOpFirst, |
| 81 | kMirOpNullNRangeUpCheck, |
| 82 | kMirOpNullNRangeDownCheck, |
| 83 | kMirOpLowerBound, |
| 84 | kMirOpPunt, |
| 85 | kMirOpLast, |
| Ben Cheng | 4238ec2 | 2009-08-24 16:32:22 -0700 | [diff] [blame] | 86 | }; |
| 87 | |
| 88 | struct SSARepresentation; |
| 89 | |
| 90 | typedef enum { |
| 91 | kMIRIgnoreNullCheck = 0, |
| 92 | kMIRNullCheckOnly, |
| 93 | kMIRIgnoreRangeCheck, |
| 94 | kMIRRangeCheckOnly, |
| 95 | } MIROptimizationFlagPositons; |
| 96 | |
| 97 | #define MIR_IGNORE_NULL_CHECK (1 << kMIRIgnoreNullCheck) |
| 98 | #define MIR_NULL_CHECK_ONLY (1 << kMIRNullCheckOnly) |
| 99 | #define MIR_IGNORE_RANGE_CHECK (1 << kMIRIgnoreRangeCheck) |
| 100 | #define MIR_RANGE_CHECK_ONLY (1 << kMIRRangeCheckOnly) |
| 101 | |
| Ben Cheng | ba4fc8b | 2009-06-01 13:00:29 -0700 | [diff] [blame] | 102 | typedef struct MIR { |
| 103 | DecodedInstruction dalvikInsn; |
| 104 | unsigned int width; |
| 105 | unsigned int offset; |
| 106 | struct MIR *prev; |
| 107 | struct MIR *next; |
| Ben Cheng | 4238ec2 | 2009-08-24 16:32:22 -0700 | [diff] [blame] | 108 | struct SSARepresentation *ssaRep; |
| 109 | int OptimizationFlags; |
| Bill Buzbee | 1465db5 | 2009-09-23 17:17:35 -0700 | [diff] [blame] | 110 | int seqNum; |
| Ben Cheng | ba4fc8b | 2009-06-01 13:00:29 -0700 | [diff] [blame] | 111 | } MIR; |
| 112 | |
| Ben Cheng | 4238ec2 | 2009-08-24 16:32:22 -0700 | [diff] [blame] | 113 | struct BasicBlockDataFlow; |
| 114 | |
| Ben Cheng | ba4fc8b | 2009-06-01 13:00:29 -0700 | [diff] [blame] | 115 | typedef struct BasicBlock { |
| 116 | int id; |
| 117 | int visited; |
| 118 | unsigned int startOffset; |
| 119 | const Method *containingMethod; // For blocks from the callee |
| 120 | BBType blockType; |
| Ben Cheng | 1efc9c5 | 2009-06-08 18:25:27 -0700 | [diff] [blame] | 121 | bool needFallThroughBranch; // For blocks ended due to length limit |
| Ben Cheng | ba4fc8b | 2009-06-01 13:00:29 -0700 | [diff] [blame] | 122 | MIR *firstMIRInsn; |
| 123 | MIR *lastMIRInsn; |
| 124 | struct BasicBlock *fallThrough; |
| 125 | struct BasicBlock *taken; |
| 126 | struct BasicBlock *next; // Serial link for book keeping purposes |
| Ben Cheng | 4238ec2 | 2009-08-24 16:32:22 -0700 | [diff] [blame] | 127 | struct BasicBlockDataFlow *dataFlowInfo; |
| Ben Cheng | ba4fc8b | 2009-06-01 13:00:29 -0700 | [diff] [blame] | 128 | } BasicBlock; |
| 129 | |
| Ben Cheng | 4238ec2 | 2009-08-24 16:32:22 -0700 | [diff] [blame] | 130 | struct LoopAnalysis; |
| Bill Buzbee | 1465db5 | 2009-09-23 17:17:35 -0700 | [diff] [blame] | 131 | struct RegisterPool; |
| Ben Cheng | 4238ec2 | 2009-08-24 16:32:22 -0700 | [diff] [blame] | 132 | |
| Ben Cheng | ba4fc8b | 2009-06-01 13:00:29 -0700 | [diff] [blame] | 133 | typedef struct CompilationUnit { |
| Ben Cheng | 1efc9c5 | 2009-06-08 18:25:27 -0700 | [diff] [blame] | 134 | int numInsts; |
| Ben Cheng | ba4fc8b | 2009-06-01 13:00:29 -0700 | [diff] [blame] | 135 | int numBlocks; |
| 136 | BasicBlock **blockList; |
| 137 | const Method *method; |
| 138 | const JitTraceDescription *traceDesc; |
| 139 | LIR *firstLIRInsn; |
| 140 | LIR *lastLIRInsn; |
| 141 | LIR *wordList; |
| Bill Buzbee | 6e963e1 | 2009-06-17 16:56:19 -0700 | [diff] [blame] | 142 | LIR *chainCellOffsetLIR; |
| Ben Cheng | ba4fc8b | 2009-06-01 13:00:29 -0700 | [diff] [blame] | 143 | GrowableList pcReconstructionList; |
| Ben Cheng | 1efc9c5 | 2009-06-08 18:25:27 -0700 | [diff] [blame] | 144 | int headerSize; // bytes before the first code ptr |
| 145 | int dataOffset; // starting offset of literal pool |
| 146 | int totalSize; // header + code size |
| Ben Cheng | ba4fc8b | 2009-06-01 13:00:29 -0700 | [diff] [blame] | 147 | unsigned char *codeBuffer; |
| 148 | void *baseAddr; |
| 149 | bool printMe; |
| 150 | bool allSingleStep; |
| Ben Cheng | 1efc9c5 | 2009-06-08 18:25:27 -0700 | [diff] [blame] | 151 | bool halveInstCount; |
| Bill Buzbee | 6e963e1 | 2009-06-17 16:56:19 -0700 | [diff] [blame] | 152 | bool executionCount; // Add code to count trace executions |
| Ben Cheng | 4238ec2 | 2009-08-24 16:32:22 -0700 | [diff] [blame] | 153 | bool hasLoop; |
| jeffhao | 9e45c0b | 2010-02-03 10:24:05 -0800 | [diff] [blame] | 154 | bool heapMemOp; // Mark mem ops for self verification |
| Ben Cheng | cec26f6 | 2010-01-15 15:29:33 -0800 | [diff] [blame] | 155 | int numChainingCells[kChainingCellGap]; |
| 156 | LIR *firstChainingLIR[kChainingCellGap]; |
| 157 | LIR *chainingCellBottom; |
| Bill Buzbee | 1465db5 | 2009-09-23 17:17:35 -0700 | [diff] [blame] | 158 | struct RegisterPool *regPool; |
| Ben Cheng | e9695e5 | 2009-06-16 16:11:47 -0700 | [diff] [blame] | 159 | int optRound; // round number to tell an LIR's age |
| Bill Buzbee | fc519dc | 2010-03-06 23:30:57 -0800 | [diff] [blame] | 160 | jmp_buf *bailPtr; |
| Bill Buzbee | 716f120 | 2009-07-23 13:22:09 -0700 | [diff] [blame] | 161 | JitInstructionSetType instructionSet; |
| Ben Cheng | 4238ec2 | 2009-08-24 16:32:22 -0700 | [diff] [blame] | 162 | /* Number of total regs used in the whole cUnit after SSA transformation */ |
| 163 | int numSSARegs; |
| 164 | /* Map SSA reg i to the Dalvik[15..0]/Sub[31..16] pair. */ |
| 165 | GrowableList *ssaToDalvikMap; |
| 166 | |
| 167 | /* The following are new data structures to support SSA representations */ |
| 168 | /* Map original Dalvik reg i to the SSA[15..0]/Sub[31..16] pair */ |
| 169 | int *dalvikToSSAMap; // length == method->registersSize |
| 170 | BitVector *isConstantV; // length == numSSAReg |
| 171 | int *constantValues; // length == numSSAReg |
| 172 | |
| 173 | /* Data structure for loop analysis and optimizations */ |
| 174 | struct LoopAnalysis *loopAnalysis; |
| Bill Buzbee | 1465db5 | 2009-09-23 17:17:35 -0700 | [diff] [blame] | 175 | |
| 176 | /* Map SSA names to location */ |
| 177 | RegLocation *regLocation; |
| 178 | int sequenceNumber; |
| Ben Cheng | 6c10a97 | 2009-10-29 14:39:18 -0700 | [diff] [blame] | 179 | |
| 180 | /* |
| 181 | * Set to the Dalvik PC of the switch instruction if it has more than |
| 182 | * MAX_CHAINED_SWITCH_CASES cases. |
| 183 | */ |
| 184 | const u2 *switchOverflowPad; |
| Ben Cheng | ba4fc8b | 2009-06-01 13:00:29 -0700 | [diff] [blame] | 185 | } CompilationUnit; |
| 186 | |
| Ben Cheng | 11d8f14 | 2010-03-24 15:24:19 -0700 | [diff] [blame^] | 187 | #if defined(WITH_SELF_VERIFICATION) |
| 188 | #define HEAP_ACCESS_SHADOW(_state) cUnit->heapMemOp = _state |
| 189 | #else |
| 190 | #define HEAP_ACCESS_SHADOW(_state) |
| 191 | #endif |
| 192 | |
| Ben Cheng | ba4fc8b | 2009-06-01 13:00:29 -0700 | [diff] [blame] | 193 | BasicBlock *dvmCompilerNewBB(BBType blockType); |
| 194 | |
| 195 | void dvmCompilerAppendMIR(BasicBlock *bb, MIR *mir); |
| 196 | |
| Ben Cheng | 4238ec2 | 2009-08-24 16:32:22 -0700 | [diff] [blame] | 197 | void dvmCompilerPrependMIR(BasicBlock *bb, MIR *mir); |
| 198 | |
| Ben Cheng | ba4fc8b | 2009-06-01 13:00:29 -0700 | [diff] [blame] | 199 | void dvmCompilerAppendLIR(CompilationUnit *cUnit, LIR *lir); |
| 200 | |
| Ben Cheng | e9695e5 | 2009-06-16 16:11:47 -0700 | [diff] [blame] | 201 | void dvmCompilerInsertLIRBefore(LIR *currentLIR, LIR *newLIR); |
| 202 | |
| Ben Cheng | dcf3e5d | 2009-09-11 13:42:05 -0700 | [diff] [blame] | 203 | void dvmCompilerInsertLIRAfter(LIR *currentLIR, LIR *newLIR); |
| 204 | |
| Bill Buzbee | fc519dc | 2010-03-06 23:30:57 -0800 | [diff] [blame] | 205 | void dvmCompilerAbort(CompilationUnit *cUnit); |
| 206 | |
| Ben Cheng | ba4fc8b | 2009-06-01 13:00:29 -0700 | [diff] [blame] | 207 | /* Debug Utilities */ |
| 208 | void dvmCompilerDumpCompilationUnit(CompilationUnit *cUnit); |
| 209 | |
| 210 | #endif /* _DALVIK_VM_COMPILER_IR */ |