blob: 7726e9749e687e2315e797e814db79156e9bba10 [file] [log] [blame]
buzbee7520ee72010-09-17 16:01:49 -07001/*
2 * This file was generated automatically by gen-template.py for 'ia32'.
3 *
4 * --> DO NOT EDIT <--
5 */
6
7/* File: ia32/header.S */
8/*
Ben Cheng8c9ac9a2010-10-22 10:15:03 -07009 * Copyright (C) 2010 The Android Open Source Project
buzbee7520ee72010-09-17 16:01:49 -070010 *
11 * Licensed under the Apache License, Version 2.0 (the "License");
12 * you may not use this file except in compliance with the License.
13 * You may obtain a copy of the License at
14 *
15 * http://www.apache.org/licenses/LICENSE-2.0
16 *
17 * Unless required by applicable law or agreed to in writing, software
18 * distributed under the License is distributed on an "AS IS" BASIS,
19 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
20 * See the License for the specific language governing permissions and
21 * limitations under the License.
22 */
23
24#if defined(WITH_JIT)
25
26/*
27 * This is a #include, not a %include, because we want the C pre-processor
28 * to expand the macros into assembler assignment statements.
29 */
30#include "../../../mterp/common/asm-constants.h"
31
32/* File: ia32/platform.S */
33/*
34 * ===========================================================================
35 * CPU-version-specific defines and utility
36 * ===========================================================================
37 */
38
39
40
41
42 .global dvmCompilerTemplateStart
43 .type dvmCompilerTemplateStart, %function
44 .text
45
46dvmCompilerTemplateStart:
47
48/* ------------------------------ */
49 .balign 4
50 .global dvmCompiler_TEMPLATE_INTERPRET
51dvmCompiler_TEMPLATE_INTERPRET:
52/* File: ia32/TEMPLATE_INTERPRET.S */
53 /*
54 * TODO: figure out how best to do this on x86, as we don't have
55 * an lr equivalent and probably don't want to push.
56 *
57 * This handler transfers control to the interpeter without performing
58 * any lookups. It may be called either as part of a normal chaining
59 * operation, or from the transition code in header.S. We distinquish
60 * the two cases by looking at the link register. If called from a
61 * translation chain, it will point to the chaining Dalvik PC -3.
62 * On entry:
63 * lr - if NULL:
64 * r1 - the Dalvik PC to begin interpretation.
65 * else
66 * [lr, #3] contains Dalvik PC to begin interpretation
67 * rGLUE - pointer to interpState
68 * rFP - Dalvik frame pointer
69 *
70 *cmp lr, #0
71 *ldrne r1,[lr, #3]
72 *ldr r2, .LinterpPunt
73 *mov r0, r1 @ set Dalvik PC
74 *bx r2
75 *@ doesn't return
76 */
77
78.LinterpPunt:
79 .long dvmJitToInterpPunt
80
81 .size dvmCompilerTemplateStart, .-dvmCompilerTemplateStart
82/* File: ia32/footer.S */
83/*
84 * ===========================================================================
85 * Common subroutines and data
86 * ===========================================================================
87 */
88
89 .text
90 .align 4
91/*
92 * FIXME - need a cacheflush for x86
93 */
94 .global cacheflush
95cacheflush:
96 movl $0xdeadf0f0, %eax
97 call *%eax
98
99
100 .global dmvCompilerTemplateEnd
101dmvCompilerTemplateEnd:
102
103#endif /* WITH_JIT */
104