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gerrit-public.fairphone.software / fp2-dev / platform / dalvik / 9bc3df373ae6f4f7e6e97d554884d4e0dbad5494 / . / vm / compiler / codegen / arm / ArmLIR.h
blob: ed02bae260b8373e25e454b9292fe77b612ac5fe [file] [log] [blame]
Bill Buzbee89efc3d2009-07-28 11:22:22 -0700[diff] [blame]1/*
2 * Copyright (C) 2009 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#include "Dalvik.h"
18#include "compiler/CompilerInternals.h"
19
20#ifndef _DALVIK_VM_COMPILER_CODEGEN_ARM_ARMLIR_H
21#define _DALVIK_VM_COMPILER_CODEGEN_ARM_ARMLIR_H
22
23/*
Bill Buzbee9bc3df32009-07-30 10:52:29 -0700[diff] [blame^]24 * r0, r1, r2, r3 are always scratch
25 * r4 (rPC) is scratch for Jit, but most be restored when resuming interp
26 * r5 (rFP) is reserved [holds Dalvik frame pointer]
27 * r6 (rGLUE) is reserved [holds current &interpState]
28 * r7 (rINST) is scratch for Jit
29 * r8 (rIBASE) is scratch for Jit, but must be restored when resuming interp
30 * r9 is always scratch
31 * r10 is always scratch
32 * r11 (fp) used by gcc unless -fomit-frame-pointer set [available for jit?]
33 * r12 is always scratch
34 * r13 (sp) is reserved
35 * r14 (lr) is scratch for Jit
36 * r15 (pc) is reserved
37 *
38 * For Thumb code use:
39 * r0, r1, r2, r3 to hold operands/results via scoreboard
40 * r4, r7 for temps
41 *
42 * For Thumb2 code use:
43 * r0, r1, r2, r3, r8, r9, r10, r11 for operands/results via scoreboard
44 * r4, r7, r14 for temps
45 *
46 * When transitioning from code cache to interp:
47 * restore rIBASE
48 * restore rPC
49 * restore r11 (fp)?
50 *
51 * Double precision values are stored in consecutive single precision registers
52 * such that dr0 -> (sr0,sr1), dr1 -> (sr2,sr3) ... dr16 -> (sr30,sr31)
Bill Buzbee89efc3d2009-07-28 11:22:22 -0700[diff] [blame]53 */
Bill Buzbee9bc3df32009-07-30 10:52:29 -0700[diff] [blame^]54
55/* Offset to distingish FP regs */
56#define FP_REG_OFFSET 32
57/* Is reg fp? */
58#define IS_FP_REG(x) (x & FP_REG_OFFSET)
59/* Mask to strip off fp flags */
60#define FP_REG_MASK (FP_REG_OFFSET-1)
61/* Mask to convert high reg to low for Thumb */
62#define THUMB_REG_MASK 0x7
63
Bill Buzbee89efc3d2009-07-28 11:22:22 -0700[diff] [blame]64typedef enum NativeRegisterPool {
65 r0 = 0,
66 r1 = 1,
67 r2 = 2,
68 r3 = 3,
69 r4PC = 4,
70 rFP = 5,
71 rGLUE = 6,
72 r7 = 7,
73 r8 = 8,
74 r9 = 9,
75 r10 = 10,
76 r11 = 11,
77 r12 = 12,
78 r13 = 13,
79 rlr = 14,
Bill Buzbee9bc3df32009-07-30 10:52:29 -0700[diff] [blame^]80 rpc = 15,
81 fr0 = 0 + FP_REG_OFFSET,
82 fr1 = 1 + FP_REG_OFFSET,
83 fr2 = 2 + FP_REG_OFFSET,
84 fr3 = 3 + FP_REG_OFFSET,
85 fr4 = 4 + FP_REG_OFFSET,
86 fr5 = 5 + FP_REG_OFFSET,
87 fr6 = 6 + FP_REG_OFFSET,
88 fr7 = 7 + FP_REG_OFFSET,
89 fr8 = 8 + FP_REG_OFFSET,
90 fr9 = 9 + FP_REG_OFFSET,
91 fr10 = 10 + FP_REG_OFFSET,
92 fr11 = 11 + FP_REG_OFFSET,
93 fr12 = 12 + FP_REG_OFFSET,
94 fr13 = 13 + FP_REG_OFFSET,
95 fr14 = 14 + FP_REG_OFFSET,
96 fr15 = 15 + FP_REG_OFFSET,
97 fr16 = 16 + FP_REG_OFFSET,
98 fr17 = 17 + FP_REG_OFFSET,
99 fr18 = 18 + FP_REG_OFFSET,
100 fr19 = 19 + FP_REG_OFFSET,
101 fr20 = 20 + FP_REG_OFFSET,
102 fr21 = 21 + FP_REG_OFFSET,
103 fr22 = 22 + FP_REG_OFFSET,
104 fr23 = 23 + FP_REG_OFFSET,
105 fr24 = 24 + FP_REG_OFFSET,
106 fr25 = 25 + FP_REG_OFFSET,
107 fr26 = 26 + FP_REG_OFFSET,
108 fr27 = 27 + FP_REG_OFFSET,
109 fr28 = 28 + FP_REG_OFFSET,
110 fr29 = 29 + FP_REG_OFFSET,
111 fr30 = 30 + FP_REG_OFFSET,
112 fr31 = 31 + FP_REG_OFFSET,
Bill Buzbee89efc3d2009-07-28 11:22:22 -0700[diff] [blame]113} NativeRegisterPool;
114
Bill Buzbee89efc3d2009-07-28 11:22:22 -0700[diff] [blame]115/* Thumb condition encodings */
116typedef enum ArmConditionCode {
117 ARM_COND_EQ = 0x0, /* 0000 */
118 ARM_COND_NE = 0x1, /* 0001 */
119 ARM_COND_LT = 0xb, /* 1011 */
120 ARM_COND_GE = 0xa, /* 1010 */
121 ARM_COND_GT = 0xc, /* 1100 */
122 ARM_COND_LE = 0xd, /* 1101 */
123 ARM_COND_CS = 0x2, /* 0010 */
124 ARM_COND_MI = 0x4, /* 0100 */
125} ArmConditionCode;
126
127#define isPseudoOpCode(opCode) ((int)(opCode) < 0)
128
129/*
130 * The following enum defines the list of supported Thumb instructions by the
131 * assembler. Their corresponding snippet positions will be defined in
132 * Assemble.c.
133 */
134typedef enum ArmOpCode {
135 ARM_PSEUDO_TARGET_LABEL = -11,
136 ARM_PSEUDO_CHAINING_CELL_HOT = -10,
137 ARM_PSEUDO_CHAINING_CELL_INVOKE_PREDICTED = -9,
138 ARM_PSEUDO_CHAINING_CELL_INVOKE_SINGLETON = -8,
139 ARM_PSEUDO_CHAINING_CELL_NORMAL = -7,
140 ARM_PSEUDO_DALVIK_BYTECODE_BOUNDARY = -6,
141 ARM_PSEUDO_ALIGN4 = -5,
142 ARM_PSEUDO_PC_RECONSTRUCTION_CELL = -4,
143 ARM_PSEUDO_PC_RECONSTRUCTION_BLOCK_LABEL = -3,
144 ARM_PSEUDO_EH_BLOCK_LABEL = -2,
145 ARM_PSEUDO_NORMAL_BLOCK_LABEL = -1,
146 /************************************************************************/
147 ARM_16BIT_DATA, /* DATA [0] rd[15..0] */
148 THUMB_ADC, /* adc [0100000101] rm[5..3] rd[2..0] */
149 THUMB_ADD_RRI3, /* add(1) [0001110] imm_3[8..6] rn[5..3] rd[2..0]*/
150 THUMB_ADD_RI8, /* add(2) [00110] rd[10..8] imm_8[7..0] */
151 THUMB_ADD_RRR, /* add(3) [0001100] rm[8..6] rn[5..3] rd[2..0] */
152 THUMB_ADD_RR_LH, /* add(4) [01000100] H12[01] rm[5..3] rd[2..0] */
153 THUMB_ADD_RR_HL, /* add(4) [01001000] H12[10] rm[5..3] rd[2..0] */
154 THUMB_ADD_RR_HH, /* add(4) [01001100] H12[11] rm[5..3] rd[2..0] */
155 THUMB_ADD_PC_REL, /* add(5) [10100] rd[10..8] imm_8[7..0] */
156 THUMB_ADD_SP_REL, /* add(6) [10101] rd[10..8] imm_8[7..0] */
157 THUMB_ADD_SPI7, /* add(7) [101100000] imm_7[6..0] */
158 THUMB_AND_RR, /* and [0100000000] rm[5..3] rd[2..0] */
159 THUMB_ASR, /* asr(1) [00010] imm_5[10..6] rm[5..3] rd[2..0] */
160 THUMB_ASRV, /* asr(2) [0100000100] rs[5..3] rd[2..0] */
161 THUMB_B_COND, /* b(1) [1101] cond[11..8] offset_8[7..0] */
162 THUMB_B_UNCOND, /* b(2) [11100] offset_11[10..0] */
163 THUMB_BIC, /* bic [0100001110] rm[5..3] rd[2..0] */
164 THUMB_BKPT, /* bkpt [10111110] imm_8[7..0] */
165 THUMB_BLX_1, /* blx(1) [111] H[10] offset_11[10..0] */
166 THUMB_BLX_2, /* blx(1) [111] H[01] offset_11[10..0] */
167 THUMB_BL_1, /* blx(1) [111] H[10] offset_11[10..0] */
168 THUMB_BL_2, /* blx(1) [111] H[11] offset_11[10..0] */
169 THUMB_BLX_R, /* blx(2) [010001111] H2[6..6] rm[5..3] SBZ[000] */
170 THUMB_BX, /* bx [010001110] H2[6..6] rm[5..3] SBZ[000] */
171 THUMB_CMN, /* cmn [0100001011] rm[5..3] rd[2..0] */
172 THUMB_CMP_RI8, /* cmp(1) [00101] rn[10..8] imm_8[7..0] */
173 THUMB_CMP_RR, /* cmp(2) [0100001010] rm[5..3] rd[2..0] */
174 THUMB_CMP_LH, /* cmp(3) [01000101] H12[01] rm[5..3] rd[2..0] */
175 THUMB_CMP_HL, /* cmp(3) [01000110] H12[10] rm[5..3] rd[2..0] */
176 THUMB_CMP_HH, /* cmp(3) [01000111] H12[11] rm[5..3] rd[2..0] */
177 THUMB_EOR, /* eor [0100000001] rm[5..3] rd[2..0] */
178 THUMB_LDMIA, /* ldmia [11001] rn[10..8] reglist [7..0] */
179 THUMB_LDR_RRI5, /* ldr(1) [01101] imm_5[10..6] rn[5..3] rd[2..0] */
180 THUMB_LDR_RRR, /* ldr(2) [0101100] rm[8..6] rn[5..3] rd[2..0] */
181 THUMB_LDR_PC_REL, /* ldr(3) [01001] rd[10..8] imm_8[7..0] */
182 THUMB_LDR_SP_REL, /* ldr(4) [10011] rd[10..8] imm_8[7..0] */
183 THUMB_LDRB_RRI5, /* ldrb(1) [01111] imm_5[10..6] rn[5..3] rd[2..0] */
184 THUMB_LDRB_RRR, /* ldrb(2) [0101110] rm[8..6] rn[5..3] rd[2..0] */
185 THUMB_LDRH_RRI5, /* ldrh(1) [10001] imm_5[10..6] rn[5..3] rd[2..0] */
186 THUMB_LDRH_RRR, /* ldrh(2) [0101101] rm[8..6] rn[5..3] rd[2..0] */
187 THUMB_LDRSB_RRR, /* ldrsb [0101011] rm[8..6] rn[5..3] rd[2..0] */
188 THUMB_LDRSH_RRR, /* ldrsh [0101111] rm[8..6] rn[5..3] rd[2..0] */
189 THUMB_LSL, /* lsl(1) [00000] imm_5[10..6] rm[5..3] rd[2..0] */
190 THUMB_LSLV, /* lsl(2) [0100000010] rs[5..3] rd[2..0] */
191 THUMB_LSR, /* lsr(1) [00001] imm_5[10..6] rm[5..3] rd[2..0] */
192 THUMB_LSRV, /* lsr(2) [0100000011] rs[5..3] rd[2..0] */
193 THUMB_MOV_IMM, /* mov(1) [00100] rd[10..8] imm_8[7..0] */
194 THUMB_MOV_RR, /* mov(2) [0001110000] rn[5..3] rd[2..0] */
195 THUMB_MOV_RR_H2H, /* mov(3) [01000111] H12[11] rm[5..3] rd[2..0] */
196 THUMB_MOV_RR_H2L, /* mov(3) [01000110] H12[01] rm[5..3] rd[2..0] */
197 THUMB_MOV_RR_L2H, /* mov(3) [01000101] H12[10] rm[5..3] rd[2..0] */
198 THUMB_MUL, /* mul [0100001101] rm[5..3] rd[2..0] */
199 THUMB_MVN, /* mvn [0100001111] rm[5..3] rd[2..0] */
200 THUMB_NEG, /* neg [0100001001] rm[5..3] rd[2..0] */
201 THUMB_ORR, /* orr [0100001100] rm[5..3] rd[2..0] */
202 THUMB_POP, /* pop [1011110] r[8..8] rl[7..0] */
203 THUMB_PUSH, /* push [1011010] r[8..8] rl[7..0] */
204 THUMB_ROR, /* ror [0100000111] rs[5..3] rd[2..0] */
205 THUMB_SBC, /* sbc [0100000110] rm[5..3] rd[2..0] */
206 THUMB_STMIA, /* stmia [11000] rn[10..8] reglist [7.. 0] */
207 THUMB_STR_RRI5, /* str(1) [01100] imm_5[10..6] rn[5..3] rd[2..0] */
208 THUMB_STR_RRR, /* str(2) [0101000] rm[8..6] rn[5..3] rd[2..0] */
209 THUMB_STR_SP_REL, /* str(3) [10010] rd[10..8] imm_8[7..0] */
210 THUMB_STRB_RRI5, /* strb(1) [01110] imm_5[10..6] rn[5..3] rd[2..0] */
211 THUMB_STRB_RRR, /* strb(2) [0101010] rm[8..6] rn[5..3] rd[2..0] */
212 THUMB_STRH_RRI5, /* strh(1) [10000] imm_5[10..6] rn[5..3] rd[2..0] */
213 THUMB_STRH_RRR, /* strh(2) [0101001] rm[8..6] rn[5..3] rd[2..0] */
214 THUMB_SUB_RRI3, /* sub(1) [0001111] imm_3[8..6] rn[5..3] rd[2..0]*/
215 THUMB_SUB_RI8, /* sub(2) [00111] rd[10..8] imm_8[7..0] */
216 THUMB_SUB_RRR, /* sub(3) [0001101] rm[8..6] rn[5..3] rd[2..0] */
217 THUMB_SUB_SPI7, /* sub(4) [101100001] imm_7[6..0] */
218 THUMB_SWI, /* swi [11011111] imm_8[7..0] */
219 THUMB_TST, /* tst [0100001000] rm[5..3] rn[2..0] */
Bill Buzbee9bc3df32009-07-30 10:52:29 -0700[diff] [blame^]220// FIXME: Enhance assembly encoding. Only low fp regs supported here
221 THUMB2_VLDRS, /* vldr low sx [111011011001] rn[19..16] rd[15-12]
222 [1010] imm_8[7..0] */
223 THUMB2_VLDRD, /* vldr low dx [111011011001] rn[19..16] rd[15-12]
224 [1011] imm_8[7..0] */
225 THUMB2_VMULS, /* vmul vd, vn, vm [111011100010] rn[19..16]
226 rd[15-12] [10100000] rm[3..0] */
227 THUMB2_VMULD, /* vmul vd, vn, vm [111011100010] rn[19..16]
228 rd[15-12] [10110000] rm[3..0] */
229 THUMB2_VSTRS, /* vstr low sx [111011011000] rn[19..16] rd[15-12]
230 [1010] imm_8[7..0] */
231 THUMB2_VSTRD, /* vstr low dx [111011011000] rn[19..16] rd[15-12]
232 [1011] imm_8[7..0] */
233 THUMB2_VSUBS, /* vsub vd, vn, vm [111011100011] rn[19..16]
234 rd[15-12] [10100040] rm[3..0] */
235 THUMB2_VSUBD, /* vsub vd, vn, vm [111011100011] rn[19..16]
236 rd[15-12] [10110040] rm[3..0] */
237 THUMB2_VADDS, /* vadd vd, vn, vm [111011100011] rn[19..16]
238 rd[15-12] [10100000] rm[3..0] */
239 THUMB2_VADDD, /* vadd vd, vn, vm [111011100011] rn[19..16]
240 rd[15-12] [10110000] rm[3..0] */
241 THUMB2_VDIVS, /* vdiv vd, vn, vm [111011101000] rn[19..16]
242 rd[15-12] [10100000] rm[3..0] */
243 THUMB2_VDIVD, /* vdiv vd, vn, vm [111011101000] rn[19..16]
244 rd[15-12] [10110000] rm[3..0] */
245 THUMB2_VCVTIF, /* vcvt.F32 vd, vm [1110111010111000] vd[15..12]
246 [10101100] vm[3..0] */
247 THUMB2_VCVTID, /* vcvt.F64 vd, vm [1110111010111000] vd[15..12]
248 [10111100] vm[3..0] */
249 THUMB2_VCVTFI, /* vcvt.S32.F32 vd, vm [1110111010111101] vd[15..12]
250 [10101100] vm[3..0] */
251 THUMB2_VCVTDI, /* vcvt.S32.F32 vd, vm [1110111010111101] vd[15..12]
252 [10111100] vm[3..0] */
253 THUMB2_VCVTFD, /* vcvt.F64.F32 vd, vm [1110111010110111] vd[15..12]
254 [10101100] vm[3..0] */
255 THUMB2_VCVTDF, /* vcvt.F32.F64 vd, vm [1110111010110111] vd[15..12]
256 [10111100] vm[3..0] */
Bill Buzbee89efc3d2009-07-28 11:22:22 -0700[diff] [blame]257 ARM_LAST,
258} ArmOpCode;
259
260/* Bit flags describing the behavior of each native opcode */
261typedef enum ArmOpFeatureFlags {
262 IS_BRANCH = 1 << 1,
263 CLOBBER_DEST = 1 << 2,
264 CLOBBER_SRC1 = 1 << 3,
265 NO_OPERAND = 1 << 4,
266 IS_UNARY_OP = 1 << 5,
267 IS_BINARY_OP = 1 << 6,
268 IS_TERTIARY_OP = 1 << 7,
269} ArmOpFeatureFlags;
270
Bill Buzbee9bc3df32009-07-30 10:52:29 -0700[diff] [blame^]271/* Instruction assembly fieldLoc kind */
272typedef enum ArmEncodingKind {
273 UNUSED,
274 BITBLT, /* Bit string using end/start */
275 DFP, /* Double FP reg */
276 SFP, /* Single FP reg */
277 IMMSHIFT8, /* Shifted 8-bit immed field using [26,14..12,7..0] */
278 IMM12, /* Zero-extended 12-bit immediate using [26,14..12,7..0] */
279} ArmEncodingKind;
280
Bill Buzbee89efc3d2009-07-28 11:22:22 -0700[diff] [blame]281/* Struct used to define the snippet positions for each Thumb opcode */
282typedef struct ArmEncodingMap {
Bill Buzbee9bc3df32009-07-30 10:52:29 -0700[diff] [blame^]283 u4 skeleton;
Bill Buzbee89efc3d2009-07-28 11:22:22 -0700[diff] [blame]284 struct {
Bill Buzbee9bc3df32009-07-30 10:52:29 -0700[diff] [blame^]285 ArmEncodingKind kind;
286 int end; /* end for BITBLT, 1-bit slice end for FP regs */
287 int start; /* start for BITBLT, 4-bit slice end for FP regs */
Bill Buzbee89efc3d2009-07-28 11:22:22 -0700[diff] [blame]288 } fieldLoc[3];
289 ArmOpCode opCode;
290 int flags;
291 char *name;
292 char* fmt;
293 int size;
294} ArmEncodingMap;
295
296extern ArmEncodingMap EncodingMap[ARM_LAST];
297
298/*
299 * Each instance of this struct holds a pseudo or real LIR instruction:
300 * - pesudo ones (eg labels and marks) and will be discarded by the assembler.
301 * - real ones will e assembled into Thumb instructions.
302 */
303typedef struct ArmLIR {
304 LIR generic;
305 ArmOpCode opCode;
306 int operands[3]; // [0..2] = [dest, src1, src2]
307 bool isNop; // LIR is optimized away
308 int age; // default is 0, set lazily by the optimizer
309 int size; // 16-bit unit size (1 for thumb, 1 or 2 for thumb2)
310} ArmLIR;
311
312/* Chain cell for predicted method invocation */
313typedef struct PredictedChainingCell {
314 u4 branch; /* Branch to chained destination */
315 const ClassObject *clazz; /* key #1 for prediction */
316 const Method *method; /* key #2 to lookup native PC from dalvik PC */
317 u4 counter; /* counter to patch the chaining cell */
318} PredictedChainingCell;
319
320/* Init values when a predicted chain is initially assembled */
321#define PREDICTED_CHAIN_BX_PAIR_INIT 0
322#define PREDICTED_CHAIN_CLAZZ_INIT 0
323#define PREDICTED_CHAIN_METHOD_INIT 0
324#define PREDICTED_CHAIN_COUNTER_INIT 0
325
326/* Used when the callee is not compiled yet */
327#define PREDICTED_CHAIN_COUNTER_DELAY 16
328
329/* Rechain after this many mis-predictions have happened */
330#define PREDICTED_CHAIN_COUNTER_RECHAIN 1024
331
332/* Used if the resolved callee is a native method */
333#define PREDICTED_CHAIN_COUNTER_AVOID 0x7fffffff
334
335/* Utility macros to traverse the LIR/ArmLIR list */
336#define NEXT_LIR(lir) ((ArmLIR *) lir->generic.next)
337#define PREV_LIR(lir) ((ArmLIR *) lir->generic.prev)
338
339#define NEXT_LIR_LVALUE(lir) (lir)->generic.next
340#define PREV_LIR_LVALUE(lir) (lir)->generic.prev
341
342#define CHAIN_CELL_OFFSET_TAG 0xcdab
343
344#endif /* _DALVIK_VM_COMPILER_CODEGEN_ARM_ARMLIR_H */