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gerrit-public.fairphone.software / fp2-dev / platform / dalvik / d45ba37dd5aeb6b37dd3091a4d6fa0a87f75fdf9 / . / vm / compiler / codegen / armv5te / Armv5teLIR.h
blob: 3341e496b159f66a74824da2279c7c3f84c548d6 [file] [log] [blame]
Ben Chengba4fc8b2009-06-01 13:00:29 -0700[diff] [blame]1/*
2 * Copyright (C) 2009 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#include "Dalvik.h"
18#include "compiler/CompilerInternals.h"
19
20#ifndef _DALVIK_VM_COMPILER_CODEGEN_ARMV5TE_H
21#define _DALVIK_VM_COMPILER_CODEGEN_ARMV5TE_H
22
23/*
24 * r0, r1, r2, r3, and r7 are always scratch
25 * r4PC is scratch if used solely in the compiled land. Otherwise it holds the
26 * Dalvik PC.
27 * rFP holds the current frame pointer
28 * rGLUE holds &InterpState
29 */
30typedef enum NativeRegisterPool {
31 r0 = 0,
32 r1 = 1,
33 r2 = 2,
34 r3 = 3,
35 r4PC = 4,
36 rFP = 5,
37 rGLUE = 6,
38 r7 = 7,
39} NativeRegisterPool;
40
41/* Thumb condition encodings */
42typedef enum Armv5teConditionCode {
43 ARM_COND_EQ = 0x0, /* 0000 */
44 ARM_COND_NE = 0x1, /* 0001 */
45 ARM_COND_LT = 0xb, /* 1011 */
46 ARM_COND_GE = 0xa, /* 1010 */
47 ARM_COND_GT = 0xc, /* 1100 */
48 ARM_COND_LE = 0xd, /* 1101 */
49 ARM_COND_CS = 0x2, /* 0010 */
50 ARM_COND_MI = 0x4, /* 0100 */
51} Armv5teConditionCode;
52
53#define isPseudoOpCode(opCode) ((int)(opCode) < 0)
54
55/*
56 * The following enum defines the list of supported Thumb instructions by the
57 * assembler. Their corresponding snippet positions will be defined in
58 * Assemble.c.
59 */
60typedef enum Armv5teOpCode {
61 ARMV5TE_PSEUDO_TARGET_LABEL = -10,
Ben Cheng1efc9c52009-06-08 18:25:27 -0700[diff] [blame]62 ARMV5TE_PSEUDO_CHAINING_CELL_HOT = -9,
Ben Chengba4fc8b2009-06-01 13:00:29 -0700[diff] [blame]63 ARMV5TE_PSEUDO_CHAINING_CELL_INVOKE = -8,
Ben Cheng1efc9c52009-06-08 18:25:27 -0700[diff] [blame]64 ARMV5TE_PSEUDO_CHAINING_CELL_NORMAL = -7,
Ben Chengba4fc8b2009-06-01 13:00:29 -0700[diff] [blame]65 ARMV5TE_PSEUDO_DALVIK_BYTECODE_BOUNDARY = -6,
66 ARMV5TE_PSEUDO_ALIGN4 = -5,
67 ARMV5TE_PSEUDO_PC_RECONSTRUCTION_CELL = -4,
68 ARMV5TE_PSEUDO_PC_RECONSTRUCTION_BLOCK_LABEL = -3,
69 ARMV5TE_PSEUDO_EH_BLOCK_LABEL = -2,
70 ARMV5TE_PSEUDO_NORMAL_BLOCK_LABEL = -1,
71 /************************************************************************/
72 ARMV5TE_16BIT_DATA, /* DATA [0] rd[15..0] */
73 ARMV5TE_ADC, /* adc [0100000101] rm[5..3] rd[2..0] */
74 ARMV5TE_ADD_RRI3, /* add(1) [0001110] imm_3[8..6] rn[5..3] rd[2..0]*/
75 ARMV5TE_ADD_RI8, /* add(2) [00110] rd[10..8] imm_8[7..0] */
76 ARMV5TE_ADD_RRR, /* add(3) [0001100] rm[8..6] rn[5..3] rd[2..0] */
77 ARMV5TE_ADD_RR_LH, /* add(4) [01000100] H12[01] rm[5..3] rd[2..0] */
78 ARMV5TE_ADD_RR_HL, /* add(4) [01001000] H12[10] rm[5..3] rd[2..0] */
79 ARMV5TE_ADD_RR_HH, /* add(4) [01001100] H12[11] rm[5..3] rd[2..0] */
80 ARMV5TE_ADD_PC_REL, /* add(5) [10100] rd[10..8] imm_8[7..0] */
81 ARMV5TE_ADD_SP_REL, /* add(6) [10101] rd[10..8] imm_8[7..0] */
82 ARMV5TE_ADD_SPI7, /* add(7) [101100000] imm_7[6..0] */
83 ARMV5TE_AND_RR, /* and [0100000000] rm[5..3] rd[2..0] */
84 ARMV5TE_ASR, /* asr(1) [00010] imm_5[10..6] rm[5..3] rd[2..0] */
85 ARMV5TE_ASRV, /* asr(2) [0100000100] rs[5..3] rd[2..0] */
86 ARMV5TE_B_COND, /* b(1) [1101] cond[11..8] offset_8[7..0] */
87 ARMV5TE_B_UNCOND, /* b(2) [11100] offset_11[10..0] */
88 ARMV5TE_BIC, /* bic [0100001110] rm[5..3] rd[2..0] */
89 ARMV5TE_BKPT, /* bkpt [10111110] imm_8[7..0] */
90 ARMV5TE_BLX_1, /* blx(1) [111] H[10] offset_11[10..0] */
91 ARMV5TE_BLX_2, /* blx(1) [111] H[01] offset_11[10..0] */
92 ARMV5TE_BL_1, /* blx(1) [111] H[10] offset_11[10..0] */
93 ARMV5TE_BL_2, /* blx(1) [111] H[11] offset_11[10..0] */
94 ARMV5TE_BLX_R, /* blx(2) [010001111] H2[6..6] rm[5..3] SBZ[000] */
95 ARMV5TE_BX, /* bx [010001110] H2[6..6] rm[5..3] SBZ[000] */
96 ARMV5TE_CMN, /* cmn [0100001011] rm[5..3] rd[2..0] */
97 ARMV5TE_CMP_RI8, /* cmp(1) [00101] rn[10..8] imm_8[7..0] */
98 ARMV5TE_CMP_RR, /* cmp(2) [0100001010] rm[5..3] rd[2..0] */
99 ARMV5TE_CMP_LH, /* cmp(3) [01000101] H12[01] rm[5..3] rd[2..0] */
100 ARMV5TE_CMP_HL, /* cmp(3) [01000110] H12[10] rm[5..3] rd[2..0] */
101 ARMV5TE_CMP_HH, /* cmp(3) [01000111] H12[11] rm[5..3] rd[2..0] */
102 ARMV5TE_EOR, /* eor [0100000001] rm[5..3] rd[2..0] */
103 ARMV5TE_LDMIA, /* ldmia [11001] rn[10..8] reglist [7..0] */
104 ARMV5TE_LDR_RRI5, /* ldr(1) [01101] imm_5[10..6] rn[5..3] rd[2..0] */
105 ARMV5TE_LDR_RRR, /* ldr(2) [0101100] rm[8..6] rn[5..3] rd[2..0] */
106 ARMV5TE_LDR_PC_REL, /* ldr(3) [01001] rd[10..8] imm_8[7..0] */
107 ARMV5TE_LDR_SP_REL, /* ldr(4) [10011] rd[10..8] imm_8[7..0] */
108 ARMV5TE_LDRB_RRI5, /* ldrb(1) [01111] imm_5[10..6] rn[5..3] rd[2..0] */
109 ARMV5TE_LDRB_RRR, /* ldrb(2) [0101110] rm[8..6] rn[5..3] rd[2..0] */
110 ARMV5TE_LDRH_RRI5, /* ldrh(1) [10001] imm_5[10..6] rn[5..3] rd[2..0] */
111 ARMV5TE_LDRH_RRR, /* ldrh(2) [0101101] rm[8..6] rn[5..3] rd[2..0] */
112 ARMV5TE_LDRSB_RRR, /* ldrsb [0101011] rm[8..6] rn[5..3] rd[2..0] */
113 ARMV5TE_LDRSH_RRR, /* ldrsh [0101111] rm[8..6] rn[5..3] rd[2..0] */
114 ARMV5TE_LSL, /* lsl(1) [00000] imm_5[10..6] rm[5..3] rd[2..0] */
115 ARMV5TE_LSLV, /* lsl(2) [0100000010] rs[5..3] rd[2..0] */
116 ARMV5TE_LSR, /* lsr(1) [00001] imm_5[10..6] rm[5..3] rd[2..0] */
117 ARMV5TE_LSRV, /* lsr(2) [0100000011] rs[5..3] rd[2..0] */
118 ARMV5TE_MOV_IMM, /* mov(1) [00100] rd[10..8] imm_8[7..0] */
119 ARMV5TE_MOV_RR, /* mov(2) [0001110000] rn[5..3] rd[2..0] */
120 ARMV5TE_MOV_RR_HL, /* mov(3) [01000110] H12[10] rm[5..3] rd[2..0] */
121 ARMV5TE_MOV_RR_LH, /* mov(3) [01000101] H12[01] rm[5..3] rd[2..0] */
122 ARMV5TE_MOV_RR_HH, /* mov(3) [01000111] H12[11] rm[5..3] rd[2..0] */
123 ARMV5TE_MUL, /* mul [0100001101] rm[5..3] rd[2..0] */
124 ARMV5TE_MVN, /* mvn [0100001111] rm[5..3] rd[2..0] */
125 ARMV5TE_NEG, /* neg [0100001001] rm[5..3] rd[2..0] */
126 ARMV5TE_ORR, /* orr [0100001100] rm[5..3] rd[2..0] */
127 ARMV5TE_POP, /* pop [1011110] r[8..8] rl[7..0] */
128 ARMV5TE_PUSH, /* push [1011010] r[8..8] rl[7..0] */
129 ARMV5TE_ROR, /* ror [0100000111] rs[5..3] rd[2..0] */
130 ARMV5TE_SBC, /* sbc [0100000110] rm[5..3] rd[2..0] */
131 ARMV5TE_STMIA, /* stmia [11000] rn[10..8] reglist [7.. 0] */
132 ARMV5TE_STR_RRI5, /* str(1) [01100] imm_5[10..6] rn[5..3] rd[2..0] */
133 ARMV5TE_STR_RRR, /* str(2) [0101000] rm[8..6] rn[5..3] rd[2..0] */
134 ARMV5TE_STR_SP_REL, /* str(3) [10010] rd[10..8] imm_8[7..0] */
135 ARMV5TE_STRB_RRI5, /* strb(1) [01110] imm_5[10..6] rn[5..3] rd[2..0] */
136 ARMV5TE_STRB_RRR, /* strb(2) [0101010] rm[8..6] rn[5..3] rd[2..0] */
137 ARMV5TE_STRH_RRI5, /* strh(1) [10000] imm_5[10..6] rn[5..3] rd[2..0] */
138 ARMV5TE_STRH_RRR, /* strh(2) [0101001] rm[8..6] rn[5..3] rd[2..0] */
139 ARMV5TE_SUB_RRI3, /* sub(1) [0001111] imm_3[8..6] rn[5..3] rd[2..0]*/
140 ARMV5TE_SUB_RI8, /* sub(2) [00111] rd[10..8] imm_8[7..0] */
141 ARMV5TE_SUB_RRR, /* sub(3) [0001101] rm[8..6] rn[5..3] rd[2..0] */
142 ARMV5TE_SUB_SPI7, /* sub(4) [101100001] imm_7[6..0] */
143 ARMV5TE_SWI, /* swi [11011111] imm_8[7..0] */
144 ARMV5TE_TST, /* tst [0100001000] rm[5..3] rn[2..0] */
145 ARMV5TE_LAST,
146} Armv5teOpCode;
147
148/* Struct used to define the snippet posotions for each Thumb opcode */
149typedef struct Armv5teEncodingMap {
150 short skeleton;
151 struct {
152 int end;
153 int start;
154 } fieldLoc[3];
155 Armv5teOpCode opCode;
156 int operands;
157 char *name;
158 char* fmt;
159} Armv5teEncodingMap;
160
161extern Armv5teEncodingMap EncodingMap[ARMV5TE_LAST];
162
163/*
164 * Each instance of this struct holds a pseudo or real LIR instruction:
165 * - pesudo ones (eg labels and marks) and will be discarded by the assembler.
166 * - real ones will e assembled into Thumb instructions.
167 */
168typedef struct Armv5teLIR {
169 LIR generic;
170 Armv5teOpCode opCode;
171 int operands[3]; /* dest, src1, src2 */
172} Armv5teLIR;
173
174/* Utility macros to traverse the LIR/Armv5teLIR list */
175#define NEXT_LIR(lir) ((Armv5teLIR *) lir->generic.next)
176#define PREV_LIR(lir) ((Armv5teLIR *) lir->generic.prev)
177
178#define NEXT_LIR_LVALUE(lir) (lir)->generic.next
179#define PREV_LIR_LVALUE(lir) (lir)->generic.prev
180
Ben Cheng1efc9c52009-06-08 18:25:27 -0700[diff] [blame]181#define CHAIN_CELL_OFFSET_TAG 0xcdab
182
Bill Buzbeed45ba372009-06-15 17:00:57 -0700[diff] [blame^]183/* Create the TemplateOpcode enum */
184#define JIT_TEMPLATE(X) TEMPLATE_##X,
185typedef enum {
186#include "../../template/armv5te/TemplateOpList.h"
187/*
188 * For example,
189 * TEMPLATE_CMP_LONG,
190 * TEMPLATE_RETURN,
191 * ...
192 */
193 TEMPLATE_LAST_MARK,
194} TemplateOpCode;
195#undef JIT_TEMPLATE
196
Ben Chengba4fc8b2009-06-01 13:00:29 -0700[diff] [blame]197#endif /* _DALVIK_VM_COMPILER_CODEGEN_ARMV5TE_H */