blob: 4e2f9912c95364c49ae82153d67d96aa111b0323 [file] [log] [blame]
Torne (Richard Coles)09380292014-02-21 12:17:33 +00001/*
2 * Copyright (C) 2013 Google Inc. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are
6 * met:
7 *
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above
11 * copyright notice, this list of conditions and the following disclaimer
12 * in the documentation and/or other materials provided with the
13 * distribution.
14 * * Neither the name of Google Inc. nor the names of its
15 * contributors may be used to endorse or promote products derived from
16 * this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31
32/*
33 * typedef void (*PushAllRegistersCallback)(SafePointBarrier*, ThreadState*, intptr_t*);
34 * extern "C" void pushAllRegisters(SafePointBarrier*, ThreadState*, PushAllRegistersCallback)
35 */
36
37.type pushAllRegisters, %function
38.global pushAllRegisters
39.hidden pushAllRegisters
Torne (Richard Coles)d5428f32014-03-18 10:21:16 +000040#ifdef __thumb__
41/* In THUMB Mode jump to ARM stub via bx to ensure CPU mode switch.
42 * FIXME: This trampoline is provided to workaround bugs in
43 * the THUMB/ARM interworking that appear in the component build.
44 * When these issues are resolved this stub can be removed.
45 */
Ben Murdochaafa69c2014-04-03 12:30:15 +010046.align 2
Torne (Richard Coles)d5428f32014-03-18 10:21:16 +000047.code 16
48.thumb_func
Torne (Richard Coles)09380292014-02-21 12:17:33 +000049pushAllRegisters:
Torne (Richard Coles)d5428f32014-03-18 10:21:16 +000050 adr r3, pushAllRegistersARM
51 bx r3
52
53.type pushAllRegistersARM, %function
54.hidden pushAllRegistersARM
Ben Murdochaafa69c2014-04-03 12:30:15 +010055.align 4
Torne (Richard Coles)d5428f32014-03-18 10:21:16 +000056.code 32
57pushAllRegistersARM:
58#else
59/* ARM Mode */
Ben Murdochaafa69c2014-04-03 12:30:15 +010060.align 4
61.code 32
Torne (Richard Coles)d5428f32014-03-18 10:21:16 +000062pushAllRegisters:
63#endif
Torne (Richard Coles)09380292014-02-21 12:17:33 +000064 /* Push all callee-saved registers and save return address. */
65 push {r4-r11, lr}
66 /* Pass the two first arguments unchanged (r0, r1)
67 * and pass the stack pointer after pushing callee-saved
68 * registers to the callback function.
69 */
70 mov r3, r2
71 mov r2, sp
72 blx r3
73 /* Discard all the registers, and pop lr into pc which returns
74 * and switches mode if needed.
75 */
76 add sp, sp, #32
77 pop {pc}