blob: ad9cf9d80bbf2804f9e853876c7dbb1f619cba95 [file] [log] [blame]
kasperl@chromium.orga5551262010-12-07 12:49:48 +00001// Copyright 2010 the V8 project authors. All rights reserved.
2// Redistribution and use in source and binary forms, with or without
3// modification, are permitted provided that the following conditions are
4// met:
5//
6// * Redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer.
8// * Redistributions in binary form must reproduce the above
9// copyright notice, this list of conditions and the following
10// disclaimer in the documentation and/or other materials provided
11// with the distribution.
12// * Neither the name of Google Inc. nor the names of its
13// contributors may be used to endorse or promote products derived
14// from this software without specific prior written permission.
15//
16// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
28// This file is an internal atomic implementation, use atomicops.h instead.
29
30#ifndef V8_ATOMICOPS_INTERNALS_X86_MSVC_H_
31#define V8_ATOMICOPS_INTERNALS_X86_MSVC_H_
32
33#include "checks.h"
34#include "win32-headers.h"
35
machenbach@chromium.orgca2f2042014-03-10 10:03:12 +000036#if defined(V8_HOST_ARCH_64_BIT)
37// windows.h #defines this (only on x64). This causes problems because the
38// public API also uses MemoryBarrier at the public name for this fence. So, on
39// X64, undef it, and call its documented
40// (http://msdn.microsoft.com/en-us/library/windows/desktop/ms684208.aspx)
41// implementation directly.
42#undef MemoryBarrier
43#endif
44
kasperl@chromium.orga5551262010-12-07 12:49:48 +000045namespace v8 {
46namespace internal {
47
48inline Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32* ptr,
49 Atomic32 old_value,
50 Atomic32 new_value) {
51 LONG result = InterlockedCompareExchange(
52 reinterpret_cast<volatile LONG*>(ptr),
53 static_cast<LONG>(new_value),
54 static_cast<LONG>(old_value));
55 return static_cast<Atomic32>(result);
56}
57
58inline Atomic32 NoBarrier_AtomicExchange(volatile Atomic32* ptr,
59 Atomic32 new_value) {
60 LONG result = InterlockedExchange(
61 reinterpret_cast<volatile LONG*>(ptr),
62 static_cast<LONG>(new_value));
63 return static_cast<Atomic32>(result);
64}
65
66inline Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr,
67 Atomic32 increment) {
68 return InterlockedExchangeAdd(
69 reinterpret_cast<volatile LONG*>(ptr),
70 static_cast<LONG>(increment)) + increment;
71}
72
73inline Atomic32 NoBarrier_AtomicIncrement(volatile Atomic32* ptr,
74 Atomic32 increment) {
75 return Barrier_AtomicIncrement(ptr, increment);
76}
77
78#if !(defined(_MSC_VER) && _MSC_VER >= 1400)
79#error "We require at least vs2005 for MemoryBarrier"
80#endif
81inline void MemoryBarrier() {
machenbach@chromium.orgca2f2042014-03-10 10:03:12 +000082#if defined(V8_HOST_ARCH_64_BIT)
83 // See #undef and note at the top of this file.
84 __faststorefence();
85#else
kasperl@chromium.orga5551262010-12-07 12:49:48 +000086 // We use MemoryBarrier from WinNT.h
87 ::MemoryBarrier();
machenbach@chromium.orgca2f2042014-03-10 10:03:12 +000088#endif
kasperl@chromium.orga5551262010-12-07 12:49:48 +000089}
90
91inline Atomic32 Acquire_CompareAndSwap(volatile Atomic32* ptr,
92 Atomic32 old_value,
93 Atomic32 new_value) {
94 return NoBarrier_CompareAndSwap(ptr, old_value, new_value);
95}
96
97inline Atomic32 Release_CompareAndSwap(volatile Atomic32* ptr,
98 Atomic32 old_value,
99 Atomic32 new_value) {
100 return NoBarrier_CompareAndSwap(ptr, old_value, new_value);
101}
102
103inline void NoBarrier_Store(volatile Atomic32* ptr, Atomic32 value) {
104 *ptr = value;
105}
106
107inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) {
108 NoBarrier_AtomicExchange(ptr, value);
109 // acts as a barrier in this implementation
110}
111
112inline void Release_Store(volatile Atomic32* ptr, Atomic32 value) {
113 *ptr = value; // works w/o barrier for current Intel chips as of June 2005
114 // See comments in Atomic64 version of Release_Store() below.
115}
116
117inline Atomic32 NoBarrier_Load(volatile const Atomic32* ptr) {
118 return *ptr;
119}
120
121inline Atomic32 Acquire_Load(volatile const Atomic32* ptr) {
122 Atomic32 value = *ptr;
123 return value;
124}
125
126inline Atomic32 Release_Load(volatile const Atomic32* ptr) {
127 MemoryBarrier();
128 return *ptr;
129}
130
131#if defined(_WIN64)
132
133// 64-bit low-level operations on 64-bit platform.
134
135STATIC_ASSERT(sizeof(Atomic64) == sizeof(PVOID));
136
137inline Atomic64 NoBarrier_CompareAndSwap(volatile Atomic64* ptr,
138 Atomic64 old_value,
139 Atomic64 new_value) {
140 PVOID result = InterlockedCompareExchangePointer(
141 reinterpret_cast<volatile PVOID*>(ptr),
142 reinterpret_cast<PVOID>(new_value), reinterpret_cast<PVOID>(old_value));
143 return reinterpret_cast<Atomic64>(result);
144}
145
146inline Atomic64 NoBarrier_AtomicExchange(volatile Atomic64* ptr,
147 Atomic64 new_value) {
148 PVOID result = InterlockedExchangePointer(
149 reinterpret_cast<volatile PVOID*>(ptr),
150 reinterpret_cast<PVOID>(new_value));
151 return reinterpret_cast<Atomic64>(result);
152}
153
154inline Atomic64 Barrier_AtomicIncrement(volatile Atomic64* ptr,
155 Atomic64 increment) {
156 return InterlockedExchangeAdd64(
157 reinterpret_cast<volatile LONGLONG*>(ptr),
158 static_cast<LONGLONG>(increment)) + increment;
159}
160
161inline Atomic64 NoBarrier_AtomicIncrement(volatile Atomic64* ptr,
162 Atomic64 increment) {
163 return Barrier_AtomicIncrement(ptr, increment);
164}
165
166inline void NoBarrier_Store(volatile Atomic64* ptr, Atomic64 value) {
167 *ptr = value;
168}
169
170inline void Acquire_Store(volatile Atomic64* ptr, Atomic64 value) {
171 NoBarrier_AtomicExchange(ptr, value);
172 // acts as a barrier in this implementation
173}
174
175inline void Release_Store(volatile Atomic64* ptr, Atomic64 value) {
176 *ptr = value; // works w/o barrier for current Intel chips as of June 2005
177
178 // When new chips come out, check:
179 // IA-32 Intel Architecture Software Developer's Manual, Volume 3:
180 // System Programming Guide, Chatper 7: Multiple-processor management,
181 // Section 7.2, Memory Ordering.
182 // Last seen at:
183 // http://developer.intel.com/design/pentium4/manuals/index_new.htm
184}
185
186inline Atomic64 NoBarrier_Load(volatile const Atomic64* ptr) {
187 return *ptr;
188}
189
190inline Atomic64 Acquire_Load(volatile const Atomic64* ptr) {
191 Atomic64 value = *ptr;
192 return value;
193}
194
195inline Atomic64 Release_Load(volatile const Atomic64* ptr) {
196 MemoryBarrier();
197 return *ptr;
198}
199
200inline Atomic64 Acquire_CompareAndSwap(volatile Atomic64* ptr,
201 Atomic64 old_value,
202 Atomic64 new_value) {
203 return NoBarrier_CompareAndSwap(ptr, old_value, new_value);
204}
205
206inline Atomic64 Release_CompareAndSwap(volatile Atomic64* ptr,
207 Atomic64 old_value,
208 Atomic64 new_value) {
209 return NoBarrier_CompareAndSwap(ptr, old_value, new_value);
210}
211
212
213#endif // defined(_WIN64)
214
215} } // namespace v8::internal
216
217#endif // V8_ATOMICOPS_INTERNALS_X86_MSVC_H_